FDMS3604AS PowerTrench® Power Stage 30 V Asymmetric Dual N-Channel MOSFET Features General Description Q1: N-Channel This device includes two specialized N-Channel MOSFETs in a Max rDS(on) = 8 mΩ at VGS = 10 V, ID = 13 A dual PQFN package. The switch node has been internally Max rDS(on) = 11 mΩ at VGS = 4.5 V, ID = 11 A connected to enable easy placement and routing of synchronous buck converters. The control MOSFET (Q1) and synchronous Q2: N-Channel SyncFET (Q2) have been designed to provide optimal power Max rDS(on) = 2.6 mΩ at VGS = 10 V, ID = 23 A efficiency. Max rDS(on) = 3.5 mΩ at VGS = 4.5 V, ID = 21 A Applications Low inductance packaging shortens rise/fall times, resulting in lower switching losses Computing MOSFET integration enables optimum layout for lower circuit inductance and reduced switch node ringing Communications General Purpose Point of Load RoHS Compliant Notebook VCORE Sever G1 D1 D1 D1 D1 PHASE (S1/D2) G2 S2 S2 Top Power 56 S2 Bottom S2 5 S2 6 S2 7 G2 8 Q2 4 D1 PHASE 3 D1 2 D1 1 G1 Q1 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current ID TJ, TSTG Units V V (Note 3) ±20 ±20 TC = 25 °C 30 40 -Continuous (Silicon limited) TC = 25 °C 60 130 -Continuous TA = 25 °C 131a 231b -Pulsed PD Q2 30 -Continuous (Package limited) Single Pulse Avalanche Energy EAS Q1 30 40 100 404 1125 Power Dissipation for Single Operation TA = 25 °C 2.21a 2.51b Power Dissipation for Single Operation TA = 25 °C 1.01c 1.01d Operating and Storage Junction Temperature Range A mJ W -55 to +150 °C Thermal Characteristics RθJA Thermal Resistance, Junction to Ambient 571a 501b RθJA Thermal Resistance, Junction to Ambient 1251c 1201d RθJC Thermal Resistance, Junction to Case 3.5 2 °C/W Package Marking and Ordering Information Device Marking 22CA N7CC Device Package Reel Size Tape Width Quantity FDMS3604AS Power 56 13 ” 12 mm 3000 units ©2011 Fairchild Semiconductor Corporation FDMS3604AS Rev.C4 1 www.fairchildsemi.com FDMS3604AS PowerTrench® Power Stage September 2011 Symbol Parameter Test Conditions Type Min 30 30 Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ID = 1 mA, VGS = 0 V Q1 Q2 ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C ID = 10 mA, referenced to 25 °C Q1 Q2 IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V Q1 Q2 1 500 μA μA IGSS Gate to Source Leakage Current, Forwad VGS = 20 V, VDS= 0 V Q1 Q2 100 100 nA nA 2.7 3 V V 15 12 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA VGS = VDS, ID = 1 mA Q1 Q2 ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C ID = 10 mA, referenced to 25 °C Q1 Q2 -6 -5 VGS = 10 V, ID = 13 A VGS = 4.5 V, ID = 11 A VGS = 10 V, ID = 13 A , TJ = 125 °C Q1 5.8 8.5 7.8 8 11 10.8 VGS = 10 V, ID = 23 A VGS = 4.5 V, ID = 21 A VGS = 10 V, ID = 23 A , TJ = 125 °C Q2 2 2.6 2.6 2.6 3.5 4 VDS = 5 V, ID = 13 A VDS = 5 V, ID = 23 A Q1 Q2 61 130 Q1: VDS = 15 V, VGS = 0 V, f = 1 MHZ Q1 Q2 1273 3078 1695 4095 pF Q1 Q2 461 1169 615 1555 pF Q1 Q2 50 98 75 150 pF 0.6 0.8 2 3 Ω rDS(on) gFS Drain to Source On Resistance Forward Transconductance 1.1 1.1 2 1.8 mV/°C mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance Q2: VDS = 15 V, VGS = 0 V, f = 1 MHZ Q1 Q2 0.2 0.2 Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg Total Gate Charge Qg Total Gate Charge Qgs Gate to Source Gate Charge Qgd Gate to Drain “Miller” Charge ©2011 Fairchild Semiconductor Corporation FDMS3604AS Rev.C4 Q1: VDD = 15 V, ID = 13 A, RGEN = 6 Ω Q2: VDD = 15 V, ID = 23 A, RGEN = 6 Ω VGS = 0 V to 10 V Q1 VDD = 15 V, VGS = 0 V to 4.5 V ID = 13 A Q2 VDD = 15 V, ID = 23 A 2 Q1 Q2 8.2 13 16 23 ns Q1 Q2 2.5 4.8 10 10 ns Q1 Q2 20 31 32 50 ns Q1 Q2 2.2 3.4 10 10 ns Q1 Q2 21 47 29 66 nC Q1 Q2 10 22 14 31 nC Q1 Q2 3.9 9 nC Q1 Q2 3.1 5.5 nC www.fairchildsemi.com FDMS3604AS PowerTrench® Power Stage Electrical Characteristics TJ = 25 °C unless otherwise noted Symbol Parameter Test Conditions Type Min Typ Max Units Q1 Q2 0.8 0.8 1.2 1.2 V Q1 Q2 25 32 40 51 ns Q1 Q2 9 39 18 62 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 13 A VGS = 0 V, IS = 23A (Note 2) (Note 2) Q1 IF = 13 A, di/dt = 100 A/μs Q2 IF = 23 A, di/dt = 300 A/μs Notes: 1: RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. b. 50 °C/W when mounted on a 1 in2 pad of 2 oz copper a. 57 °C/W when mounted on a 1 in2 pad of 2 oz copper c. 125 °C/W when mounted on a minimum pad of 2 oz copper d. 120 °C/W when mounted on a minimum pad of 2 oz copper 2: Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3: As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied. 4: EAS of 40 mJ is based on starting TJ = 25 oC; N-ch: L = 1 mH, IAS = 9 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.3 mH, IAS = 14 A. 5: EAS of 112 mJ is based on starting TJ = 25 oC; N-ch: L = 1 mH, IAS = 15 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.3 mH, IAS = 22 A. ©2011 Fairchild Semiconductor Corporation FDMS3604AS Rev.C4 3 www.fairchildsemi.com FDMS3604AS PowerTrench® Power Stage Electrical Characteristics TJ = 25 °C unless otherwise noted 4 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 40 ID, DRAIN CURRENT (A) VGS = 10 V VGS = 6 V 30 VGS = 4.5 V VGS = 4 V 20 VGS = 3.5 V 10 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0.0 0.2 0.4 0.6 0.8 3 VGS = 4 V 2 VGS = 4.5 V VGS = 6 V 1 0 1.0 VGS = 10 V 0 10 20 ID, DRAIN CURRENT (A) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 1. On Region Characteristics rDS(on), DRAIN TO 1.2 1.0 0.8 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 1.4 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 16 ID = 13 A 12 TJ = 125 oC 8 4 TJ = 25 oC 0 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On Resistance vs Junction Temperature Figure 4. On-Resistance vs Gate to Source Voltage 40 40 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX IS, REVERSE DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 40 20 ID = 13 A VGS = 10 V -50 30 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.6 0.6 -75 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 3.5 V 30 VDS = 5 V TJ = 150 oC 20 TJ = 25 oC 10 TJ = -55 oC 0 1.5 2.0 2.5 3.0 3.5 1 TJ = 150 oC TJ = 25 oC 0.1 0.01 TJ = -55 oC 0.001 0.0 4.0 VGS, GATE TO SOURCE VOLTAGE (V) 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics ©2011 Fairchild Semiconductor Corporation FDMS3604AS Rev.C4 VGS = 0 V 10 Figure 6. Source to Drain Diode Forward Voltage vs Source Current 4 www.fairchildsemi.com FDMS3604AS PowerTrench® Power Stage Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted 2000 ID = 13 A VDD = 10 V 1000 Ciss 8 VDD = 15 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 6 VDD = 20 V 4 Coss 100 Crss 2 f = 1 MHz VGS = 0 V 0 0 5 10 15 20 10 0.1 25 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 20 100 o ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) RθJC = 3.5 C/W 10 TJ = 25 oC TJ = 100 oC TJ = 125 oC 1 0.01 0.1 1 80 VGS = 10 V 60 VGS = 4.5 V 40 20 Limited by Package 10 0 25 100 50 P(PK), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) 150 1000 100us 10 1 ms 10 ms THIS AREA IS LIMITED BY rDS(on) 100 ms 1s SINGLE PULSE TJ = MAX RATED 10s RθJA = 125 oC/W DC TA = 25 oC 0.01 0.01 125 Figure 10. Maximum Continuous Drain Current vs Case Temperature 100 0.1 100 o Figure 9. Unclamped Inductive Switching Capability 1 75 TC, CASE TEMPERATURE ( C) tAV, TIME IN AVALANCHE (ms) 0.1 1 10 100 200 100 TA = 25 oC 10 1 0.1 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, PULSE WIDTH (sec) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 11. Forward Bias Safe Operating Area ©2011 Fairchild Semiconductor Corporation FDMS3604AS Rev.C4 SINGLE PULSE RθJA = 125 oC/W Figure 12. Single Pulse Maximum Power Dissipation 5 www.fairchildsemi.com FDMS3604AS PowerTrench® Power Stage Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted 2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 125 C/W (Note 1c) 0.001 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2011 Fairchild Semiconductor Corporation FDMS3604AS Rev.C4 6 www.fairchildsemi.com FDMS3604AS PowerTrench® Power Stage Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted 25 oC unlenss otherwise noted 8 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 100 VGS = 10 V VGS = 4.5 V ID, DRAIN CURRENT (A) 80 VGS = 4 V 60 VGS = 3.5 V 40 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 20 VGS = 3 V 0 0.0 0.2 0.4 0.6 0.8 VGS = 3 V 6 VGS = 3.5 V 4 VGS = 10 V 0 1.0 0 20 40 60 80 100 ID, DRAIN CURRENT (A) Figure 14. On-Region Characteristics Figure 15. Normalized on-Resistance vs Drain Current and Gate Voltage 1.6 12 ID = 23 A VGS = 10 V rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 -75 -50 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 4.5 V VGS = 4 V 2 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 IS, REVERSE DRAIN CURRENT (A) 60 TJ = 125 oC 40 TJ = 25 oC 20 TJ = -55 oC 3.0 3.5 TJ = 125 oC 3 TJ = 25 oC 2 4 6 8 10 VGS = 0 V 10 TJ = 125 oC 1 TJ = 25 oC 0.1 TJ = -55 oC 0.01 0.001 0.0 4.0 VGS, GATE TO SOURCE VOLTAGE (V) 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 19. Source to Drain Diode Forward Voltage vs Source Current Figure 18. Transfer Characteristics ©2011 Fairchild Semiconductor Corporation FDMS3604AS Rev.C4 6 100 VDS = 5 V 2.5 ID = 23 A Figure 17. On-Resistance vs Gate to Source Voltage 80 2.0 9 VGS, GATE TO SOURCE VOLTAGE (V) PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 1.5 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) Figure 16. Normalized On-Resistance vs Junction Temperature ID, DRAIN CURRENT (A) PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 7 www.fairchildsemi.com FDMS3604AS PowerTrench® Power Stage Typical Characteristics (Q2 N-Channel) TJ = 10000 ID = 23 A 8 Ciss VDD = 10 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 6 VDD = 15 V 4 VDD = 20 V 1000 Coss 100 Crss 2 f = 1 MHz VGS = 0 V 0 0 10 20 30 40 10 0.1 50 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 21. Capacitance vs Drain to Source Voltage Figure 20. Gate Charge Characteristics 50 160 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) o RθJC = 2 C/W TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC 120 VGS = 10 V 80 VGS = 4.5 V 40 Limited by Package 1 0.01 0.1 1 10 100 0 25 1000 50 150 1000 P(PK), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) 125 Figure 23. Maximun Continuous Drain Current vs Case Temperature 200 100 1 ms 10 0.1 100 o Figure 22. Unclamped Inductive Switching Capability 1 75 TC, CASE TEMPERATURE ( C) tAV, TIME IN AVALANCHE (ms) 10 ms THIS AREA IS LIMITED BY rDS(on) 100 ms 1s SINGLE PULSE TJ = MAX RATED 10s RθJA = 120 oC/W DC TA = 25 oC 0.01 0.01 0.1 1 10 100200 100 TA = 25 oC 10 1 0.1 -3 10 -2 10 -1 10 1 10 100 1000 t, PULSE WIDTH (sec) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 25. Single Pulse Maximum Power Dissipation Figure 24. Forward Bias Safe Operating Area ©2011 Fairchild Semiconductor Corporation FDMS3604AS Rev.C4 SINGLE PULSE RθJA = 120 oC/W 8 www.fairchildsemi.com FDMS3604AS PowerTrench® Power Stage Typical Characteristics (Q2 N-Channel) TJ = 25 oC unless otherwise noted 2 TJ = 25 oC unless otherwise noted DUTY CYCLE-DESCENDING ORDER NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 SINGLE PULSE 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 120 C/W (Note 1d) 0.001 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 26. Junction-to-Ambient Transient Thermal Response Curve ©2011 Fairchild Semiconductor Corporation FDMS3604AS Rev.C4 9 www.fairchildsemi.com FDMS3604AS PowerTrench® Power Stage Typical Characteristics (Q2 N-Channel) SyncFET Schottky body diode Characteristics Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device. Fairchild’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 27 shows the reverse recovery characteristic of the FDMS3604AS. -2 IDSS, REVERSE LEAKAGE CURRENT (A) 25 20 CURRENT (A) didt = 300 A/μs 15 10 5 0 -5 0 50 100 150 200 TIME (ns) TJ = 125 oC -3 10 TJ = 100 oC -4 10 -5 10 TJ = 25 oC -6 10 0 5 10 15 20 25 30 VDS, REVERSE VOLTAGE (V) Figure 28. SyncFET body diode reverse leakage versus drain-source voltage Figure 27. FDMS3604AS SyncFET body diode reverse recovery characteristic ©2011 Fairchild Semiconductor Corporation FDMS3604AS Rev.C4 10 10 www.fairchildsemi.com FDMS3604AS PowerTrench® Power Stage Typical Characteristics (continued) 1. Switch Node Ringing Suppression Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage solution rings significantly less than competitor solutions under the same set of test conditions. Competitors solution Power Stage Device Figure 29. Power Stage phase node rising edge, High Side Turn on *Patent Pending ©2011 Fairchild Semiconductor Corporation FDMS3604AS Rev.C4 11 www.fairchildsemi.com FDMS3604AS PowerTrench® Power Stage Application Information FDMS3604AS PowerTrench® Power Stage Figure 30. Shows the Power Stage in a buck converter topology 2. Recommended PCB Layout Guidelines As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2), should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout procedure is discussed below to maximize the electrical and thermal performance of the part. Figure 31. Recommended PCB Layout ©2011 Fairchild Semiconductor Corporation FDMS3604AS Rev.C4 12 www.fairchildsemi.com 1. Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic inductance and high frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close to the part between D1 and S2. Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected depending upon the application. 2. The PHASE copper trace serves two purposes; In addition to being the current path from the Power Stage package to the output inductor (L), it also serves as heat sink for the lower FET in the Power Stage package. The trace should be short and wide enough to present a low resistance path for the high current flow between the Power Stage and the inductor. This is done to minimize conduction losses and limit temperature rise. Please note that the PHASE node is a high voltage and high frequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. The reference layout in figure 31 shows a good balance between the thermal and electrical performance of Power Stage. 3. Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace resistance. A shorter and wider PHASE trace to the inductor reduces the conduction loss. Preferably the Power Stage should be directly in line (as shown in figure 31) with the inductor for space savings and compactness. 4. The PowerTrench® Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing. It allows the part to operate well within the breakdown voltage limits. This eliminates the need to have an external snubber circuit in most cases. If the designer chooses to use an RC snubber, it should be placed close to the part between the PHASE pad and S2 pins to dampen the high-frequency ringing. 5. The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side gates through a wide trace connection. This eliminates the effect of parasitic inductance and resistance between the driver and the MOSFET and turns the devices on and off as efficiently as possible. At higher-frequency operation this impedance can limit the gate current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional switching losses. Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This provides a very compact path for the drive signals and improves efficiency of the part. 6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET. 7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction. Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected from the backside via a network of low inductance vias. ©2011 Fairchild Semiconductor Corporation FDMS3604AS Rev.C4 13 www.fairchildsemi.com FDMS3604AS PowerTrench® Power Stage Following is a guideline, not a requirement which the PCB designer should consider: FDMS3604AS PowerTrench® Power Stage Dimensional Outline and Pad Layout ©2011 Fairchild Semiconductor Corporation FDMS3604AS Rev.C4 14 www.fairchildsemi.com tm tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used here in: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ANTI-COUNTERFEITING POLICY Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website, www.Fairchildsemi.com, under Sales Support. Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are experiencing counterfeiting of their parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed application, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild’s full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I55 ©2011 Fairchild Semiconductor Corporation FDMS3604AS Rev.C4 15 www.fairchildsemi.com FDMS3604AS PowerTrench® Power Stage TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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