FDMS7660 N-Channel PowerTrench® MOSFET 30 V, 2.8 mΩ Features General Description This N-Channel MOSFET has been designed specifically to improve the overall efficiency and to minimize switch node ringing of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(on), fast switching speed and body diode reverse recovery performance. Max rDS(on) = 2.8 mΩ at VGS = 10 V, ID = 25 A Max rDS(on) = 3.5 mΩ at VGS = 4.5 V, ID = 19 A Advanced Package and Silicon combination for low rDS(on) and high efficiency Next generation enhanced body diode technology, engineered for soft recovery. Provides Schottky-like performance with minimum EMI in sync buck converter applications Applications IMVP Vcore Switching for Notebook MSL1 robust package design VRM Vcore Switching for Desktop and Server 100% UIL tested OringFET / Load Switch RoHS Compliant DC-DC Conversion Bottom Top S D D D Pin 1 S S G D 5 4 G D 6 3 S D 7 2 S D 8 1 S D Power 56 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage (Note 4) Drain Current -Continuous (Package limited) ID TC = 25 °C -Continuous (Silicon limited) TC = 25 °C -Continuous TA = 25 °C PD TJ, TSTG Units V ±20 V 42 144 (Note 1a) 25 (Note 3) 128 -Pulsed A 150 Single Pulse Avalanche Energy EAS Ratings 30 Power Dissipation TC = 25 °C Power Dissipation TA = 25 °C 78 (Note 1a) Operating and Storage Junction Temperature Range 2.5 -55 to +150 mJ W °C Thermal Characteristics RθJC Thermal Resistance, Junction to Case RθJA Thermal Resistance, Junction to Ambient 1.6 (Note 1a) 50 °C/W Package Marking and Ordering Information Device Marking FDMS7660 Device FDMS7660 ©2009 Fairchild Semiconductor Corporation FDMS7660 Rev. D Package Power 56 1 Reel Size 13 ’’ Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMS7660 N-Channel PowerTrench® MOSFET April 2009 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 µA, VGS = 0 V ∆BVDSS ∆TJ Breakdown Voltage Temperature Coefficient ID = 250 µA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 1 µA IGSS Gate to Source Leakage Current, Forward VGS = 20 V, VDS = 0 V 100 nA 3.0 V 30 V 17 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 µA ∆VGS(th) ∆TJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 µA, referenced to 25 °C rDS(on) Static Drain to Source On Resistance gFS Forward Transconductance 1.25 1.9 -7 mV/°C VGS = 10 V , ID = 25 A 1.9 2.8 VGS = 4.5 V, ID = 19 A 2.7 3.5 VGS = 10 V, ID = 25 A, TJ = 125 °C 2.5 3.7 VDS = 5 V, ID = 25 A 250 mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance VDS = 15 V, VGS = 0 V, f = 1 MHz 4185 5565 1380 1830 pF pF 125 190 pF 0.9 2.0 Ω 17 31 ns 9 18 ns 37 60 ns 7 13 ns nC Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg Total Gate Charge VGS = 0 V to 10 V 60 84 Qg Total Gate Charge 27 38 Qgs Gate to Source Charge VGS = 0 V to 4.5 V VDD = 15 V, ID = 25 A Qgd Gate to Drain “Miller” Charge VDD = 15 V, ID = 25A, VGS = 10 V, RGEN = 6 Ω nC 12.3 nC 7.2 nC Drain-Source Diode Characteristics VGS = 0 V, IS = 2.1 A (Note 2) 0.7 0.95 VGS = 0 V, IS = 25 A (Note 2) 0.8 1.1 VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time 46 74 ns Qrr Reverse Recovery Charge 26 42 nC ta Reverse Recovery Fall Time 19 nC tb Reverse Recovery Rise Time 27 nC S Softness (tb/ta) 1.4 trr Reverse Recovery Time Qrr Reverse Recovery Charge IF = 25 A, di/dt = 100 A/µs IF = 25 A, di/dt = 300 A/µs V 36 58 ns 43 68 nC Notes: 1. RθJA is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. a. 50 °C/W when mounted on a 1 in2 pad of 2 oz copper. b. 125 °C/W when mounted on a minimum pad of 2 oz copper. 2. Pulse Test: Pulse Width < 300 µs, Duty cycle < 2.0%. 3. EAS of 128 mJ is based on starting TJ = 25 °C, L = 1 mH, IAS = 16 A, VDD = 27 V, VGS = 10 V. 100% test at L = 0.3 mH, IAS = 23 A. 4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied. ©2009 Fairchild Semiconductor Corporation FDMS7660 Rev. D 2 www.fairchildsemi.com FDMS7660 N-Channel PowerTrench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted 150 14 VGS = 4.5 V 120 ID, DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 10 V VGS = 4 V 90 VGS = 3.5 V 60 PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX 30 VGS = 3 V 0 0 0.5 1.0 1.5 VDS, DRAIN TO SOURCE VOLTAGE (V) 12 VGS = 3 V 8 VGS = 3.5 V 6 4 VGS = 4 V VGS = 4.5 V 0 2.0 0 30 60 90 120 150 ID, DRAIN CURRENT (A) Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 10 ID = 25 A VGS = 10 V rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 0.6 -75 SOURCE ON-RESISTANCE (mΩ) 1.6 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 10 V 2 Figure 1. On-Region Characteristics PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX 8 ID = 25 A 6 4 TJ = 125 oC 2 TJ = 25 oC 0 -50 2 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On- Resistance vs Junction Temperature Figure 4. On-Resistance vs Gate to Source Voltage 150 IS, REVERSE DRAIN CURRENT (A) 200 PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX 120 ID, DRAIN CURRENT (A) PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX 10 VDS = 5 V 90 TJ = 150 oC 60 TJ = 25 oC 30 TJ = -55 oC 0 1 2 3 4 VGS = 0 V TJ = 150 oC 10 TJ = 25 oC 1 TJ = -55 oC 0.1 0.2 5 VGS, GATE TO SOURCE VOLTAGE (V) 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics ©2009 Fairchild Semiconductor Corporation FDMS7660 Rev. D 100 Figure 6. Source to Drain Diode Forward Voltage vs Source Current 3 www.fairchildsemi.com FDMS7660 N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25°C unless otherwise noted 10000 ID = 25 A Ciss 8 VDD = 15 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 6 VDD = 20 V VDD = 10 V 4 1000 Coss 100 Crss 2 f = 1 MHz VGS = 0 V 10 0.1 0 0 15 30 45 60 1 Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics 150 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC 120 VGS = 10 V 90 VGS = 4.5 V 60 30 o Limited by Package 1 0.01 0.1 1 10 100 0 25 1000 50 P(PK), PEAK TRANSIENT POWER (W) 100 100 us 10 1 ms 0.1 10 ms 100 ms 1s 10 s RθJA = 125 oC/W DC o TA = 25 C 0.01 0.01 0.1 1 10 100 125 150 2000 1000 VGS = 10 V SINGLE PULSE RθJA = 125 oC/W 100 TA = 25 oC 10 1 0.5 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, PULSE WIDTH (sec) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 11. Forward Bias Safe Operating Area ©2009 Fairchild Semiconductor Corporation FDMS7660 Rev. D 100 Figure 10. Maximum Continuous Drain Current vs Case Temperature 500 SINGLE PULSE TJ = MAX RATED 75 o Figure 9. Unclamped Inductive Switching Capability THIS AREA IS LIMITED BY rDS(on) RθJC = 1.6 C/W Tc, CASE TEMPERATURE ( C) tAV, TIME IN AVALANCHE (ms) 1 30 Figure 8. Capacitance vs Drain to Source Voltage 100 ID, DRAIN CURRENT (A) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 12. Single Pulse Maximum Power Dissipation 4 www.fairchildsemi.com FDMS7660 N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25°C unless otherwise noted NORMALIZED THERMAL IMPEDANCE, ZθJA 2 1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 0.1 PDM 0.01 t1 0.001 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 125 C/W 0.0001 -4 10 -3 -2 10 -1 10 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve Figure 15. 30 25 CURRENT (A) 20 di/dt = 300 A/µs 15 10 5 0 -5 0 40 80 120 160 200 240 TIME (ns) Figure 14. Body Diode Reverse Recovery Characteristics ©2009 Fairchild Semiconductor Corporation FDMS7660 Rev. D 5 www.fairchildsemi.com FDMS7660 N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25°C unless otherwise noted FDMS7660 N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout ©2009 Fairchild Semiconductor Corporation FDMS7660 Rev. D 6 www.fairchildsemi.com tm tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. 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Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I40 ©2009 Fairchild Semiconductor Corporation FDMS7660 Rev. D 7 www.fairchildsemi.com FDMS7660 N-Channel PowerTrench® MOSFET TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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