ONSEMI NTHD2110TT1G

AND PIN A
NTHD2110T
Power MOSFET
-12 V, -6.4 A, Single P-Channel +TVS,
ChipFETt Package
Features
•Low RDS(on) MOSFET and TVS Diode ChipFET Package
•Integrated Drain Side TVS for 15 kV Contact Discharge ESD
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Protection
•1.8 V Gate Rating
•This is a Pb-Free Device
RDS(on) MAX
V(BR)DSS
ID MAX
40 mW @ -4.5 V
Applications
•Battery Switch and Load Management Applications in Portable
53 mW @ -2.5 V
-12 V
80 mW @ -1.8 V
Equipment
MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
-6.4 A
TVS
Symbol
Value
Unit
VRWM
VC @ MAX IPP
IPP MAX
Drain-to-Source Voltage
VDSS
-12
V
12
21.5
6.2 A
Gate-to-Source Voltage
VGS
"8
V
ID
-4.5
A
Continuous Drain
Current (Note 1)
Steady
State
TA = 25°C
t≤5s
TA = 25°C
Power Dissipation
(Note 1)
Steady
State
TA = 85°C
-3.2
-6.4
PD
W
1.1
G
TA = 25°C
t≤5s
2.3
TJ,
TSTG
-55 to
150
°C
Storage Temperature Range
TJ
-55 to
150
°C
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 seconds)
TL
260
°C
Operating Junction and Storage Temperature
8
ChipFET
CASE 1206A
STYLE 6
Value
Unit
PPK
150
W
Human Body Model (HBM)
Machine Model (MM)
IEC 61000-4-2 Specification (Contact)
ESD
16
400
30
kV
V
kV
PIN
CONNECTIONS
1
8
2
7
A
D
C/D
1
D
2
D
3
S
4
6
D
THERMAL RESISTANCE RATINGS
MARKING
DIAGRAM
8
FTZ M
G
Symbol
7
6
3
Parameter
Symbol
Max
Junction-to-Ambient – Steady State (Note 1)
RqJA
110
Junction-to-Ambient – t ≤ 5 s (Note 1)
RqJA
55
Unit
°C/W
Junction-to-Ambient - Steady State Min Pad
225
RqJA
(Note 3)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface-mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq
[1 oz] including traces).
2. Nonrepetitive Current Pulse per Figure 11.
3. Surface Mounted on FR4 board using 1 in sq size (Cu area = 1.127 in sq
[1 oz] included traces).
March, 2008 - Rev. 0
TVS Diode
1
Peak Power Dissipation
8 x 20 ms Double Exponential Waveform
(Note 2)
© Semiconductor Components Industries, LLC, 2008
C
D
P-Channel MOSFET
TVS MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
A
S
1
G
4
FTZ
M
G
5
5
= Specific Device Code
= Month Code
= Pb-Free Package
ORDERING INFORMATION
Device
Package
Shipping†
NTHD2110TT1G
ChipFET
(Pb-Free)
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NTHD2110T/D
NTHD2110T
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Test Condition
Min
V(Br)DSS
VGS = 0 Vdc, ID = -250 mA
-12
Typ
Max
Unit
OFF CHARACTERISTICS
Drain-to-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate-to-Source Leakage Current
IDSS
VDS = -12 V,
VGS = 0 V
V
TJ = 25°C
-1.0
TJ = 85°C
-5.0
VDS = 0 V, VGS = "8.0 V
IGSS
"0.1
mA
mA
ON CHARACTERISTICS (Note 6)
Gate Threshold Voltage
VGS(th)
VDS = VGS, ID = -250 mA
-0.85
V
Drain-to-Source On-Resistance
RDS(on)
VGS = -4.5 V, ID = -6.4 A
33
40
mW
VGS = -2.5 V, ID = -2.0 A
42
53
VGS = -1.8 V, ID = -1.7 A
57
80
VDS = -5.0 V, ID = -6.4 A
13.7
S
1072
pF
Forward Transconductance
gFS
-0.40
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
Ciss
VDS = -6.0 V, VGS = 0 V
f = 1.0 MHz
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
134
Total Gate Charge
QG(TOT)
10.5
Threshold Gate Charge
QG(TH)
Gate-to-Source Charge
QGS
Gate-to-Drain Charge
QGD
VGS = -4.5 V, VDS = -6.0 V,
ID = -6.4 A
260
14
nC
0.6
1.3
2.8
SWITCHING CHARACTERISTICS (Note 7)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
td(on)
tr
VDD = -6.0 V, VGS = -4.5 V,
ID = -1.0 A, RG = 6.0 W
ns
7.5
8.6
td(off)
99.7
tf
49.8
DRAIN-SOURCE DIODE CHARACTERISTICS
Diode Forward Voltage
VSD
IS = -1.7 A,
VGS = 0 V
TJ = 25°C
-0.7
TJ = 125°C
-0.6
-1.0
V
Reverse Recovery Time
tRR
VGS = 0 V,
dIS / dt = 100 A/ms, IS = -1.7 A
41.7
ns
Reverse Recovery Charge
QRR
VGS = 0 V,
dIS / dt = 100 A/ms, IS = -1.7 A
22
nC
4.
5.
6.
7.
Surface Mounted on FR4 board using 1 in sq size (Cu area = 1.127 in sq [1 oz] included traces).
Surface mounted on FR4 board using the minimum recommended pad size.
Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
Switching characteristics are independent of operating junction temperatures.
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2
NTHD2110T
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Test Condition
Min
Typ
Max
Unit
TVS DIODE
Reverse Working Voltage (Note 8)
Breakdown Voltage (Note 9)
VRWM
12
VBR
IT = 1 mA
Reverse Leakage Current
IR
VRWM = 12 V
Clamping Voltage (Note 10)
VC
Clamping Voltage (Note 10)
V
14.5
15.7
V
10
nA
IPP = 1 A (8 x 20 ms Waveform)
15.7
V
VC
IPP = 5 A (8 x 20 ms Waveform)
19.1
V
Maximum Peak Pulse Current (Note 10)
IPP
8 x 20 ms Waveform
6.2
A
Capacitance
CJ
VR = 0 V, f = 1 MHz
(Anode-to-GND)
60
pF
0.6
8. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC
or continuous peak operating voltage level.
9. VBR is measured at pulse test current IT.
10. Pulse waveform per Figure 11.
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3
NTHD2110T
TYPICAL MOSFET PERFORMANCE CURVES
12.5
14
-ID, DRAIN CURRENT (A)
12
VDS w -10 V
TJ = 25°C
-ID, DRAIN CURRENT (A)
-7 V
-4.5 V
-1.8 V
10
-2.5 V
-2 V
8
-1.6 V
6
-1.4 V
4
-1.2 V
2
10
7.5
5
25°C
2.5
TJ = -55°C
VGS = -1 V
0
0
0.5
1
1.5
2
2.5
-VDS, DRAIN-TO_SOURCE VOLTAGE (V)
0
3
0.5
1
1.5
2
-VGS, GATE-TO_SOURCE VOLTAGE (V)
0.38
ID = -6.4 A
TJ = 25°C
0.34
0.3
0.26
0.22
0.18
0.14
0.1
0.6
0.2
1
2
3
4
5
-VGS, GATE-TO_SOURCE VOLTAGE (V)
6
0.05
TJ = 25°C
0.045
VGS = -2.5 V
0.04
0.035
VGS = -4.5 V
0.03
2
Figure 3. On-Resistance vs. Gate Voltage
3
4
5
-ID, DRAIN CURRENT (A)
6
7
Figure 4. On-Resistance vs. Drain Current and
Gate Voltage
1.5
1.4
2.5
Figure 2. Transfer Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
Figure 1. On-Region Characteristics
100000
ID = -6.4 A
VGS = -4.5 V
VGS = 0 V
1.3
-IDSS, LEAKAGE (nA)
RDS(on), DRAIN-TO-SOURCE RESISTANCE
(NORMALIZED)
125°C
0
1.2
1.1
1
0.9
TJ = +150°C
10000
TJ = +125°C
1000
0.8
0.7
-50
-25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
150
100
2
Figure 5. On-Resistance Variation with
Temperature
3
4
5
6
7
8
9
10 11
-VDS, DRAIN-TO_SOURCE VOLTAGE (V)
Figure 6. Drain-to-Source Leakage Current
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4
12
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
4.5
-VGS, GATE-TO-SOURCE VOLTAGE
(V)
C, CAPACITANCE (pF)
NTHD2110T
TTJ J==25°C
25°C
VGS = 0 V
CISS
COSS
CRSS
0
2
4
6
8
10
QT
4
3.5
3
2.5
2 Q1
Q2
1.5
1
ID = -6.4 A
TJ = 25°C
0.5
0
12
0
2
-VDS, DRAIN-TO_SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
12
Figure 8. Gate-to-Source and
Drain-to-Source Voltage vs. Total Charge
1000
-IS, SOURCE CURRENT (A)
6
VDS = -6 V
ID = -1 A
VGS = -4.5 V
t, TIME (ns)
4
6
8
10
Qg, TOTAL GATE CHARGE (nC)
td(off)
tf
100
tr
10
td(on)
VGS = 0 V
TJ = 25°C
5
4
3
2
1
0
1
1
10
RG, GATE RESISTANCE (W)
0
100
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
-VSD, SOURCE-TO-DRAIN VOLTAGE (V)
1
Figure 10. Diode Forward Voltage vs. Current
TYPICAL TVS PERFORMANCE CURVES
7
WAVEFORM
PARAMETERS
tr = 8 ms
td = 20 ms
100
90
80
IPP, PEAK PULSE CURRENT (A)
% OF PEAK PULSE CURRENT
110
c-t
70
60
td = IPP/2
50
40
30
20
10
0
0
5
10
15
t, TIME (ms)
20
25
30
6
PULSE WAVEFORM
8 x 20 ms per Figure 11
5
4
3
2
1
0
14
Figure 11. Pulse Waveform, 8 × 20 ms
15
16
17
18
VC, CLAMPING VOLTAGE (V)
19
Figure 12. Clamping Voltage vs Peak Pulse
Current
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5
20
NTHD2110T
18
17
16
16.5
14
16
VZ, (V)
10
8
IZ = 5 mA
15.5
6
15
IZ = 1 mA
4
14.5
2
0
-60
-20
20
60
100
140
14
-60
180
-10
40
90
140
190
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Typical Leakage vs. Temperature
Figure 14. Typical VZ @ 1 mA vs. Temperature
60
25°C
50
C, CAPACITANCE (pF)
IR, (nA)
12
40
30
20
10
0
0
2
4
6
8
10
12
14
VBIAS, (V)
Figure 15. Capacitance vs. VBIAS
Gate Controller
Input
Voltage
Load
Figure 16. Typical Application Circuit
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6
NTHD2110T
PACKAGE DIMENSIONS
ChipFETt
CASE 1206A-03
ISSUE J
D
8
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.
q
6
L
5
HE
5
6
7
8
4
3
2
1
E
1
2
3
e1
4
b
DIM
A
b
c
D
E
e
e1
L
HE
q
c
e
A
0.05 (0.002)
SOLDERING FOOTPRINT*
1
2.032
0.08
2.362
0.093
MILLIMETERS
NOM
MAX
1.05
1.10
0.30
0.35
0.15
0.20
3.05
3.10
1.65
1.70
0.65 BSC
0.55 BSC
0.28
0.35
0.42
1.80
1.90
2.00
5° NOM
MIN
1.00
0.25
0.10
2.95
1.55
INCHES
NOM
0.041
0.012
0.006
0.120
0.065
0.025 BSC
0.022 BSC
0.011
0.014
0.071
0.075
5° NOM
MIN
0.039
0.010
0.004
0.116
0.061
MAX
0.043
0.014
0.008
0.122
0.067
0.017
0.079
STYLE 6:
PIN 1. ANODE
2. DRAIN
3. DRAIN
4. GATE
5. SOURCE
6. DRAIN
7. DRAIN
8. CATHODE / DRAIN
0.635
0.025
PITCH
8X
8X
0.66
0.026
0.457
0.018
mm Ǔ
ǒinches
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ChipFET is a trademark of Vishay Siliconix
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NTHD2110T/D