PROCESS CP630 Power Transistors PNP - Silicon Darlington Transistor Chip PROCESS DETAILS Process EPITAXIAL BASE Die Size 80 X 80 MILS Die Thickness 8 MILS Base Bonding Pad Area 18 X 27 MILS Emitter Bonding Pad Area 34 X 34 MILS Top Side Metalization Al - 30,000Å Back Side Metalization Ti/Pd/Ag (20,000Å) GEOMETRY GROSS DIE PER 4 INCH WAFER 1,445 PRINCIPAL DEVICE TYPES CZT127 CJD127 BACKSIDE COLLECTOR 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R0 (9 -May 2005)