FUJITSU MB3889

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-27229-2E
ASSP
For Power Supply Applications (General Purpose DC/DC Converter)
2-Channel DC/DC Converter IC
with Overcurrent Protection Symmetrical-Phase Type
MB3889
■ DESCRIPTION
The MB3889 is a symmetrical-phase type of two-channel, DC/DC converter IC using pulse width modulation
(PWM) , incorporating an overcurrent protection circuit (requiring no current sense resistor) and an overvoltage
protection circuit. Providing high output driving capabilities, the MB3889 is suitable for down-conversion.
The MB3889 adopts both synchronous rectification to provide high efficiency and symmetrical phasing (two antiphase triangular waves) which contributes to making the input capacitor small.
The MB3889 contains a 5-volt regulator resulting in a reduced number of components used. It also contains a
variety of protection features which output the protection status upon detection of an overvoltage or overcurrent
while reducing the number of external protective devices required.
The result is an ideal built-in power supply for driving products with high speed CPU’s such as home TV game
devices and notebook PC’s.
This product is covered by US Patent Number 6,147,477.
■ FEATURES
•
•
•
•
•
•
•
•
Built-in timer-latch overcurrent protection circuit (requiring no current sense resistor)
Built-in timer-latch overvoltage protection circuit
Synchronous rectification system providing high efficiency
Power supply voltage range: 5.5 V to 18 V
PWRGOOD terminals (open-drain) to output the protection status
Symmetrical-phase system reducing the input capacitor loss
Built-in channel control function
Reference voltage: 3.5 V ± 1 %
(Continued)
■ PACKAGE
30-pin plastic TSSOP
(FPT-30P-M04)
MB3889
(Continued)
• Error amplifier threshold voltage: 1.23 V ± 1 % (0 °C to + 85 °C)
• Support for frequency setting using an external resistor (Frequency setting capacitor integrated)
• Oscillation frequency range: 100 kHz to 500 kHz
• Built-in circuit for load-independent soft-start and discharge control
• Built-in totem-pole output for Nch MOS FET
2
MB3889
■ PIN ASSIGNMENT
(TOP VIEW)
−INE1 : 1
30 : CB1
FB1 : 2
29 : OUT1-1
CS1 : 3
28 : VS1
N.C. : 4
27 : OUT2-1
RT : 5
26 : PGND1
CTL : 6
25 : ILIM1
SGND : 7
24 : VCC
VREF : 8
23 : ILIM2
CTL1 : 9
22 : VB
CTL2 : 10
21 : N.C.
CSCP : 11
20 : PGND2
PWRGOOD : 12
19 : OUT2-2
CS2 : 13
18 : VS2
FB2 : 14
17 : OUT1-2
−INE2 : 15
16 : CB2
(FPT-30P-M04)
3
MB3889
■ PIN DESCRIPTION
4
Pin No.
Symbol
I/O
Descriptions
1
−INE1
I
CH1 error amp inverted input terminal
2
FB1
O
CH1 error amp output terminal
3
CS1

CH1 soft-start capacitor connection terminal
4
N.C.

No connection
5
RT

Triangular waveform oscillation frequency setting resistor connection terminal
6
CTL
I
7
SGND

Ground terminal
8
VREF
O
Reference voltage output terminal
9
CTL1
I
CH1 control terminal
“H” level : CH1 ON state
“L” level : CH1 OFF state and protection status reset
10
CTL2
I
CH2 control terminal
“H” level : CH2 ON state
“L” level : CH2 OFF state and protection status reset
11
CSCP

Timer-latch short-circuit protection capacitor connection terminal
12
PWRGOOD
O
CH1, CH2 protection status output terminal
13
CS2

CH2 soft-start capacitor connection terminal
14
FB2
O
CH2 error amp output terminal
15
−INE2
I
CH2 error amp inverted input terminal
16
CB2

CH2 boot capacitor connection terminal
Connect a capacitor between the CB2 and VS2 terminals.
17
OUT1-2
O
CH2 totem-pole output terminal (External main-side FET gate drive)
18
VS2

CH2 external main-side FET source connection terminal
19
OUT2-2
O
CH2 totem-pole output terminal (External synchronous-rectification-side FET
gate drive)
20
PGND2

Ground terminal
21
N.C.

No connection
22
VB
O
Output circuit bias output terminal
23
ILIM2
I
CH2 overcurrent detection resistor connection terminal
24
VCC

25
ILIM1
I
26
PGND1

Ground terminal
27
OUT2-1
O
CH1 totem-pole output terminal (External synchronous-rectification-side FET
gate drive)
28
VS1

CH1 external main-side FET source connection terminal
29
OUT1-1
O
CH1 totem-pole output terminal (External main-side FET gate drive)
30
CB1

CH1 boot capacitor connection terminal
Connect a capacitor between the CB1 and VS1 terminals.
Power supply control terminal.
“H” level : IC operating mode
“L” level : IC Standby mode
Reference voltage, control circuit power supply terminal
CH1 overcurrent detection resistor connection terminal
MB3889
■ BLOCK DIAGRAM
VCC
24
5.1 V
VB Reg.
CH1
L priority
PWM
+ Comp.1
+
−
L priority
Error
Amp1
−INE1 1
−
+
+
1.23 V
OVP
+ Comp.1
CS1 3
VREF 3 µA
Max Duty 81%
Dtr ± 6%
30 CB1
Dead Time
Modulation 1
FB1 2
Drv
1-1
28 VS1
1.38 V
Current
Protection
Logic
CTL1 9
Open : CH1 ON
CTL1 = H
L : CH1 OFF
6 kΩ
VTH = 1.4 V
−INE2 15
CS2 13
VREF 3 µA
Error
Amp2
−
+
+
1.23 V
OVP
+ Comp.2
PWM
Comp.2
+
+
−
Max Duty 81%
Dtr ± 6%
18 VS2
Current
Protection
Logic
H: priority
19 OUT2-2
20 PGND2
OCP
Comp.2
−
+
23 ILIM2
118 µA
H: at
UVLO release
H: at OVP
3.1 V
H: at OVP
H: at OVP
H: at OCP
H: at SCP
Latch1
SQ
CTL
CTL1
CTL2
L: at protection
operation
R
CTL
CTL1
CTL2
S R
Latch
Latch2
3.0 V
CT1
1.8 V
3.0 V
CT2
1.8 V
VREF
UVLO
PWRGOOD
12
10 µA
CSCP 11
17 OUT1-2
Drv
2-2
H: at OCP
SCP Comp. +
+
−
25 ILIM1
Drv
1-2
1.38 V
CTL2 10
Open : CH2 ON
CTL2 = H
L : CH2 OFF
6 kΩ
VTH = 1.4 V
+
16 CB2
−
100
kΩ
Buff
26 PGND1
OCP
Comp.1
−
CH2
Dead Time
Modulation 2
L priority
L priority
27 OUT2-1
118 µA
H: at OCP
FB2 14
29 OUT1-1
Drv
2-1
−
100
kΩ
Buff
22 VB
4 N.C.
to Error amp reference
1.23 V
bias
OSC
VREF
3.5 V
8
VREF
VCC
Power
VR1 ON/OFF
CTL
45 pF
5
RT
Protection
control
signal
7
SGND
21 N.C.
6 CTL
H : ON (Power On)
L : OFF (Standby mode)
VTH = 1.4 V
5
MB3889
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Power-supply voltage
VCC

Boot voltage
VCB
CB terminal

Rating
Unit
Min
Max

20
V

25
V

120
mA
Output current
IO
Peak output current
IOP
Duty ≤ 5%
(t = 1 / fOSC × Duty)

800
mA
Power dissipation
PD
Ta ≤ +25 °C

1390*
mW
−55
+125
°C
Storage temperature
TSTG

* : The packages are mounted on the dual-sided epoxy board (10 cm × 10 cm) .
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
6
MB3889
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Power-supply voltage
VCC

Boot voltage
VCB
Reference voltage output current
Bias output current
Input voltage
Value
Unit
Min
Typ
Max
5.5
12
18
V
CB terminal


23
V
IOR
VREF terminal
−1

0
mA
IOB
VB terminal
−1

0
mA
VIN
−INE terminal
0

VCC − 1.8
V
CTL1, CTL2 terminal
0

VREF
V
CTL terminal
0

VCC
V
PWRGOOD terminal
0

15
V
− 100

100
mA
− 700

700
mA
VCTL
Output voltage
VPG
Output current
IO
Peak output current
IOP
Oscillation frequency
fOSC

100
300
500
kHz
Timing resistor
RT

30
47
130
kΩ
Boot capacitor
CB


0.1
1.0
µF

Duty ≤ 5%
(t = 1 / fOSC × Duty)
Reference voltage output
capacitor
CREF
VREF terminal

0.1
1.0
µF
Bias output capacitor
CVB
VB terminal
1.0
4.7
10
µF
Soft-start capacitor
CS


0.1
1
µF
Short-circuit detection capacitor
CSCP


0.01
1
µF
Overcurrent detection setting
resistor
RLIM

0.1
1
10
kΩ
Operating ambient temperature
Ta

− 30
+ 25
+ 85
°C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
7
MB3889
■ ELECTRICAL CHARACTERISTICS
(VCC = 12 V, VB = 0 mA, VREF = 0 mA, Ta = +25 °C)
Symbol
Pin
No.
VREF
8
Ta = + 25 °C
Output voltage ∆VREF/
VREF
8
Input stability
Line
Load stability
Short-circuit
output current
Parameter
1. Reference
Voltage
Block [REF]
2. Bias Voltage
Output voltage
Block [VB]
3. Triangular
Waveform
Oscillator
Block [OSC]
4. Undervoltage (VCC)
Lockout Circuit
Block [UVLO]
Oscillation
frequency
Frequency/
temperature
variation
[OCP]
Value
Unit
Min
Typ
Max
3.465
3.500
3.535
V
Ta = 0 °C to + 85 °C

0.5*

%
8
VCC = 5.5 V to 18 V

1
10
mV
Load
8
VREF = 0 mA to − 1 mA

3
10
mV
IOS
8
VREF = 0 V
− 40
− 20
− 10
mA
VB
22
5.0
5.1
5.2
V
17, 29 RT = 47 kΩ
270
300
330
kHz
∆fOSC/
17, 29 Ta = 0 °C to + 85 °C
fOSC

1*

%
2.6
2.8
3.0
V
fOSC

Threshold
voltage
VTH
8
Hysteresis
width
VH
8


0.2*

V
VTH
11

0.65
0.70
0.75
V
ICSCP
11

− 14
− 10
−6
µA
VRST
8
1.7
2.1
2.5
V
106
118
130
µA

1*

mV
Threshold
5. Short-circuit voltage
Protection
Input source
Circuit Block
current
[SCP]
Reset voltage
6. Overcurrent
Protection
Circuit Block
Conditions
VREF =
VREF =
ILIM terminal
input current
ILIM
23, 25 RT = 47 kΩ
Offset voltage
VIO
23, 25
VTH
1, 15 −INE =
1.35
1.38
1.41
V
1, 15 −INE = 0 V
−730
−110

nA
7. Overvoltage Threshold
voltage
Protection
Circuit Block
Input bias
[OVP]
current
IB

8.Protection
Status
Output leakage
current
ILEAK
12
PWRGOOD = 5 V


40
µA
Output Cirsuit
Block
[PWRGOOD]
Output “L” level
voltage
VOL
12
PWRGOOD = 1 mA

0.1
0.4
V
Charge current
ICS
3, 13
− 4.2
− 3.0
− 1.8
µA
9. Soft-start
Circuit Block
[CS]

*: Standard design value
(Continued)
8
MB3889
(VCC = 12 V, VB = 0 mA, VREF = 0 mA, Ta = +25 °C)
Parameter
Threshold
voltage
10. Error Amp
Block
[Error Amp]
Pin
No.
VTH1
1, 15
VTH2
1, 15
Value
Unit
Min
Typ
Max
FB = 2.4 V,
Ta = + 25 °C
1.221
1.230
1.239
V
FB = 2.4 V,
Ta = 0 °C to + 85 °C
1.218
1.230
1.242
V
− 730
− 110

nA
IB
1, 15 −INE = 0 V
Voltage gain
AV
2, 14 DC
60
100

dB
Frequency
bandwidth
BW
2, 14 AV = 0 dB

1.5*

MHz
VFBH
2, 14

3.2
3.4

V
VFBL
2, 14


40
200
mV

−2
−1
mA
Output source
current
Output sink
current
ISOURCE 2, 14 FB = 2.4 V
ISINK
2, 14 FB = 2.4 V
150
250

µA
VTL
2, 14 Duty cycle = 0 %
1.7
1.8

V
VTH
2, 14 Duty cycle = Dtr

2.86
3.00
V
Dtr
17, 29 RT = 47 kΩ
75
81
87
%
ISOURCE1
OUT1 = 12 V, CB = 17 V,
VS = 12 V,
17, 29
Duty ≤ 5 %
(t = 1/ fOSC × Duty)

− 700*

mA
ISINK1
OUT1 = 17 V, CB = 17 V,
VS = 12 V,
17, 29
Duty ≤ 5 %
(t = 1/ fOSC × Duty)

900*

mA
VOH1
17, 29
OUT1 = − 100 mA,
CB = 17 V, VS = 12 V
VCB
− 2.5
VCB
− 0.9

V
VOL1
17, 29
OUT1 = 100 mA,
CB = 17 V, VS = 12 V

VS
+ 0.9
VS
+ 1.4
V

− 750*

mA

900

mA
Threshold
voltage
12. Dead Time
Maximum duty
Control Block
cycle
[DTC]
Output
current
(main side)
13. Output
Block
[Drive]
Conditions
Input bias
current
Output voltage
11. PWM
Comparator
Block
[PWM Comp.]
Symbol
Output voltage
(main side)
OUT2 = 0 V,
Output current
(synchronous
rectification
side)
ISOURCE2 19, 27 Duty ≤ 5 %
(t = 1/ fOSC × Duty)
ISINK2
OUT2 = 5.1 V,
19, 27 Duty ≤ 5 %
(t = 1/ fOSC × Duty)
*: Standard design value
(Continued)
9
MB3889
(Continued)
Parameter
13. Output
Block
[Drive]
Symbol
Pin
No.
(VCC = 12 V, VB = 0 mA, VREF = 0 mA, Ta = + 25 °C)
Value
Unit
Conditions
Min
Typ
Max
Output voltage
(synchronous
rectification
side)
VOH2
19, 27 OUT2 = − 100 mA
2.5
4.1

V
VOL2
19, 27 OUT2 = 100 mA

1.0
1.4
V
Diode voltage
VD
16, 30 VB = 10 mA

0.9
1.1
V
tD1
29, 27,
VS = 0 V
17, 19
40
80
120
ns
60
120
180
ns
OUT1 = OUT2 = OPEN,
OUT2 :
Dead time
OUT1 = OUT2 = OPEN,
tD2
29, 27,
VS = 0 V
17, 19
OUT1 :
14. Control
Block
(CTL, CTL1,
CTL2)
[CTL]
15. General
− OUT2 :
Output ON
condition
VON
9, 10

2

VREF
V
Output OFF
condition
VOFF
9, 10

0

0.8
V
Output ON
condition
VON
6

2

VCC
V
Output OFF
condition
VOFF
6

0

0.8
V
Input current
ICTL
− 44
− 35
− 29
µA
Standby
current
Power-supply
current
*: Standard design value
10
− OUT1 :
9, 10 CTL1 = CTL2 = 0 V
6
CTL = 5 V

50
75
µA
ICCS
24
CTL = 0 V

0
10
µA
ICC
24
CTL = 5 V

15
23
mA
MB3889
Power Supply Current vs. Power Supply Voltage
Reference Voltage vs. Power Supply Voltage
20
6
Ta = +25 °C
CTL = 5 V
18
Reference voltage VREF (V)
Power Supply current ICC (mA)
■ TYPICAL CHARACTERISTICS
16
14
12
10
8
6
4
2
0
0
5
10
15
Ta = +25 °C
CTL = 5 V
VREF = 0 mA
5
4
3
2
1
0
20
0
5
Power supply voltage VCC (V)
Reference voltage ∆VREF (%)
Ta = +25 °C
VCC = 12 V
CTL = 5 V
4
3
2
1
0
0
5
10
15
20
25
VCC = 12 V
CTL = 5 V
VREF = 0 mA
1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
−40
−20
3
2
ICTL
1
100
0
0
5
10
15
CTL terminal voltage VCTL (V)
0
20
Triangular wave oscillation
frequency fOSC (kHz)
VREF
200
40
60
1000
Reference voltage VREF (V)
5
Ta = +25 °C
VCC = 12 V
VREF = 0 mA 4
300
20
80
100
Triangular Wave Oscillation Frequency
vs. Timing Resistor
CTL Terminal Current, Reference Voltage
vs. CTL Terminal Voltage
400
0
Ambient temperature Ta (°C)
Load current IREF (mA)
500
20
Reference Voltage vs. Ambient Temperature
2.0
5
Reference voltage VREF (V)
15
Power supply voltage VCC (V)
Reference Voltage vs. Load Current
CTL terminal current ICTL (µA)
10
Ta = +25 °C
VCC = 12 V
CTL = 5 V
100
10
10
100
1000
Timing resistor RT (Ω)
(Continued)
11
MB3889
330
325
320
315
310
305
300
295
290
285
280
275
270
Triangular Wave Oscillation Frequency
vs. Ambient Temperature
2
Ta = +25 °C
RT = 47 kΩ
CTL = 5 V
0
5
10
15
Triangular wave oscillation
frequency ∆fOSC/fOSC (%)
Triangular wave oscillation
frequency fosc (kHz)
Triangular Wave Oscillation Frequency
vs. Power Supply Voltage
VCC = 12 V
RT = 47 kΩ
CTL = 5 V
1.5
1
0.5
0
−0.5
−1
−1.5
−2
−40
20
−20
0
20
40
60
80
100
Ambient temperature Ta ( °C)
Power supply voltage VCC (V)
Error amplifier threshold
voltage VTH (V)
Error Amplifier Threshold Voltage
vs. Ambient Temperature
1.244
1.242
1.240
1.238
1.236
1.234
1.232
1.230
1.228
1.226
1.224
1.222
1.220
1.218
−40
VCC = 12 V
CTL = 5 V
−20
0
20
40
60
80
100
Ambient temperature Ta ( °C)
Error Amplifier, Gain, Phase
vs. Frequency
Ta = +25 °C
40
ϕ
20
90
10
0
0
−10
−20
−90
−30
10 kΩ
1 µF
+
IN
10 kΩ
240 kΩ
10 kΩ
2.4 kΩ
10 kΩ
(15)
1 −
3 +
(13) +
1.23 V
2
(14)
OUT
Error Amp1
(Error Amp2)
−180
−40
100
4.2 V VCC = 12 V
Phase φ (deg)
30
Gain AV (dB)
180
AV
1k
10 k
100 k
1M
10 M
Frequency f (Hz)
(Continued)
12
MB3889
(Continued)
Power Dissipation vs. Ambient Temperature
Power dissipation PD (mW)
1600
1400
1390
1200
1000
800
600
400
200
0
−40
−20
0
20
40
60
80
100
Ambient temperature Ta ( °C)
13
MB3889
■ FUNCTIONS
1. DC/DC Converter Functions
(1) Reference voltage block (Ref)
The reference voltage circuit generates a temperature-compensated reference voltage (typically 3.5 V) using
the voltage supplied from the power supply terminal (pin 24) . The voltage is used as the reference voltage for
the IC’s internal circuitry.
The reference voltage can be used to supply a load current of up to 1 mA to an external device through the
VREF terminal (pin 8) .
(2) Triangular-wave oscillator block (OSC)
The triangular waveform oscillator incorporates a timing capacitor connected respectively to the RT terminal
(pin 5) to generate triangular oscillation waveforms CT1 (amplitude of 1.8 V to 3.0 V) and CT2 (amplitude of 1.8
V to 3.0 V in antiphase with CT1). The symmetrical-phase system using the two opposite-phase triangular waves
reduces the input ripple current, resulting in a smaller input capacitor.
The triangular oscillation waveforms are input to the IC’s internal PWM comparator.
(3) Error amplifier block (Error Amp1, Error Amp2)
The error amplifier detects the DC/DC converter output voltage and outputs PWM control signals. By connecting
a feedback resistor and capacitor between the output terminal and inverted input terminal, it is possible to create
any desired level of loop gain, thereby providing stable phase compensation to the system.
Also, it is possible to prevent rush current at power supply start-up by connecting a soft-start capacitor to the
CS1 terminal (pin 3) or CS2 terminal (pin 13), the non-inverted input terminal for Error Amp. The use of Error
Amp for soft-start detection makes it possible for a system to operate on a fixed soft-start time that is independent
of the output load on the DC/ DC converter.
(4) PWM comparator (PWM Comp.) block
The PWM comparator is a voltage-pulse width modulator that controls the output duty depending on the
input/output voltage.
Main side : Turns the output transistor on in the intervals in which the error amplifier output voltage is higher
than the triangular wave voltage.
Synchronous rectification side : Turns the output transistor on in the intervals in which the error amplifier output
voltage is lower than the triangular wave valtage.
(5) Output block
The output circuits on the main side and on the synchronous rectification side are both in the totem pole
configuration, capable of driving an external N-ch MOS FET.
In addition, because the output drive ability (700 mA Max : Duty ≤ 5%) is high, the gate − source capacity is
large and the FET of low ON resistor can be used.
14
MB3889
2. Channel Control Function
Channels, main, VB and PWRGOOD are turned on and off depending on the voltage levels at the CTL terminal
(pin 6), CTL1 terminal (pin 9) and CTL2 terminal (pin 10).
Channel On/Off Setting Conditions
CTL
CTL1
CTL2
Power
CH1
CH2
VB
PWRGOOD
L
*
*
OFF
OFF
OFF
OFF
OFF
H
H
H
H
L
H
L
H
L
L
H
H
ON
ON
ON
ON
OFF
ON
OFF
ON
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
*: Undefined
3. Protective Functions
(1) Undervoltage lockout protection circuit (UVLO)
The transient state or a momentary drops in supply voltage, which occurs when the power supply is turned on,
may cause the control IC to malfunction, resulting in breakdown or degradation of the system. To prevent such
malfunctions, the undervoltage lockout protection circuit detects the internal reference voltage level with respect
to the power supply voltage, turns off the output transistor, and sets the dead time to 100% while holding the
CSCP terminal (pin 11) at the “L” level and setting the PWRGOOD terminal (pin 12) to the “L” level.
The system is restored when the supply voltage reaches the threshold voltage of the undervoltage lockout
protection circuit.
(2) Timer-latch overcurrent protection circuit block (OCP)
The timer-latch overcurrent protection circuit is actuated upon completion of the soft-start period. When an
overcurrent flows, the circuit detects the increase in the voltage between the main-side FET’s drain and source
using the main-side FET ON resistor, actuates the timer circuit, and starts charging the capacitor CSCP connected to the CSCP terminal (pin 11). If the overcurrent remains flowing beyond the predetermined period of
time, the circuit sets the latch to turn off the FETs on the main side and synchronous rectification side of each
channel while setting the PWRGOOD terminal (pin 12) to the “L” level. The detection current value can be set
by resistor RLIM1 connected between the main-side FET’s drain and the ILIM1 terminal (pin 25) and resistor
RLIM2 connected between the drain and the ILIM2 terminal (pin 23).
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 6) to the “L” level to lower the VREF terminal (pin 8) voltage to 1.7 V (Min) or less. It can also be reset by
setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to the “L” level. (See “1. Setting Timer-Latch
Overcurrent Protection Detection Current” in ■ ABOUT TIMER-LATCH PROTECTION CIRCUIT.)
(3) Timer-latch short-circuit protection circuit (SCP)
The short-circuit detection comparator (SCP Comp.) provided for the two channels detects the output voltage
level and, if the error amplifier output voltage of either channel reaches the short-circuit detection voltage (typically
3.1 V), the timer circuit is actuated to start charging the external capacitor Cscp connected to the CSCP terminal
(pin 11).
When the capacitor voltage reaches about 0.7 V, the circuit turns off the output transistor and sets the dead time
to 100%.
The PWRGOOD terminal (pin 12) is fixed at the “L” level.
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 6) to the “L” level to lower the VREF terminal (pin 8) voltage to 1.7 V (Min) or less. It can also be reset by
setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to the “L” level. (See “2. Setting Time
Constant for Timer-Latch Short-Circuit Protection Circuit” in ■ ABOUT TIMER-LATCH PROTECTION CIRCUIT.)
15
MB3889
(4) Timer-latch overvoltage protection circuit block (OVP)
When the overvoltage detection comparator (OVP Comp.) provided for each channel detects the DC-DC converter’s output voltage level exceeding its threshold voltage, the timer-latch overvoltage protection circuit actuates
the timer circuit and starts charging the capacitor CSCP connected to the CSCP terminal (pin 11). If the overvoltage remains applied beyond the predetermined period of time, the circuit sets the latch to turn off the FET
on the main side of each channel while setting the PWRGOOD terminal (pin 12) to the “L” level.
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 6) to the “L” level to lower the VREF terminal (pin 8) voltage to 1.7 V (Min) or less. It can also be reset by
setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to the “L” level. (See “3. Setting Detection
of Timer-Latch Overvoltage Protection Circuit” in ■ ABOUT TIMER-LATCH PROTECTION CIRCUIT.)
(5) Protection status output circuit block (PWRGOOD)
The protection status output circuit outputs the “L” level signal to the PWRGOOD terminal (pin 12) when each
protection circuit is actuated.
16
MB3889
■ SETTING THE OUTPUT VOLTAGE
VO
R1
(−INE2) 15
−INE1
1
R2
(CS2) 13
CS1
3
Error Amp
VO (V) =
−
+
+
1.23
R2
(R1 + R2)
1.23 V
< CH1, CH2 >
■ SETTING THE TRIANGULAR OSCILLATION FREQUENCY
The triangular oscillation frequency is determined by the timing capacitor connected to the timing resistor (RT)
connected to the RT terminal (pin 5).
Triangular oscillation frequency: fOSC
fOSC (kHz) =:
14100
RT (kΩ)
17
MB3889
■ SETTING THE SOFT-START AND DISCHARGE TIMES
To prevent rush currents when the IC is turned on, you can set a soft-start by connecting soft-start capacitors
(CS1 and CS2) to the CS1 terminal (pin 3) for channel 1 and the CS2 terminal (pin 13) for channel 2, respectively.
Setting the each control terminals (CTL1 and CTL2) from “L” to “OPEN” switches SW1 and SW2 from B to A to
charge the external soft-start capacitors (CS1 and CS2) connected to the CS1 and CS2 terminals at 3 µA.
The error amplifier output (FB1 or FB2) is determined by comparison between the lower one of the potentials
at two noninverted input terminals (1.23 V, CS terminal voltages) and the inverted input terminal voltage (-INE).
The FB terminal voltage during the soft-start period is therefore determined by comparison between the -INE
terminal and CS terminal voltages. The DC/DC converter output voltage rises in proportion to the CS terminal
voltage as the soft-start capacitor connected to the CS terminal is charged.
The soft-start time is obtained from the following equation:
Soft-start time: ts (time to output 100%)
ts (s) =: 0.41 × CS (µF)
Setting the each control terminals (CTL1 and CTL2) from “OPEN” to “L” switches SW1 and SW2 from A to B.
Then the IC discharges the soft-start capacitors (CS1 and CS2) charged at about 3.4 V using the internally set
discharge resistor (Rs: = 6 kΩ) and lowers the output voltage regardless of the DC/DC converter load current.
The discharge time is obtained from the following equation:
Discharge time: toff (time to output 10%)
toff (s) =: 0.020 × CS (µF)
CS terminal voltage
=: 3.4 V
=: 1.23 V
Error amp block comparison
voltage to −INE voltage
=: 0.123 V
=: 0 V
Soft-start time (ts)
OPEN
CTL signal
L
18
Discharge time (toff)
MB3889
R1
L priority
−INE1
1
(CS2)
13
−
3
+
+
CS1
Error Amp
R2
1.23 V
VREF
3 µA
100 KΩ
CTL2
10
CTL1
9
Buff
A SW1 (SW2)
B
Open : CH ON
L : CH OFF
VTH = 1.4 V
CTL1 = H
Soft-start
Discharge
6 kΩ
<Soft-start circuit>
■ TREATMENT OF UNUSED CS TERMINALS
When the soft-start function is not used, the CS1 terminal (pin 3) and CS2 terminal (pin 13) should be left open.
3
CS1
13 CS2
< Operation Without Soft-start Setting >
19
MB3889
■ ABOUT TIMER-LATCH PROTECTION CIRCUIT
1. Setting Timer-Latch Overcurrent Protection Detection Current
The overcurrent protection circuit is actuated upon completion of the soft-start period. When an overcurrent
flows, the circuit detects the increase in the voltage between the main-side FET’s drain and source using the
main-side FET ON resistor (RON), actuates the timer circuit, and starts charging the capacitor CSCP connected
to the CSCP terminal (pin 11). If the overcurrent remains flowing beyond the predetermined period of time, the
circuit sets the latch to turn off the FETs on the main side and synchronous rectification side of each channel
while setting the PWRGOOD terminal (pin 12) to the "L" level. The detection current value can be set by the
resistors (RLIM1 and RLIM2) connected between the main-side FET’s drain and the ILIM1 terminal (pin 25) and
between the drain and the ILIM2 terminal (pin 23), respectively.
The internal current (ILIM) can be set by the timing resistor (RT) connected to the RT terminal (pin 5).
Time until activating timer circuit and setting latch is equal to short-circuit detection time in "2. Setting Time
Constant for Timer-Latch Short-Circuit Protection Circuit".
Internal current value: ILIM
ILIM (µA) =:
5546
RT (kΩ)
Detection current value: IOCP
IOCP (A) =:
ILIM(A) × RLIM(Ω)
RON (Ω)
(Vin(V) − VO(V)) × VO(V)
2 × Vin(V) × fOSC(Hz) × L(H)
−
RLIM: Overcurrent detection resistor
RON: Main-side FET ON resistor
Vin: Input voltage
VO: DC-DC converter output voltage
fOSC: Oscillation frequency
L: Coil inductance
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 6) to the "L" level to lower the VREF terminal (pin 8) voltage to 1.7 V (Min) or less. It can also be reset by
setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to the "L" level.
VIN
M1
(VS2)
18 VS1
28
−
Current
Protection
Logic
+
(ILIM2)
23 ILIM1
25
118 µA
PWRGOOD
12
10 µA
CTL
CTL1
CTL2
CSCP
11
VREF
S
R
Latch
UVLO
Latch2
<Overcurrent detection circuit>
20
MB3889
2. Setting Time Constant for Timer-Latch Short-Circuit Protection Circuit
Each channel uses the short-circuit detection comparator (SCP Comp.) to always compare the error amplifier’s
output level to the reference voltage.
While the DC-DC converter load conditions are stable on both channels, the short-circuit detection comparator
keeps its output at the “H” level and the CSCP terminal (pin 11) remains at the “L” level.
If a load condition changes rapidly due to a short-circuit of the load, causing the output voltage to drop, the shortcircuit detection comparator changes its output to the “L” level. This causes the external short-circuit protection
capacitor Cscp connected to the CSCP terminal to be charged at 10 µA.
Short-circuit detection time (tSCP)
tSCP (s) =: 0.070 × CSCP (µF)
When capacitor Cscp is charged to the threshold voltage (VTH =: 0.70 V), the protection circuit sets the latch
and turns off the external FET (setting the dead time to 100%). At this time, the latch input is closed and the
CSCP terminal is held at the “L” level. The protection circuit closes both channels even when a short-circuit is
detected on only either.
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 6) to the “L” level to lower the VREF terminal (pin 8) voltage to 1.7 V (Min) or less. It can also be reset by
setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to the “L” level.
(FB2)
VO
R1
FB1
14
2
(−INE2) 15
−INE1
−
1
Error
Amp
+
R2
1.23 V
SCP
Comp.
+
+
−
PWRGOOD
3.1 V
10 µA
12
CTL
CTL1
CTL2
CSCP
11
VREF
S
R
Latch
UVLO
Latch2
<Timer-latch short-circuit protection circuit>
21
MB3889
3. Setting Overvoltage Detection by the Timer-Latch Overvoltage Protection Circuit
An overvoltage output from the DC-DC converter can be detected by connecting external resistors from the DCDC converter output to the noninverted input terminal (-INE1 terminal (pin 1) and -INE2 terminal (pin 15)) of the
overvoltage comparators (OVP Comp. 1 and 2).
When the DC-DC converter output voltage exceeds the overvoltage detection level, the output of the overvoltage
comparator (OVP Comp. 1, 2) becomes the “H” level and the overvoltage protection circuit actuates the timer
circuit to start charging the external capacitor Cscp connected to the CSCP terminal (pin 11). If the overvoltage
remains applied beyond setting time, the circuit sets the latch to turn off the FET on the main side of each channel
while setting the PWRGOOD terminal (pin 12) to the “L” level. The protection circuit closes both channels even
when an overvoltage is detected on only either.
Note that the time from the actuation of the timer circuit until the latch is set is equal to the short-circuit detection
time defined in “2. Setting Time Constant for Timer-Latch Short-Circuit Protection Circuit”.
Overvoltage detection voltage : VOVP
VOVP (V) =: 1.38 × (R1 (Ω) + R2 (Ω) ) / R2 (Ω) =: 1.12 × VO
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 6) to the "L" level to lower the VREF terminal (pin 8) voltage to 1.7 V (Min) or less. It can also be reset by
setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to the "L" level.
VO
(−INE2)
R1
−INE1
15
1
−
Error
Amp
+
1.23 V
OVP
Comp.
+
R2
−
1.38 V
PWRGOOD
12
10 µA
CTL
CTL1
CTL2
CSCP
11
VREF
S
R
Latch
UVLO
Latch2
<Timer-latch overvoltage protection circuit>
22
MB3889
■ TREATMENT OF UNUSED ILIM TERMINALS
When the overcurrent protection circuit is not used, the ILIM1 terminal (pin 25) and ILIM2 terminal (pin 23) should
be shorted to the SGND terminal (pin 6) .
7
ILIM1
25
ILIM2
23
SGND
<Operation Without Using the ILIM Terminals>
■ PROCESSING WITHOUT USING THE CSCP TERMINAL
When the timer-latch short-circuit protection circuit is not used, the CSCP terminal (pin 11) should be shorted
to SGND using the shortest possible connection.
7
SGND
11 CSCP
<Operation Without Using the CSCP Terminals>
■ TREATMENT OF UNUSED PWRGOOD TERMINALS
When the PWRGOOD terminal is not used, the PWRGOOD terminal (pin 12) should be shorted or open to the
SGND terminal.
7
SGND
"Open"
12 PWRGOOD
12 PWRGOOD
<Operation Without Using the PWRGOOD Terminals>
23
MB3889
■ OUTPUT STATES DURING PROTECTION CIRCUIT OPERATION
The table below lists the output states with each protection circuits actuated.
CH1
CH2
Output terminal
Protection circuit
OUT1-1
OUT2-1
OUT1-2
OUT2-2
PWRGOOD
CH1
L
L
L
L
L
CH2
CH1
Short-circuit protection
CH2
CH1
Overvoltage protection circuit
CH2
Under voltage lockout protection circuit
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
Overcurrent protection circuit
■ RESETTING THE LATCH OF EACH PROTECTION CIRCUIT
When the overvoltage, overcurrent, or short-circuit protection circuit detects each abnormality, it sets the latch
to fix the output at the "L" level. The PWRGOOD terminal (pin 12) is fixed at the "L" level upon abnormality
detection by each protection circuit.
To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal
(pin 6) to the "L" level to lower the VREF terminal (pin 8) voltage to 1.7 V (Min) or less. It can also be reset by
setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to the "L" level.
24
MB3889
■ NOTE ON IC’S INTERNAL POWER CONSUMPTION
The oscillation frequency of an IC and the total gate charge of FETs largely affects the internal dissipation of
the IC.
Pay attention to the following point with respect to the internal power consumption of the IC when applications
are used.
IB (mean current) is obtained from the following equation, assuming Qg1 and Qg2 as the total gate charges
applied to the gate capacitors (Ciss1, Ciss2, Crss1, Crss2) of external FETs Q1 and Q2.
Current per channel
IB (A) = I1 + I2
As the current consumption by the IC, excluding IB, is about 15 mA, the power consumption is obtained from the
following equation :
Power consumption : Pc
Pc (W) = 0.015 × VCC (V) + 2 × VCC (V) •IB (A) − VB (V) •IB (A)
Vin
VCC
24
IB
5V
22
30
VB
CVB
A
CB1
L1
Q1
I1
Drive
1-1
29
I2
28
VO1
Crss2
Crss1
OUT1-1
Ciss1
Q2
VS1
Ciss2
Drive
2-1
27
26
OUT2-1
PGND1
t
VOUT1-1
VOUT2-1
Bias current
Ibias1 =: 3 mA
I1
t1
Bias current
Ibias1 =: 3 mA
I2
t2
t
See “Power Consumption vs. Input Voltage” on the next page as a reference and use the above method of
obtaining the power consumption to design your application of the IC taking account of the “Power Dissipation
vs. Ambient Temperature” characteristic in the “TYPICAL CHARACTERISTICS” section.
25
MB3889
Power Consumption vs. Input Voltage (Qg Parameter)
1.5
Qg1 = Qg2 = 70 nC
1.4
1.3
Power consumption PC (W)
1.2
Qg1 = Qg2 = 50 nC
1.1
1.0
0.9
Qg1 = Qg2 = 30 nC
0.8
0.7
Qg1 = Qg2 = 20 nC
0.6
0.5
Qg1 = Qg2 = 10 nC
0.4
0.3
Ta = +25 °C
fOSC = 290 kHz
SW1 = OFF
SW2 = OFF
0.2
0.1
0.0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Input voltage Vin (V)
Power Consumption vs. Input Voltage (fOSC Parameter)
1.2
1.1
Power consumption PC (W)
1.0
fOSC = 500 kHz
0.9
0.8
0.7
fOSC = 300 kHz
0.6
0.5
fOSC = 200 kHz
0.4
fOSC = 100 kHz
fOSC = 10 kHz
0.3
Ta = +25 °C
Qg1 = Qg2 = 20 nC
SW1 = OFF
SW2 = OFF
0.2
0.1
0.0
5
6
7
8
9
10
11
12
13
14
15
Input voltage Vin (V)
26
16
17
18
19
20
MB3889
■ SAMPLE CIRCUIT
C16
0.1 µF
VCC
24
5.1 V
R13
430 Ω
R10
10 kΩ
R12
6.2 kΩ
VB Reg.
C10 FB1
0.022
2
µF
R9
13 kΩ
1
−INE1
CS1
3
C11
0.1 µF
PWM
+ Comp.1
+
−
L priority
Error
Amp1
−
+
+
1.23 V
OVP
+ Comp.1
VREF 3 µA
Max Duty 81%
Dtr ± 6%
Drv
1-1
Drv
2-1
−
100
kΩ
Buff
CTL1
CH1
L priority
Dead Time
Modulation 1
A
1.38 V
Current
Protection
Logic
9
Open : CH1 ON
CTL1 = H
L : CH1 OFF
6 kΩ
VTH = 1.4 V
OCP
Comp.1
−
+
118 µA
H: OVP
VB
22
D1
CB1
30
OUT1-1
29
VS1
28
OUT2-1
27
PGND1
26
VIN
AC/DC
Converter
(12 V)
CTL2
L priority
VREF 3 µA
Comp.2
+
+
−
Error
Amp2
−
+
+
1.23 V
OVP
+ Comp.2
Max Duty 81%
Dtr ± 6%
Drv
1-2
Drv
2-2
−
100
kΩ
Buff
1.38 V
Current
Protection
Logic
10
Open : CH2 ON
CTL2 = H
L : CH2 OFF
6 kΩ
VTH = 1.4 V
H: at OVP
H priority
SCP Comp. +
+
−
+
118 µA
150
µF
C5
0.1 µF
C6 0.1 µF B
Q2 L2
CB2
16
V O2
(5 V/5 A)
22
µH
OUT1-2
17
VS2
18
OUT2-2
19
PGND2
20
C26 C17
+
0.1
µF
82
µF
C7
+
150
µF
C8
0.1 µF
ILIM2
23
R5
1.3 kΩ
H: at OVP
H: at OCP
H: at SCP
Latch1
SQ
L: at protection
operation
R
CTL
CTL1
CTL2
S R
Latch
3.0 V
CT1
1.8 V
3.0 V
CT2
1.8 V
VREF
UVLO
PWRGOOD
12
10 µA
11
OCP
Comp.2
−
C4
+
H: at OVP
3.1 V
CTL
CTL1
CTL2
C14
0.01 µF
C25 C18
+
0.1
µF
82
µF
H: UVLO
release
H: at OVP
CSCP
22
µH
D2
CH2
L priority PWM
Dead Time
Modulation 2
R17
3.3 kΩ
C12 FB2
0.022
14
µF
R14
13 kΩ
15
−INE2
CS2
13
C13
0.1 µF
V O1
(2 V/10 A)
ILIM1
25
R1
1.3 kΩ
B
R16
120 Ω
R15
10 kΩ
C9
4.7 µF
C3 0.1 µF A
Q1 L1
to Error amp reference
1.23 V
bias
VCC
OSC
Latch2
VREF
Power
VR1 ON/OFF
CTL
45 pF
3.5 V
5
RT
R8
47 kΩ
8
VREF
7
SGND
N.C.
4
N.C.
21
CTL
6
Protection
control
signal
R4
100 kΩ
H : ON (Power/CH6)
L : OFF (Standby mode)
VTH = 1.4 V
C15
0.1 µF
27
MB3889
■ PARTS LIST
COMPONENT
ITEM
SPECIFICATION
VENDOR
PARTS NO.
Q1, Q2
Dual FETKYTM
Main sides:
VDS = 30 V, Qg = 9.9 nC (Max)
Synchronous sides:
VDS = 30 V, Qg = 20.7 nC (Max)
SBD: VF = 0.52 V (Max)
at IF = 1 A
IR
IRF7901D1
D1, D2
Diode
VF = 0.3 V (Max) , at IF = 10 mA
ROHM
RB495D
L1, L2
Coil
22 µH
3.5 A, 31.6 mΩ
TDK
SLF12565T220M3R5
C3, C6
C4
C5, C8
C7
C9
C10
C11, C13
C12
C14
C15, C16
C17, C18
C25, C26
Ceramics Condenser
OS-CONTM
Ceramics Condenser
OS-CONTM
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
OS-CONTM
0.1 µF
150 µF
0.1 µF
150 µF
4.7 µF
0.022 µF
0.1 µF
0.022 µF
0.01 µF
0.1 µF
0.1 µF
82 µF
50 V
6.3 V
50 V
6.3 V
10 V
50 V
50 V
50 V
50 V
50 V
50 V
16 V
TDK
SANYO
TDK
SANYO
TDK
TDK
TDK
TDK
TDK
TDK
TDK
SANYO
C1608JB1H104K
6SVP150M
C1608JB1H104K
6SVP150M
C3216JB1A475M
C1608JB1H223K
C1608JB1H104K
C1608JB1H223K
C1608JB1H103K
C1608JB1H104K
C1608JB1H104K
16SVP82M
R1, R5
R4
R8
R9
R10
R12
R13
R14
R15
R16
R17
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
1.3 Ω
100 Ω
47 kΩ
13 kΩ
10 kΩ
6.2 kΩ
430 Ω
13 kΩ
10 kΩ
120 Ω
3.3 kΩ
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
0.5 %
SUSUMU
SUSUMU
SUSUMU
SUSUMU
SUSUMU
SUSUMU
SUSUMU
SUSUMU
SUSUMU
SUSUMU
SUSUMU
RR0816P132D
RR0816P104D
RR0816P473D
RR0816P133D
RR0816P103D
RR0816P622D
RR0816P431D
RR0816P133D
RR0816P103D
RR0816P121D
RR0816P332D
Note : IR : International Rectifier Corp.
ROHM : ROHM Co., Ltd.
TDK : TDK Corporation
SANYO : SANYO Electric Co., Ltd.
SUSUMU : SUSUMU Electronics Corp.
Dual FETKY is a trademark of International Rectifier Corp.
OS-CON is a trademark of SANYO Electric Co., Ltd.
28
MB3889
■ REFERENCE DATA
Conversion Efficiency vs. Load Current (CH1)
100
Conversion efficiency η (%)
90
80
70
Vin = 8.5 V
Vin = 10 V
Vin = 12 V
60
Ta = + 25 °C
3.3 V output
CTL = 5 V
CTL1 = Open
CTL2 = “L” level
50
40
30
10 m
100 m
1
10
Load current IL (A)
Conversion Efficiency vs. Load Current (CH2)
100
Conversion efficiency η (%)
90
80
70
Vin = 8.5 V
Vin = 10 V
Vin = 12 V
60
Ta = + 25 °C
5 V output
CTL = 5 V
CTL1 = “L” level
CTL2 = Open
50
40
30
10 m
100 m
1
10
Load current IL (A)
(Continued)
29
MB3889
Switching Waveform (CH1)
VS1 (V)
12
Ta = + 25 °C
VIN = 12 V
CTL = 5 V
CTL1 = Open
CTL2 = “L”level
VO1 = 3 A
10
8
6
4
2
0
0
1
2
3
4
5
6
7
8
Expansion
9
10
t (µs)
Expansion
VS1 (V)
3
VS1 (V)
3
2
2
1
1
0
0
0
40
80 120 160 200 240 280 320 360 400
t (ns)
tD2
136 ns
0
40
80 120 160 200 240 280 320 360 400
t (ns)
tD1
84 ns
(Continued)
30
MB3889
Switching Waveform (CH2)
VS2 (V)
12
Ta = + 25 °C
VIN = 12 V
CTL = 5 V
CTL1 = “L”level
CTL2 = Open
VO1 = 3 A
10
8
6
4
2
0
0
1
2
3
4
5
6
7
8
Expansion
VS2 (V)
3
9
10
t (µs)
Expansion
VS2 (V)
3
2
2
1
1
0
0
0
40
80 120 160 200 240 280 320 360 400
t (ns)
tD2
148 ns
0
40
80 120 160 200 240 280 320 360 400
t (ns)
tD1
88 ns
(Continued)
31
MB3889
(Continued)
Soft-start Operating Waveform (CH1)
Ta = + 25 °C
VIN = 12 V
CTL1 = Open
CTL2 = “L”level
VO1 = 1.2 Ω
VO1 (V)
4
2
V O1
0
ts
39 ms
VCTL (V)
5
VCTL
0
0
10
20
30
40
50
60
70
80
90
100
(ms)
Soft-start Operating Waveform (CH2)
Ta = + 25 °C
VIN = 12 V
CTL1 = “L”level
CTL2 = Open
VO2 = 1.67 Ω
VO2 (V)
6
4
2
V O2
0
ts
37 ms
VCTL (V)
5
VCTL
0
0
10
20
30
40
50
60
70
80
90
100
(ms)
32
MB3889
■ NOTES ON USE
• Take account of common impedance when designing the earth line on a printed wiring board.
• Take measures against static electricity.
- For semiconductors, use antistatic or conductive containers.
- When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container.
- The work table, tools, and measuring instruments must be grounded.
- The worker must put on a grounding device containing 250 kΩ to 1 MΩ resistors in series.
• Do not apply a negative voltage.
- Applying a negative voltage of −0.3 V or less to an LSI may generate a parasitic transistor, resulting in
malfunction.
■ ORDERING INFORMATION
Part number
MB3889PFT
Package
Remarks
30-pin plastic TSSOP
(FPT-30P-M04)
33
MB3889
■ PACKAGE DIMENSION
30-pin plastic TSSOP
(FPT-30P-M04)
7.80±0.10(.307±.004)
"A"
Details of "A" part
0~8°
1.10(.043)
MAX
0.60±0.10
(.024±.004)
+0.20
4.40 –0.10
6.40±0.10
+.008
.173 –.004 (.252±.004)
INDEX
0.25(.010)
0.10±0.05
(.004±.002)
0.50(.020)
0.20±0.03
(.008±.001)
0.10(.004)
7.00(.276)
C
0.3865(.0152)
0.127±0.03
(.005±.001)
0.90±0.05
(.035±.002)
0.3865(.0152)
2001 FUJITSU LIMITED F30007SC-1-1
Dimensions in mm (inches)
34
MB3889
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0209
 FUJITSU LIMITED Printed in Japan