RICHTEK RT9245CGC

RT9245C
Multi-Phase PWM Controller for CPU Core Power Supply
General Description
Features
RT9245C is a multi-phase buck DC/DC controller
integrated with all control functions for AMD K8 CPU or
z
Multi-Phase Power Conversion with Automatic
Phase Selection
Intel ® GHz CPU which is VRD10.x-compliant. The
RT9245C could be operated with 2, 3 or 4 buck switching
stages operating in interleaved phase set automatically.
The multiphase architecture provides high output current
while maintaining low power dissipation on power devices
and low stress on input and output capacitors. The high
equivalent operating frequency also reduces the
component dimension and the output voltage ripple in load
transient.
z
6-bits VRD10.x or 5-bit K8 DAC Output with Active
Droop Compensation for Fast Load Transient
Smooth VCORE Transition at VID Jump
Power Stage Thermal Balance by DCR Current
Sense
Hiccup Mode Over-Current Protection
Programmable Switching Frequency (50kHz to
400kHz per Phase), Under-Voltage Lockout and SoftStart
High Ripple Frequency Times Channel Number
28-TSSOP Package
RoHS Compliant and 100% Lead (Pb)-Free
RT9245C implements both voltage and current loops to
achieve good regulation, response and power stage
thermal balance.
RT9245C applies the DCR sensing technology newly. The
RT9245C extracts the DCR of output inductor as sense
component to deliver a precise load line regulation and
good thermal balance for next generation processor
application.
Current sense setting, droop tuning, VCORE initial offset
and over current protection are independent on
compensation circuit of voltage loop. The feature greatly
facilitates the flexibility of CPU power supply design and
tuning. The DAC output of RT9245C supports AMD K8
5-bit VID and Intel® VRD10.x with 6-bit VID input, precise
offset value & smooth VCORE transient at VID jump. The
IC monitors the VCORE voltage for PGOOD and over-voltage
protection. Soft-start, over-current protection and
programmable under-voltage lockout are also provided to
assure the safety of microprocessor and power system.
The RT9245C comes to a small footprint package
TSSOP-28.
z
z
z
z
z
z
z
Applications
z
z
z
Intel® Processors Voltage Regulator : VRD10.x and AMD
K8
Low Output Voltage, High Current DC-DC Converters
Voltage Regulator Modules
Pin Configurations
(TOP VIEW)
VID4
VID3
VID2
VID1
VID0
VID125/VIDSEL
SGND
FB
COMP
PGOOD
DVD
SS
RT
VOSS
Ordering Information
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
PWM1
PWM2
PWM3
PWM4
CSP4
CSP2
CSP3
CSP1
GND
ADJ
IOUT
CSN
IMAX
TSSOP-28
Note :
RT9245C
Package Type
C : TSSOP-28
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commercial Standard)
DS9245C-02 March 2007
RichTek Pb-free and Green products are :
`RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.
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1
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2
VCC
3.3V
ATX
12V
VCC
5V
11
10
9
8
7
5
DVD
PGOOD
COMP
FB
SGND
VID0
VID2
VID1
R9
R8 100k 14
VOSS
RT
C3
12
SS
68nF
R7 20k 13
R4 10k
C2
2.7nF
5.6pF
VID0
4
25
26
19
20
21
22
IMAX
CSN
IOUT
15
16
17
ADJ 18
GND
CSP1
CSP3
CSP2
CSP4
23
PWM4 24
PWM3
PWM2
27
28
R19
6.8k
R18 100k
R17 470
R16
R15 33
C7
1uF
C6
1uF
C5
1uF
D5
R20 BAT254
100
C8
1uF
R14
470
R13 470
R12 470
R11 470
NC
PWM
VCC
C30
1uF
PGND
6
LGATE
PHASE
5
7
RT9619
8
BOOT
UGATE
5
7
3
NC
PWM
PGND
6
LGATE
5
Q5
Q7
IPD06N03LA
Q8
IPD09N03LA
R32
0
VIN
IPD06N03LA
Q6
IPD09N03LA
R29
0
VIN
IPD06N03LA
Q4
IPD09N03LA
Q3
NTC 10k
L2
0.3uH
L3
0.3uH
C34
3.3nF
R33
2.2
4.7uF
C31
C32
C33
1000uF 1000uF
C28
3.3nF
R30
2.2
4.7uF
C25
R27 240
C26
C27
1000uF 1000uF
C22
3.3nF
R26
2.2
4.7uF
C19
L4
0.3uH
C47 to C64
10uF x 18
+
C35 to C44
560uF x 10
+
VOUT
C15
1000uF
C21
C20
1000uF 1000uF
C16
3.3nF
R23
2.2
+
2
RT9619
8
1
BOOT
UGATE
4
VCC
7
PHASE
3
2
4
1
C24
1uF
PGND
6
LGATE
PHASE
R25
0
VIN
IPD06N03LA
Q2
+
C29
1uF
VCC
RT9619
8
BOOT
UGATE
2
PWM
3
NC
4
1
5
+
R31
10
D4
1N4148
ATX
12V
C23
1uF
R28
10 D3
1N4148
ATX
12V
C17
1uF
R24
10
D2
1N4148
C18
1uF
PGND
6
LGATE
+
R6
1.2k
C1
R3 15k
R5 10k
R2 1.5k
680pF
R1 0
VID2
VID1
VID3
PWM1
VCC
ATX
12V
NC
PWM
L1
0.3uH
+
3
1
VID4
2
/VIDSEL
6 VID125
C4
1uF
3
2
4.7uF
C13
+
VID3
VID4
VID125
RT9245C
C9
1uF
Q1
C14
1000uF
+
R10
10
VCC
5V
R22
0
VIN
C12
4.7uF
1uH
+
IPD09N03LA
C11
1000uF
RT9619
8
1
BOOT
UGATE
4
VCC
7
PHASE
C10
1uF
+
R21
10
D1
1N4148
ATX
12V
ATX
12V
RT9245C
Typical Application Circuit
Figure A. For Intel
DS9245C-02 March 2007
DS9245C-02 March 2007
NC
ATX
12V
7
13
12
11
10
9
8
R8 100k
R7 20k 14
C3
68nF
R4 10k
C2
10nF
33pF
VID0
4
5
VOSS
RT
SS
DVD
PGOOD
COMP
FB
SGND
VID0
VID2
VID1
VID3
25
26
IMAX
CSN
IOUT
ADJ
GND
CSP1
CSP3
CSP2
CSP4
R15
15
C7
1uF
C6
1uF
C5
1uF
R18
6.8k
R17 100k
16 R16 470
17
18 R14 33
19
20
21
22
23
PWM4 24
PWM3
PWM2
D5
R19 BAT254
100
C8
1uF
R13 1k
R12 1k
R11 1k
R10 1k
C29
1uF
VCC
3
2
4
1
3
2
4
1
5
7
C30
1uF
PGND
6
LGATE
PHASE
5
7
NC
PWM
VCC
PGND
6
LGATE
PHASE
5
7
RT9619
8
BOOT
UGATE
NC
PWM
VCC
RT9619
8
BOOT
UGATE
C24
1uF
PGND
6
LGATE
PHASE
RT9619
8
BOOT
UGATE
2
PWM
3
NC
4
1
5
Q3
Q5
Q7
IPD06N03LA
Q8
IPD09N03LA
R31
0
VIN
IPD06N03LA
Q6
IPD09N03LA
R28
0
VIN
IPD06N03LA
Q4
IPD09N03LA
R24
0
VIN
IPD06N03LA
Q2
NTC 10k
L2
1uH
L3
1uH
C34
3.3nF
R32
2.2
4.7uF
C31
L4
1uH
C33
C32
1000uF 1000uF
C28
3.3nF
R29
2.2
4.7uF
C25
R26 240
C27
C26
1000uF 1000uF
C22
3.3nF
R25
2.2
4.7uF
C19
C47 to C50
10uF x 4
+
C35 to C46
1000uF x 12
+
VOUT
C15
1000uF
C21
C20
1000uF 1000uF
C16
3.3nF
R22
2.2
+
R30
10 D4
1N4148
ATX
12V
C23
1uF
R27
10 D3
1N4148
ATX
12V
C17
1uF
R23
10 D2
1N4148
C18
1uF
PGND
6
LGATE
+
R6
1.2k
R5 10k
R3 15k
VCC 3.3V/FSBVTT
C1
VID2
VID1
3
27
28
NC
PWM
L1
1uH
+
R2 3k
C51
R1 0
VID4
PWM1
VCC
ATX
12V
3
2
4.7uF
+
VID3
1
VID4
2
/VIDSEL
6 VID125
C4
1uF
C9
1uF
Q1
C13
C14
1000uF
+
RT9245C
R38 820
R9
10
VCC
5V
R21
0
VIN
C12
4.7uF
1uH
+
IPD09N03LA
C11
1000uF
RT9619
8
1
BOOT
UGATE
4
VCC
7
PHASE
C10
1uF
+
R20
10
D1
1N4148
ATX
12V
ATX
12V
RT9245C
+
+
Figure B. For AMD
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3
RT9245C
Functional Pin Description
VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4),
VID0 (Pin 5)
IMAX (Pin 15)
Programmable over currert setting.
DAC voltage identification inputs for VRD10.x. These pins
are internally pulled to 1.2V (VRD10.x) or 2.1V (K8) if left
open.
CSN (Pin 16)
VID125/VIDSEL (Pin 6)
IOUT (Pin 17)
When this pin pull low or left pen -->VR10 VID input, pull
high to 5V -->K8.
Output Current Indication Pin. The current through IOUT
pin is proportional to the output current.
SGND (Pin 7)
ADJ (Pin 18)
VCORE differential sense negative input.
Current sense output for active droop adjust. Connect a
resistor from this pin to GND to set the load droop.
Current sense negative input of all channels.
FB (Pin 8)
Inverting input of the internal error amplifier.
GND (Pin 19)
Ground for the IC.
COMP (Pin 9)
Output of the error amplifier and input of the PWM
comparator.
CSP1 (Pin 20), CSP2 (Pin 22), CSP3 (Pin 21) & CSP4
(Pin 23)
PGOOD (Pin 10)
Current sense positive inputs for individual converter
channel current sense.
Power good open-drain output.
DVD (Pin 11)
Programmable power UVLO detection input. Trip threshold
= 1.0V at VDVD rising.
SS (Pin 12)
Connect this SS pin to GND with a capacitor to set the
soft-start time interval.
RT (Pin 13)
PWM1 (Pin 27), PWM2 (Pin 26), PWM3 (Pin 25) &
PWM4 (Pin 24)
PWM outputs for each driven channel. Connect these pins
to the PWM input of the MOSFET driver. For systems
which use 3 channels, connect PWM4 high. Two channel
systems connect PWM3 high.
VCC (Pin 28)
IC power supply. Connect this pin to a 5V supply.
Switching frequency setting. Connect this pin to GND with
a resistor to set the frequency.
VOSS (Pin 14)
VCORE initial value offset. Connect this pin to GND with a
resistor to set the negative offset value. Connect this pin
to VCC to set positive offset value.
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4
DS9245C-02 March 2007
VOSS
Offset Currrent
Source/Sink
FB
Error
Amplifier
COMP
PG Trip
Point
+
-
DAC + Droop
OVP Trip
Point
+
SS
SS
Control
-
DAC
GAP
Amplifier
-
+
ADJ
IOUT
Power On Reset
INH
-
+
-
+
-
+
-
+
OCP
Setting
Oscillator
&
Sawtooth
GND
SUM/M
Current
Correction
+
+
++
++
+
+
INH
MUX
PWMCP
INH
PWMCP
INH
PWMCP
INH
PWMCP
-
+
+
-
VID4
VID3
VID2
VID1
VID0
VID125
+
-
RT
PWM Logic
& Driver
PWM Logic
& Driver
PWM Logic
& Driver
PWM Logic
& Driver
CSA
MUX
Phase Control
-
+
-
PGOOD VCC DVD
+
+
DS9245C-02 March 2007
-
IMAX
CSN
CSP4
CSP3
CSP2
CSP1
PWM4
PWM3
PWM2
PWM1
RT9245C
Function Block Diagram
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5
RT9245C
Table 1. Output Voltage Program (VRD 10.x)
Pin Name
Nominal Output oltage DACOUT
ID4
ID3
ID2
ID1
ID0
ID125
1
1
1
1
1
X
No CPU
0
1
0
1
0
0
0.8375
0
1
0
0
1
1
0.8500
0
1
0
0
1
0
0.8625
0
1
0
0
0
1
0.8750
0
1
0
0
0
0
0.8875
0
0
1
1
1
1
0.9000
0
0
1
1
1
0
0.9125
0
0
1
1
0
1
0.9250
0
0
1
1
0
0
0.9375
0
0
1
0
1
1
0.9500
0
0
1
0
1
0
0.9625
0
0
1
0
0
1
0.9750
0
0
1
0
0
0
0.9875
0
0
0
1
1
1
1.0000
0
0
0
1
1
0
1.0125
0
0
0
1
0
1
1.0250
0
0
0
1
0
0
1.0375
0
0
0
0
1
1
1.0500
0
0
0
0
1
0
1.0625
0
0
0
0
0
1
1.0750
0
0
0
0
0
0
1.0875
1
1
1
1
0
1
1.1000
1
1
1
1
0
0
1.1125
1
1
1
0
1
1
1.1250
1
1
1
0
1
0
1.1375
1
1
1
0
0
1
1.1500
1
1
1
0
0
0
1.1625
1
1
0
1
1
1
1.1750
1
1
0
1
1
0
1.1875
1
1
0
1
0
1
1.2000
1
1
0
1
0
0
1.2125
To be continued
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6
DS9245C-02 March 2007
RT9245C
Table 1. Output Voltage Program (VRD 10.x)
Pin Name
Nominal Output oltage DACOUT
ID4
ID3
ID2
ID1
ID0
ID125
1
1
0
0
1
1
1.2250
1
1
0
0
1
0
1.2375
1
1
0
0
0
1
1.2500
1
1
0
0
0
0
1.2625
1
0
1
1
1
1
1.2750
1
0
1
1
1
0
1.2875
1
0
1
1
0
1
1.3000
1
0
1
1
0
0
1.3125
1
0
1
0
1
1
1.3250
1
0
1
0
1
0
1.3375
1
0
1
0
0
1
1.3500
1
0
1
0
0
0
1.3625
1
0
0
1
1
1
1.3750
1
0
0
1
1
0
1.3875
1
0
0
1
0
1
1.4000
1
0
0
1
0
0
1.4125
1
0
0
0
1
1
1.4250
1
0
0
0
1
0
1.4375
1
0
0
0
0
1
1.4500
1
0
0
0
0
0
1.4625
0
1
1
1
1
1
1.4750
0
1
1
1
1
0
1.4875
0
1
1
1
0
1
1.5000
0
1
1
1
0
0
1.5125
0
1
1
0
1
1
1.5250
0
1
1
0
1
0
1.5375
0
1
1
0
0
1
1.5500
0
1
1
0
0
0
1.5625
0
1
0
1
1
1
1.5750
0
1
0
1
1
0
1.5875
0
1
0
1
0
1
1.6000
Note: (1) 0 : Connected to GND
(2) 1 : Open
(3) X : Don't Care
DS9245C-02 March 2007
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7
RT9245C
Table 2. Output Voltage Program (K8)
VID4
VID3
VID2
VID1
VID0
Nominal Output Voltage DACOUT
0
0
0
0
0
1.550
0
0
0
0
1
1.525
0
0
0
1
0
1.500
0
0
0
1
1
1.475
0
0
1
0
0
1.450
0
0
1
0
1
1.425
0
0
1
1
0
1.400
0
0
1
1
1
1.375
0
1
0
0
0
1.350
0
1
0
0
1
1.325
0
1
0
1
0
1.200
0
1
0
1
1
1.275
0
1
1
0
0
1.250
0
1
1
0
1
1.225
0
1
1
1
0
1.200
0
1
1
1
1
1.175
1
0
0
0
0
1.150
1
0
0
0
1
1.125
1
0
0
1
0
1.100
1
0
0
1
1
1.075
1
0
1
0
0
1.050
1
0
1
0
1
1.025
1
0
1
1
0
1.000
1
0
1
1
1
0.975
1
1
0
0
0
0.950
1
1
0
0
1
0.925
1
1
0
1
0
0.900
1
1
0
1
1
0.875
1
1
1
0
0
0.850
1
1
1
0
1
0.825
1
1
1
1
0
0.800
1
1
1
1
1
Shutdown
Note: (1) 0 : Connected to GND
(2) 1 : Open
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8
DS9245C-02 March 2007
RT9245C
Absolute Maximum Ratings
z
z
z
z
z
z
z
z
(Note 1)
Supply Voltage, VCC ------------------------------------------------------------------------------------------Input, Output or I/O Voltage ---------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
TSSOP-28 -------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 4)
TSSOP-28, θJA -------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------ESD Susceptibility (Note 2)
HBM (Human Body Mode) ----------------------------------------------------------------------------------MM (Machine Mode) -------------------------------------------------------------------------------------------
Recommended Operating Conditions
z
z
z
7V
GND − 0.3V to VCC + 0.3V
1W
100°C/W
150°C
260°C
−65°C to 150°C
2kV
200V
(Note 3)
Supply Voltage, VCC ------------------------------------------------------------------------------------------- 5V ± 10%
Junction Temperature Range --------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range --------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
--
12
16
mA
4.0
4.2
4.5
V
0.2
0.5
--
V
0.94
1.0
1.06
V
--
50
--
mV
170
200
230
kHz
50
--
400
kHz
--
1.9
--
V
0.7
1.0
--
V
58
64
70
%
RRT = 20kΩ
0.9
1.0
1.1
V
VDAC ≥ 1V
−0.5
--
+0.5
%
VDAC < 1V
−5
--
+5
mV
VCC Supply Current
ICC
PWM 1,2,3,4 Open
POR Threshold
VCCRTH
VCC Rising
Hysteresis
VCCHYS
Nominal Supply Current
Power-On Reset
VDVD Threshold
Trip (Low to High)
VDVDTP
Hysteresis
VDVDHYS
Enable
Oscillator
Free Running Frequency
fOSC
Frequency Adjustable Range
fOSC_ADJ
Ramp Amplitude
ΔVOSC
Ramp Valley
VRV
RRT = 20kΩ
RRT = 20kΩ
Maximum Duty of Each Channel
RT Pin Voltage
VRT
Reference and DAC
DACOUT Voltage Accuracy
ΔVDAC
To be continued
DS9245C-02 March 2007
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9
RT9245C
Parameter
DAC (VID0-VID125) Input Low
DAC (VID0-VID125) Input High
Symbol
VILDAC
VIHDAC
Test Conditions
Min
Typ
Max
Units
VRD 10.x
--
--
0.4
V
K8
--
--
0.8
V
VRD 10.x
0.8
--
--
V
K8
1.2
--
--
V
2.5
3.5
4.5
kΩ
VRD 10.x
--
1.2
--
V
K8
--
2.1
--
V
0.9
1.0
1.1
V
--
60
--
dB
--
10
--
MHz
--
6
--
V/μs
100
--
--
μA
150
--
--
μA
DAC (VID0-VID125) pull up resistor
DAC Pull Up Voltage
VOSS Pin Voltage
VVOSS
RVOSS = 100kΩ
Error Amplifier
DC Gain
Gain-Bandwidth Product
GBW
Slew Rate
SR
COMP = 10pF
Current Sense GM Amplifier
CSN Full Scale Source Current
IISPFSS
CSN Current for OCP
Protection
Over-Voltage Trip (VFB − VDAC)
ΔOVT
RADJ = 0Ω
320
400
450
mV
IMAX Voltage
VIMAX
RIMAX = 20kΩ
0.9
1.0
1.1
V
--
--
0.2
V
Power Good
Output Low Voltage
VPGOODL IPGOOD = 4mA
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are
for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA is measured in the natural convection at TA = 25°C on a low effective single layer thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
www.richtek.com
10
DS9245C-02 March 2007
RT9245C
Typical Operating Characteristics
PWM vs. VCOMP
70
600
60
500
50
Duty Ratio (%)
F SW (kHz)
Adjustable Frequency
700
400
300
200
100
RRT = 16kΩ
40
30
20
10
0
0
0
10
20
30
40
50
60
70
0.5
1
1.5
2
2.5
RRT (kW)
(kΩ)
VCOMP (V)
Relationship Between Inductor
Current and VADJ
Power-Off @ IOUT = 60A
3
3.5
CH1:(5V/Div)
CH2:(5V/Div)
PWM
PWM
VSS
CH1:(5V/Div)
CH2:(20V/Div)
UGATE
CH3:(10V/Div)
CH4:(1V/Div)
VADJ
LGATE
CH3:(50mV/Div)
CH4:(20A/Div)
IL
VCOMP
Time (25ms/Div)
Time (10μs/Div)
Power-On @ IOUT = 60A
Ripple
CH1:(5V/Div)
CH2:(5V/Div)
VSS
PWM
V CORE
(5mV/Div)
UGATE
CH3:(20V/Div)
CH4:(10V/Div)
LGATE
L = 0.3μH, C = 5600μF
Time (10ms/Div)
DS9245C-02 March 2007
Time (2.5μs/Div)
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11
RT9245C
DVID at Rising
DVID at Falling
V CORE
(500mV/Div)
(500mV/Div)
V CORE
VID125
VID125
(2V/Div)
(2V/Div)
Time (50μs/Div)
Time (50μs/Div)
Transient Response
Transient Falling
(20mV/Div)
V CORE
V CORE
(20mV/Div)
Time (5ms/Div)
www.richtek.com
12
Time (500ns/Div)
DS9245C-02 March 2007
RT9245C
Application Information
RT9245C is a multi-phase DC/DC controller that precisely
regulates CPU core voltage and balances the current of
different power channels. The converter consisting of
RT9245C and its companion MOSFET driver RT9619
provides high quality CPU power and all protection
functions to meet the requirement of modern VRM.
VADJ = 8 x IX x RADJ
VADJ is then subtracted from VID_DAC output as the real
reference voltage at non-inverting input of the error amplifier
as shown if Figure 1. Consequently, load line slope is
calculated as :
Load Line =
Voltage Control
ΔVCORE 8 x RADJ x DCR
=
ΔICORE
N x RCSN
RT9245C senses the CPU VCORE by SGND pin to sense
the return of CPU to minimize the voltage drop on PCB
trace at heavy load. OVP is sensed at FB pin. The internal
high accuracy VID DAC provides the reference voltage for
VRD10.x compliance. Control loop consists of error
amplifier, multi-phase pulse width modulator, driver and
power components. As conventional voltage mode PWM
controller, the output voltage is locked at the VREF of error
amplifier and the error signal is used as the control signal
of pulse width modulator. The PWM signals of different
channels are generated by comparison of EA output and
split-phase sawtooth wave. Power stage transforms VIN
to output by PWM signal on-time ratio.
where N is the phase number of operation.
Current Balance
The chip detects FB for over voltage and power good
detection. The “hiccup mode” operation of over current
protection is adopted to reduce the short circuit current.
The in-rush current at the start up is suppressed by the
soft start circuit through clamping the pulse width and
output voltage.
RT9245C senses the inductor current via inductor's DCR
for channel current balance and droop tuning. The
differential sensing GM amplifier converts the voltage on
the sense component (can be a sense resistor or the
DCR of the inductor) to current signal into internal balance
circuit.
The current balance circuit sums and averages the current
signals and then produces the balancing signals injected
to pulse width modulator. If the current of some power
channel is larger than average, the balancing signal
reduces that channels pulse width to keep current balance.
The use of single GM amplifier via time sharing technique
to sense all inductor currents can reduce the offset errors
and linearity variation between GMs. Thus it can greatly
improve signal processing especially when dealing with
such small signal as voltage drop across DCR.
IVOSS /4
RCSN
DAC
EA
+
VADJ
8IX
+
-
VCORE
RADJ
Figure 1. Load Line and Offset Function
Fault Detection
Phase Setting and Converter Start Up
RT9245C interfaces with companion MOSFET drivers (like
RT9619, RT9607 series) for correct converter initialization.
The tri-state PWM output (high, low and high impedance)
senses its interface voltage when IC POR acts (both VCC
and DVD trip). The channel is enabled if the pin voltage is
1.2V less than VCC. Tie the PWM to VCC and the
corresponding current sense pins to GND or left float if
the channel is unused. For example, for 3-Channel
application, connect PWM4 high.
Current Sensing Setting
Droop & Load Line Setting
RT9245C injects averaged current IX into the resistor RADJ
connected to ADJ pin to generate a load-currentdependent voltage RADJ for droop setting :
DS9245C-02 March 2007
RT9245C senses the current flowing through inductor via
its DCR for channel current balance and droop tuning.
www.richtek.com
13
RT9245C
The differential sensing GM amplifier converts the voltage
on the sense component (can be a sense resistor or the
DCR of the inductor) to current signal into internal circuit
(see Figure 2).
L
VC
= R × C VC = DCR × IL I X =
DCR
R CSN
L
Figure 5 shows the time sharing technique of GM amplifier.
We apply test signal at phase 4 and observe the waveforms
at both pins of GM amplifier. The waveforms show time
sharing mechanism and the perfomance of GM to hold
both input pins equal when the shared time is on.
Time Sharing of GM
DCR
CH1:(2V/Div)
CH2:(50mV/Div)
CH3:(50mV/Div)
+VCR
C
PWM3
+
-
RCSN
GMx
VCSP4
Ix
Figure 2. Current Sense Circuit
Figure 3 is the test circuit for GM. We apply test signal at
GM inputs and observe its signal process output at ADJ
pin. Figure 4 shows the variation of signal processing of
all channels. We observe zero offsets and good linearity
between phases.
CSPX
ADJ
+
VADJ
-
VC
SUM/M
MUX
RADJ
1k
+
GM
-
CSN
RCSN
1k
Ix
Figure 3. The Test Circuit of GM
VCSP4
and
V CSN
V CSN
Time (1μs/Div)
Figure 5
Over Current Protection
RT9245C uses an external resistor R IMAX to set a
programmable over current trip point. OCP comparator
compares each inductor current with this reference current.
RT9245C uses hiccup mode to eliminate fault detection
of OCP or reduce output current when output is shorted
to ground.
1 VIMAX
1 IL x DCR
x
⇔ x
2 RIMAX
3
RCSN
GM
300
OCP Comparator
250
+
VADJ (mV)
200
-
150
100
VIMX
1/3 IX
1/2 IIMAX
OCP
Setting
RIMX
50
0
0
25
50
75
100
VC (mV)
125
150
Figure 6. Over Current Comparator
Figure 4. The Linearity of GMx
www.richtek.com
14
DS9245C-02 March 2007
RT9245C
Over Current Protection
CH1:(5V/Div)
CH2:(5V/Div)
PWM
For some case with preferable current ratio instead of
current balance, the corresponding technique is provided.
Due to different physical environment of each channel, it
is necessary to slightly adjust current loading between
channels. Figure 9 shows the application circuit of GM for
current ratio requirement. Applying KVL along L+DCR
branch and R1+C//R2 branch :
V
dV
dIL
+ DCR × IL = R1( C + C C ) + VC
dt
R2
dt
dV
R + R2
VC
= R1C C + 1
dt
R2
R2
For VC =
DCR × IL
R1 + R 2
L
VSS
Time (25ms/Div)
Figure 7. The Over Current Protection in the soft start
interval
Over Current Protection
CH1:(5V/Div)
CH2:(5V/Div)
Look for its corresponding conditions :
dIL
dI
+ DCR × IL = (R1//R2)× C × DCR × L + DCR × IL
dt
dt
L
Let
= (R1//R2)× C
DCR
L
Thus if
PWM
L
= (R1//R2) × C
DCR
Then VC =
VSS
Time (25ms/Div)
Figure 8. Over Current Protection at steady state
R2
× DCR × IL
R1+ R2
With internal current balance function, this phase would
share (R 1+R 2)/R 2 times current than other phases.
Figure 10 & 11 show different settings for the power stages.
Figure 12 shows the performance of current ratio compared
with conventional current balance function in Figure 13.
IL
0.3uH
0.6m
Current Ratio Setting
470
IL
L
DCR
+VC-
R1
C
1uF
470
Figure 10. GM4 Setting for current ratio function
IL
0.3uH
0.6m
R2
Figure 9. Application circuit for current ratio setting
470
1uF
Figure 11. GM1~3 Setting for current ratio function
DS9245C-02 March 2007
www.richtek.com
15
RT9245C
Load Line without dead zone at light loads
Current Ratio Function
35
1.31
IL4
30
1.3
20
V CORE (V)
I L (A)
w/o Dead Zone Compensation
RCSN open
1.29
25
IL3
IL2
IL1
15
10
1.28
1.27
1.26
RCSN = 82k
w/i Dead Zone Compensation
1.25
5
1.24
0
1.23
0
15
30
45
60
75
90
0
5
10
I OUT (A)
20
25
I OUT (A)
Figure 14
Figure 12
ILX
Current Balance Function
30
15
IL3
LX
RLX
RX
CX
+ V X
IL4
25
VOUT
+
IL1
I L (A)
20
-
GMx
IL2
15
Ix
10
RCSN
RCSN2
Figure 15. Application circuit of GM
5
Referring to Figure 15, IX is expressed as :
0
0
20
40
60
80
100
I OUT (A)
Figure 13
Dead Zone Elimination
RT9245C samples and holds inductor current at 50%
period by time-sharing sourcing a current IX to RCSN. At
light load condition when inductor current is not balance,
voltage VX across the sensing capacitor would be negative.
It needs a negative IX to sense the voltage. However,
RT9245C CANNOT provide a negative IX and consequently
cannot sense negative inductor current. This results in
dead zone of load line performance as shown in Figure
14. Therefore a technique as shown in Figure 15 is required
to eliminate the dead zone of load line at light load
condition.
www.richtek.com
16
IX =
VOUT ILX_50% x RLX ILX_50% x RLX
+
+
RCSN2
RCSN2
RCSN
(1)
where ILX_50% is the of inductor current at 50% period. To
make sure RT9245C could sense the inductor current,
right hand side of Equation (1) should always be positive:
VOUT ILX_50% x RLX ILX_50% x RLX
+
+
≥0
RCSN2
RCSN2
RCSN
(2)
Since RCSN2 >> RCSN in practical application, Equation (2)
could be simplified as :
VOUT ILX_50% x RLX
≥
RCSN2
RCSN
Figure 14 shows that dead zone of load line at light load
is eliminated by applying this technique.
DS9245C-02 March 2007
RT9245C
VID on the Fly
Output Voltage Offset Function
With external pull up resistors tied to VID pins, RT9245C
converters different VID codes from CPU into output
voltage. Figure 16 and Figure 17 show the waveforms of
VID on the fly function.
To meet Intel® requirement of initial offset of load line,
RT9245C provides programmable initial offset function.
External resistor RVOSS and voltage source at VOSS pin
V
generate offset current IVOSS = VOSS
R VOSS
, where VVOSS is 1V typical. One quarter of IVOSS flows
through RB1 as shown in Figure 18. Error amplifier would
hold the inverting pin equal to VDAC - VADJ. Thus output
voltage is subtracted from VDAC - VADJ for a constant offset
voltage.
RFB1
VCORE = VDAC - VADJ 4 × R VOSS
A positive output voltage offset is possible by connecting
RVOSS to VDD instead of to GND. Please note that when
RVOSS is connected to VDD, VVOSS is VDD − 2V typically
and half of IVOSS flows through RFB1. VCORE is rewritten as:
VID on the Fly (Falling)
PWM
V CORE
VFB
CH3:(500mV/Div)
CH4:(1V/Div)
CH1:(5V/Div)
CH2:(500mV/Div)
VID125
VDAC = 1.500, IOUT = 5A
VCORE = VDAC - VADJ +
RFB1
RVOSS
Time (25μs/Div)
Voltage Offset Function
Figure 16
1.284
1.282
VID on the Fly (Rising)
V CORE (V)
1.28
PWM
V CORE
VFB
CH1:(5V/Div)
CH2:(500mV/Div)
CH3:(500mV/Div)
CH4:(1V/Div)
1.278
1.276
1.274
1.272
1.27
1.268
VID125
50
60
70
90
100
110
ROSS (kΩ)
(kٛ )
VDAC = 1.500, IOUT = 5A
Figure 19
Time (25μs/Div)
Figure 17
80
Load Line Setting and Thermal Compensation
VADJ = 8 x AVG(IX) x RADJ
1/4 IVOSS
RB1
EA
+
VOUT = VDAC - VADJ
AVG(IX) is a PTC current. By properly use an NTC resistor
at ADJ. Load line can be thermally compensated.
VDAC-VADJ
Figure 18. Offset Setting
DS9245C-02 March 2007
www.richtek.com
17
RT9245C
PGOOD Function
If the fault condition is OV, V(SS) and PGOOD will be pulled
During start-up, RT9245C will detect 5VCC and 12VIN
(through DVD pin). In Figure 21, 5VCC or 12VIN is not ready
during T1. V(SS) (in Figure 20) is pulled to GND by FAULT.
V(EAP) is also equal to GND. V(FB) and VOUT will try to
follow V(EAP) thus both V(FB) and VOUT are equal to GND
during T1. During T2, both 5VCC and 12VIN are ready,
FAULT = low, OPSS starts charging up CSS. In the design
of RT9245C, ISS (the maximal current sink and source
capability of OPSS) is limited and time-variant. During T2
(V1 = 0.4V > V(SS) > 0), ISS(T2) is equal to about 10uA.
low immediately also. RT9245C will try to turn on low
side MOSFET and turn off high side MOSFET. VOUT will
fall quickly to protect CPU from high voltage. The typical
waveform is shown in Figure 23.
T2 = CSS x
V1
ISS(T2)
Z2
VOUT
FB
Z1
5VCC
VDAC
+
-
OPSS
N1
EA
+
COMP
EAP
≅ 4x10 4 x CSS
SS
FAULT
After V(SS) > V1, ISS changes to about 20uA. The rising
speed of V(SS) becomes about 2 times faster than in T1.
In Figure 20, MOSFET N1 will turn on only if V(SS) > VTH_N1
(threshold voltage of N1)
on, V(EAP) is still 0V.
CSS
Figure 20. Soft Start Circuit
≅ 0.7V = V2. Before N1 turns
5VCC_ready
and DVD_ready
(V2 - V1)
T3 = CSS x
≅ 1.5x10 4 x CSS
ISS(T3)
PGOOD
After V(SS) > V2, MOSFET N1 turns on, V(EAP) starts rising.
ISS(T4) is still equal to about 20uA. V(SS,EAP) is equal to
VTH_N1. Due to the body effect of MOSFET N1, VTH_N1
increases with higher V(EAP). For example, if VOUT target
is 1.4V, V(SS,EAP) will be equal to about 0.7V at the
beginning of T4 and equal to about 1.1V at the end of T4.
T4 = CSS x
(V4 - V2)
≅ 9x10 4 x CSS
ISS(T4)
At the end of T4, VOUT is very close to the target (within
the range of ±40mV). An internal 1ms timer starts. After
about 1ms(T5), The open-drain output PGOOD releases.
After PGOOD releases, ISS(T6) becomes about 320uA to
accelerate OPSS. RT9245C enters normal operation mode
and is capable to follow VID on the fly.
When any of the fault conditions happens, V(SS) and
PGOOD will be pulled low immediately. If the fault condition
is one of 5VCC low, DVD low, OC or VID_OFF, RT9245C
will try to turn off both high side MOSFET and low side
MOSFET. VOUT will fall slowly to avoid negative VOUT. The
typical waveform is shown in Figure 22.
www.richtek.com
18
V4
V(SS)
V3
VOUT
V2
V1
T2
T1
T3
T4
T5
T6
Figure 21. Soft Start Waveform
PGOOD
V(SS)
VOUT
5VCC_Low + DVD_Low + OC + VID_OFF
Figure 22. Waveform for 5VCC_Low, DVD_Low, OC or
VID_OFF
DS9245C-02 March 2007
RT9245C
EA Rising Slew Rate
PGOOD
VFB
V(SS)
VOUT
OV
Figure 23. Waveform for OV
CH1:(500mV/Div)
CH2:(2V/Div)
VCOMP
Error Amplifier Characteristic
For fast response of converter to meet stringent output
current transient response, RT9245C provides large slew
rate capability and high gain-bandwidth performance.
Time (250ns/Div)
Figure 25. EA Falling Transient with 10pF Loading;
Slew Rate = 8V/us
4.7k
EA Falling Slew Rate
B 4.7k
EA
+
A
VDAC
VFB
VCOMP
Figure 26. Gain-Bandwidth Measurement by signal A
divided by signal B
CH1:(500mV/Div)
CH2:(2V/Div)
Time (250ns/Div)
Figure 24. EA Rising Transient with 10pF Loading; Slew
Rate = 8V/us
DS9245C-02 March 2007
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19
RT9245C
0dB
180°
Figure 27. EA Frequency Response with closed loop gain set at 0db to observe gain-bandwidth product; -3dB at
10.86MHz
Design Procedure Suggestion
PCB Layout
a.Output filter pole and zero (Inductor, output capacitor
value & ESR).
a.Kelvin sense for current sense GM amplifier input.
b.Refer to layout guide for other items.
b.Error amplifier compensation & sawtooth wave amplitude (compensation network).
Voltage Loop Setting
c.Kelvin sense for VCORE.
Design Example
Current Loop Setting
Given :
a.GM amplifier S/H current (current sense component
DCR, CSN pin external resistor value).
Apply for four phase converter
b.Over-current protection trip point (RIMAX resistor).
VCORE = 1.4V
VRM Load Line Setting
ILOAD = 30A to 125A
a.Droop amplitude (ADJ pin resistor).
VDROOP = 95mV with load (1mΩ Load Line)
b.No load offset (RCSN2)
OCP trip point set at 40A for each channel (S/H)
c.DAC offset voltage setting (VOSS pin & compen- sation
network resistor RB1).
DCR = 1mΩ of inductor at 25°C
Power Sequence & SS
VIN = 12V
L = 0.3μH
COUT = 5600μF with 1mΩ equivalent ESR.
DVD pin external resistor and SS pin capacitor.
www.richtek.com
20
DS9245C-02 March 2007
RT9245C
C2 5.6pF
1. Compensation Setting
a. Modulator Gain, Pole and Zero :
C3 680pF
From the following formula :
RB1
Modulator Gain = VIN/VRAMP = 12/1.9 = 6.3 (i.e 16dB)
1.5k
where VRAMP : Ramp amplitude of saw-tooth wave
RB2
C1
15k 2.7nF
EA
+
Figure 28. Type 3 compensation network of EA
LC Filter Pole = 3.88kHz and
The over all loop gain with load is shown in Figure 29 to
Figure 31.
ESR Zero = 28kHz
b. EA Compensation Network :
Select RB1 = 1.5k, RB2 = 15k, C1 = 2.7nF, C2 = 5.6pF,
C3 = 680pF and use the Type 3 compensation scheme
shown in Figure 28. By calculation.
1
FZ1 =
= 156kHz
2π x RB1 x C3
FZ2 =
FP =
Consider the temperature coef f icient of copper
3900ppm/°C,
1 × VIMAX ⇔ 1 × IL × DCR
3
R CSN
2 RIMAX
1 × 1V ⇔ 1 × 40A × 1.39m Ω
3
330 Ω
2 RIMAX
1
= 3.9kHz
2π x RB2 x C1
1
= 5.8kHz
2π x RB2 x (C2//C1)
Middle Band Gain = 10 (i.e. 20dB)
2. Over-Current Protection Setting
⇒ RIMAX = 8.9kΩ
3. Soft-Start Capacitor Selection
For most application cases, 0.1µF is a good engineering
value.
Figure 29. The Frequency Response with No Load
DS9245C-02 March 2007
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21
RT9245C
Figure 30. The Frequency Response with Middle Load
Figure 31. The Frequency Response with Heavy Load
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22
DS9245C-02 March 2007
RT9245C
Layout Guide
Place the high-power switching components first, and separate them from sensitive nodes.
1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense
resistors tied to CSP1,2,3,4 and CSN should be located not more than 0.5 inch from the IC and away from
the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible.
2. Switching ripple current path:
a. Input capacitor to high side MOSFET.
b. Low side MOSFET to output capacitor.
c. The return path of input and output capacitor.
d. Separate the power and signal GND.
e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points.
Keep them away from sensitive small-signal node.
f. Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via.
3. MOSFET driver should be closed to MOSFET.
4. The compensation, bypass and other function setting components should be near the IC and away from the noisy
power path.
SW1
L1
VOUT
VIN
RIN
COUT
CIN
RL
V
SW2
L2
Figure 32. Power Stage Ripple Current Path
DS9245C-02 March 2007
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23
RT9245C
Next to IC
+12V
+12V or +5V
0.1uF
VCC
BOOT
PWM
RT9619
CIN
LGATE
CBP
VOSS
LO1
PHASE
+5VIN
VCC
RT
CBOOT
UGATE
PWM
VCORE
COUT
Next to IC
COMP
CC
RCSN
RT9245C
RC
CSN
Locate next
to FB Pin
FB
PGND
RFB
Locate near MOSFETs
CSPx
ADJ
For Thermal Couple
SGND
GND
Figure 33. Layout Consideration
Figure 34. Layout of power stage
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24
DS9245C-02 March 2007
RT9245C
Outline Dimension
D
L
E1
E
e
A2
A
A1
b
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.850
1.200
0.033
0.047
A1
0.050
0.152
0.002
0.006
A2
0.800
1.050
0.031
0.041
b
0.178
0.305
0.007
0.012
D
9.601
9.804
0.378
0.386
e
0.650
0.026
E
6.300
6.500
0.248
0.256
E1
4.293
4.496
0.169
0.177
L
0.450
0.762
0.018
0.030
28-Lead TSSOP Plastic Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: [email protected]
DS9245C-02 March 2007
www.richtek.com
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