RT9246A Multi-Phase PWM Controller for CPU Core Power Supply General Description Features The RT9246A is a multi-phase buck DC/DC controller integrated with all control functions for GHz CPU VRM. The RT9246A controls 2 or 3 buck switching stages z operating in interleaved phase set automatically. The multiphase architecture provides high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. The high equivalent operating frequency also reduces the component dimension and the output voltage ripple in load transient. RT9246A controls both voltage and current loops to achieve good regulation, response & power stage thermal balance. Precise current loop using Inductor DCR as sense component builds precise load line for strict VRM DC & transient specification and also ensures thermal balance of different power stages. The settings of current sense, droop tuning, VCORE initial offset and over current protection are independent to compensation circuit of voltage loop. The feature greatly facilitates the flexibility of CPU power supply design and tuning. The DAC output of RT9246A supports K8 CPU by 5-bit VID input, precise initial value & smooth VCORE transient at VID jump. The IC monitors the VCORE voltage for PGOOD and over-voltage protection. Soft-start, over-current protection and programmable under-voltage lockout are also provided to assure the safety of microprocessor and power system. Ordering Information RT9246A Package Type C : TSSOP-28 Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) z Multi-Phase Power Conversion with Automatic Phase Selection K8 DAC Output with Active Droop Compensation for Fast Load Transient Smooth VCORE Transition at VID Jump Power Stage Thermal Balance by Inductor DCR Current Sense Hiccup Mode Over-Current Protection Programmable Switching Frequency (50kHz to 400kHz per Phase), Under-Voltage Lockout and Soft-Start High Ripple Frequency Times Channel Number z RoHS Compliant and 100% Lead (Pb)-Free z z z z z Applications AMD® AthlonTM 64 and OpteronTM Processors Voltage Regulator z Low Output Voltage, High Current DC-DC Converters z Voltage Regulator Modules z Pin Configurations (TOP VIEW) VID4 VID3 VID2 VID1 VID0 NC FBRTN FB COMP PGOOD DVD SS RT VOSS 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC PWM1 PWM2 PWM3 NC ISP1 ISP2 ISP3 NC GND ADJ IOUT ICOMMON IMAX TSSOP-28 Note : RichTek Pb-free and Green products are : `RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. `Suitable for use in SnPb or Pb-free soldering processes. `100% matte tin (Sn) plating. DS9246A-04 March 2007 www.richtek.com 1 www.richtek.com 2 R25 1k R6 1k R5 9.1k ATX_12V C2 C3 10nF VID0 VID1 VID2 ATX_5V C1 NC R1 3k VID4 VID3 R7 13k C4 0.1uF R4 1k R3 10k R2 15k 33pF 1 VID4 VOSS RT SS DVD PGOOD R27 1k VCC 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VCOREFB_H IMAX ICOMMON IOUT ADJ GND NC ISP3 ISP2 ISP1 NC PWM3 PWM2 PWM1 RT9246A COMP FB FBRTN NC VID0 VID1 VID2 VID3 R26 1k R8 1M 14 13 12 11 10 9 8 7 6 5 4 3 2 C6 R17 1k R18 82k R16 300 R15 1k R13 300 C5 1uF R9 10 ATX_5V R14 0 NC C7 1uF NC R22 C8 1uF NC R23 R24 NC VCORE 1uF C9 R21 430 R20 430 R19 430 C26 1uF D3 1N4148 R38 10 ATX_12V C20 1uF R33 10 D2 1N4148 ATX_12V C17 1uF D1 1N4148 R28 10 ATX_12V VCC 2 4 1 LGATE PHASE UGATE LGATE PHASE UGATE LGATE PHASE UGATE PGND 6 PWM VCC BOOT RT9619 C25 1uF PGND 6 PWM VCC BOOT RT9619 C19 1uF PGND 6 PWM R39 0 2 4 1 C16 1uF 5 7 8 5 7 8 5 7 8 C12 1000uF R35 0 R31 0 R30 0 R41 0 R40 0 R36 0 C11 10uF C10 10uF RT9619 BOOT R34 0 2 4 1 R29 0 ATX_12V L1 1uH Q6 Q5 VIN Q4 Q3 VIN Q2 Q1 VIN C13 10uF C27 10uF C21 10uF 10uF C28 10uF C22 10uF C14 C30 3.3nF R42 2.2 R43 NTC L4 0.3uH 1000uF C29 C24 3.3nF R37 2.2 L3 0.3uH C23 1000uF C18 3.3nF R32 2.2 L2 0.3uH C15 1000uF C41 to C58 22uF x 18 C31 to C40 560uF x 10 VCORE RT9246A Typical Application Circuit DS9246A-04 March 2007 RT9246A Functional Pin Description VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4), VID0 (Pin 5) SS (Pin 12) DAC voltage identification inputs for K8. These pins are internally pulled to 2.2V if left open. Connect this SS pin to GND with a capacitor to set the soft-start time interval and to smooth VCORE transient at VID Jump. NC (Pin 6, Pin 20, Pin 24) RT (Pin 13) No Input Connection Switching frequency setting. Connect this pin to GND with a resistor to set the frequency. FBRTN (Pin 7) VCORE differential sense return. VOSS (Pin 14) FB (Pin 8) VCORE initial value offset. Connect this pin to GND with a resistor to set the offset value. Inverting input of the internal error amplifier. IMAX (Pin 15) COMP (Pin 9) Output of the error amplifier and input of the PWM comparator. Over-Current protection set. ICOMMON (Pin 16) Common negative input of current sense amplifiers for all three channels. PGOOD (Pin 10) Power good open-drain output. IOUT (Pin 17) DVD (Pin 11) Programmable power UVLO detection or converter enable input. Output current indication pin. The current through IOUT pin is proportional to the output current. ADJ (Pin 18) 700 Current sense output for active droop adjust. Connect a resistor from this pin to GND to set the load droop. 600 GND (Pin 19) 500 IC ground. 400 ISP1 (Pin 23), ISP2 (Pin 22), ISP3 (Pin 21) 300 Current sense positive input pins for individual converter channel current sensing. Oscillator Ferquency (kHz) Oscillator Ferquency vs. RRT 200 PWM1 (Pin 27), PWM2 (Pin 26), PWM3 (Pin 25) 100 0 0 10 20 30 40 RRT (kΩ) (k◊ ) 50 60 70 PWM outputs for each driven channel. Connect these pins to the PWM input of the MOSFET driver. For systems which use 2 channels, connect PWM3 high. VCC (Pin 28) IC power supply. Connect this pin to a 5V supply. DS9246A-04 March 2007 www.richtek.com 3 VOSS Offset Currrent Source/Sink DAC + Droop FB ERROR AMP COMP PG Trip Point OVP Trip Point + - FBRTN SS SS Control GAP AMP - + + - DAC ADJ INH IOUT GND Power On Reset OCP Setting - + - + - + + - VID0 VID1 VID2 VID3 VID4 Oscillator & Sawtooth SUM/M Current Correction + + + + + + INH Mux PWMCP INH PWMCP INH PWMCP + - RT CSA Mux PWM Logic & Driver PWM Logic & Driver PWM Logic & Driver + + - PGOOD VCC DVD - + - www.richtek.com 4 IMAX ISP3 ISP2 ISP1 ICOMMON PWM3 PWM2 PWM1 RT9246A Function Block Diagram DS9246A-04 March 2007 RT9246A Table 1. Output Voltage Program VID4 VID3 VID2 VID1 VID0 Nominal Output Voltage DACOUT 0 0 0 0 0 1.550 0 0 0 0 1 1.525 0 0 0 1 0 1.500 0 0 0 1 1 1.475 0 0 1 0 0 1.450 0 0 1 0 1 1.425 0 0 1 1 0 1.400 0 0 1 1 1 1.375 0 1 0 0 0 1.350 0 1 0 0 1 1.325 0 1 0 1 0 1.200 0 1 0 1 1 1.275 0 1 1 0 0 1.250 0 1 1 0 1 1.225 0 1 1 1 0 1.200 0 1 1 1 1 1.175 1 0 0 0 0 1.150 1 0 0 0 1 1.125 1 0 0 1 0 1.100 1 0 0 1 1 1.075 1 0 1 0 0 1.050 1 0 1 0 1 1.025 1 0 1 1 0 1.000 1 0 1 1 1 0.975 1 1 0 0 0 0.950 1 1 0 0 1 0.925 1 1 0 1 0 0.900 1 1 0 1 1 0.875 1 1 1 0 0 0.850 1 1 1 0 1 0.825 1 1 1 1 0 0.800 1 1 1 1 1 Shutdown Note: (1) 0 : Connected to GND (2) 1 : Open DS9246A-04 March 2007 www.richtek.com 5 RT9246A Absolute Maximum Ratings z z z z z z z z (Note 1) Supply Voltage, VCC ------------------------------------------------------------------------------------------Input, Output or I/O Voltage ---------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C TSSOP-28 -----------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 4) TSSOP-28, θJA -------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------ESD Susceptibility (Note 2) HBM (Human Body Mode) ----------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------- Recommended Operating Conditions z z z 7V GND-0.3V to VCC+0.3V 1W 100°C/W 150°C 260°C −65°C to 150°C 2kV 200V (Note 3) Supply Voltage, VCC ------------------------------------------------------------------------------------------- 5V ± 10% Ambient Temperature Range --------------------------------------------------------------------------------- 0°C to 70°C Junction Temperature Range --------------------------------------------------------------------------------- 0°C to 125°C Electrical Characteristics (VCC = 5V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Units -- 12 -- mA 4.0 4.2 4.5 V 0.2 0.5 -- V 0.9 1.0 1.1 V -- 60 -- mV 170 200 230 kHz 50 -- 400 kHz -- 1.9 -- V -- 1.0 -- V 62 66 75 % RRT = 20kΩ 0.9 1.0 1.1 V VDAC ≥ 1V −1 -- +1 % VDAC < 1V −10 -- +10 mV VCC Supply Current Nominal Supply Current ICC PWM 1,2,3 Open POR Threshold VCCRTH VCC Rising Hysteresis VCCHYS Power-On Reset VDVD Threshold Input High VDVDTH Input Low VDVDHYS Enable Oscillator Free Running Frequency fOSC Frequency Adjustable Range fOSC_ADJ Ramp Amplitude ΔVOSC Ramp Valley VRV RRT = 20kΩ RRT = 20kΩ Maximum On-Time of Each Channel RT Pin Voltage VRT Reference and DAC DACOUT Voltage Accuracy ΔVDAC DAC (VID0-VID4) Input Low ΔVILDAC -- -- 0.8 V DAC (VID0-VID4) Input High ΔVIHDAC 1.2 -- -- V To be continued www.richtek.com 6 DS9246A-04 March 2007 RT9246A Parameter Min Typ Max Units DAC (VID0-VID4) Pull-up Voltage 2.0 2.2 2.4 V DAC (VID0-VID4) Pull-up Resistance 10 13 16 kΩ 0.9 1.0 1.1 V -- 65 -- dB -- 10 -- MHz -- 8 -- V/μs ICOMMON Full Scale Source Current 100 -- -- μA ICOMMON Current for OCP 150 -- -- μA 0.84 0.94 1.05 V 340 400 450 mV -- -- 0.2 V VOSS Pin Voltage Symbol VVOSS Test Conditions RVOSS = 100kΩ Error Amplifier DC Gain Gain-Bandwidth Product GBW Slew Rate SR CCOMP = 10pF Current Sense GM Amplifier Protection IMAX Voltage VIMAX Over-Voltage Trip (VFB- VDAC) ΔOVT RIMAX = 10k RADJ = 0 Power Good Output Low Voltage VPGOODL IPGOOD = 4mA Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θJA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. DS9246A-04 March 2007 www.richtek.com 7 RT9246A Typical Operating Characteristics Power On Duty Ratio vs. VCOMP 70 RRT = 16kΩ IOUT = 3A 60 Duty Ratio (%) V CC 50 (5V/Div) 40 (2V/Div) SS 30 VOUT (1V/Div) 20 PGOOD (5V/Div) 10 0 0.5 1 1.5 2 2.5 3 Time (25ms/Div) 3.5 VCOMP (V) Power Off Start Up IOUT = 3A V CC PWM (5V/Div) (5V/Div) SS (2V/Div) SS (2V/Div) VOUT COMP (1V/Div) (1V/Div) PGOOD V CORE (5V/Div) (1V/Div) Time (25ms/Div) Time (10ms/Div) VID Jump OVP Unit Gain FB (2V/Div) SS V CORE (2V/Div) (100mV/Div) PWM SS (2V/Div) (500mV/Div) Time (5ms/Div) www.richtek.com 8 Time (5ms/Div) DS9246A-04 March 2007 RT9246A Applications Information RT9246A is a multi-phase DC/DC controller specifically designed to deliver high quality power for next generation CPU. Phase currents are sensed by innovative timesharing DCR current sensing technique for channel current balance, droop tuning, and over current protection. Using one common GM amplifier for current sensing eliminates offset errors and linearity variation between GMs. As submilli-ohm-grade inductors are widely used in modern mother boards, slight mismatch of GM amplifiers offset and linearity results in considerable current shift between phases. The time-sharing DCR current sensing technique is extremely important to guarantee phase current balance at mass production. Converter Initialization, Phase Selection, and Power Good Function The RT9246A initiates only after two pins are ready: VCC pin power on reset (POR) and DVD pin is higher than 1V. VCC POR is to make sure RT9246A is powered by a voltage for normal work. The rising threshold voltage of VCC POR is 4.2V typically. At VCC POR, RT9246A checks PWM3 status to determine phase number of operation. Pull high PWM3 for two-phase operation. The unused current sense pin should be connected to GND or left floating. DVD is to make sure that ATX12V is ready for companion MOSFET drivers(RT960X series) to work normally. Connect a voltage divider from ATX12V to DVD pin as shown in the Typical Application Circuit. Make sure that DVD pin voltage is below its threshold voltage before drivers are ready and above its threshold voltage for minimum ATX12V during normal operation. If either one of VCC and DVD is not ready, RT9246A keeps its PWM outputs high impedance and the companion drivers turn off both upper and lower MOSFETs. After VCC and DVD are ready, RT9246A initiates its soft start cycle as shown in Figure 1. A time-variant internal current source charges the capacitor connected to SS pin. SS voltage ramps up piecewise linearly and locks VID_DAC output with a specified voltage drop. Consequently, VCORE is built up according to VID_DAC output. PGOOD output is tripped to high impedance when VCORE reaches VID_DAC DS9246A-04 March 2007 output with 1~2ms delay. An SS capacitor about 47nF is recommend for typical application. VCC POR and DVD ready SS VCORE PGOOD VID Jump 1~2ms 1~2ms 1~2ms Figure 1. Timming Diagram During Soft Start Interval Voltage Control CPU VCORE voltage is Kelvin sensed by FB and FBRTN pins and precisely regulated to VID_DAC output by internal high gain Error Amplifier (EA). The sensed signal is also used for power good and over voltage function. The typical OVP trip point is 400mV above VID_DAC output. RT9246A pulls PWM outputs low and latches up upon OVP trip to prevent CPU from damaging. It can only restart by resetting either VCC or DVD pin. The VID pins are internally pulled high to internal 2.2V with 13kΩ resistors and are easily interfaced with CPU VID outputs. The change of VID_DAC output at VID Jump is also smoothed by capacitor connected to SS pin. Consequently, VCORE shifts to its new position smoothly. DCR Current Sensing RT9246A adopts an innovative time-sharing DCR current sensing technique to sense the phase currents for phase current balance (phase thermal balance) and load line regulation as shown in Figure 2. Current sensing amplifier GM samples and holds voltages VX across the current sensing capacitor C X by turns in a switching cycle. According to the Basic Circuit Theory, if LX = RX x CX then VX = ILX x RLX RLX Consequently, the sensing current IX is proportional to inductor current ILX and is expressed as : IX = ILX x RLX RCOMM www.richtek.com 9 RT9246A LX RX RLX ILX CX + VX VCORE + T1 S/H CKT + - T2 Ix T3 T1 T4 RCOMM Figure 2 The sensed current IX is used for current balance and droop tuning as described as followed. Since all phases share one common GM, GM offset and linearity variation effect is eliminated in practical applications. As sub-milli-ohmgrade inductors are widely used in modern mother boards, slight mismatch of GM amplifiers offset and linearity results in considerable current shift between phases. The timesharing DCR current sensing technical is extremely important to guarantee phase current balance at mass production. Over Current Protection RT9246A uses an external resistor RIMAX connected to IMAX pin to generate a reference current IIMAX for over current protection: IIMAX= VIMAX RIMAX where VIMAX is 1.0V typical. OCP comparator compares each sensed phase current IX with this reference current as shown in Figure 3. Equivalently, the maximum phase current is calculated as: Phase Current Balance The sampled and held phase current IX are summed and averaged to get the averaged current IX . Each phase current IX then is compared with the averaged current. The difference between I X and IX is injected to corresponding PWM comparator. If phase current IX is smaller than the averaged current , RT9246A increases the duty cycle of corresponding phase to increase the phase current accordingly, vice versa. www.richtek.com 10 ILX(MAX)= 3 VIMAX RCOMM 2 RIMAX RLX OCP Comparator + 1/3 IX - 1/2 IIMAX Figure 3. Over Current Comparator RT9246A uses hiccup mode to eliminate nuisance detection of OCP or reduce output current when output is shorted to ground as shown in Figure 4 and 5. DS9246A-04 March 2007 RT9246A Over Current Protection (5V/Div) PWM (10A/Div) I CORE (2V/Div) VSS (500mV/Div) VCORE where N is the phase number of operation. The averaged current IX is also injected into the resistor RIOUT connected to IOUT pin for monitoring load current. Voltage at IOUT pin VIOUT is proportional to load current and is calculated as: VIOUT = 8 IX x RIOUT = VCORE 8 x ICORE x RADJ x RLX N x RCOMM Error Amp. + RFB1 IVOSS 4 Time (5ms/Div) VADJ Figure 4. The Over Current Protection in the soft start interval Over Current Protection 8IX + - DAC RADJ Figure 6. Load Line and Offset Function Output Voltage Offset Function RT9246A provides programmable initial offset function. External resistor RVOSS and voltage source at VOSS pin (5A/Div) generate offset current IVOSS = I CORE V VOSS R VOSS , where VVOSS is 1V typical. One quarter of IVOSS flows through RFB1 as shown in Figure 6. Error amplifier would hold the inverting pin equal to VDAC − VADJ. A constant offset voltage is consequently added to VDAC − VADJ as : (1V/Div) VSS Time (2.5ms/Div) VCORE = VDAC − VADJ + RFB1 4 x RVOSS Figure 5. Over Current Protection at steady state Current Ratio Setting Droop and Load Line Setting RT9246A injects averaged phase current IX into the resistor RADJ connected to ADJ pin to generate a loadcurrent-dependent voltage VADJ for droop setting: VADJ = 8IX RADJ VADJ is then subtracted form VID_DAC output as the real reference voltage at non-inverting input of the error amplifier as shown if Figure 6. Consequently, load line slope is calculated as: Load Line = Current ratio adjustment is possible as described below. It is important for achieving thermal balance in practical application where thermal conditions between phases are not identical. Figure 7 shows the application circuit of GM for current ratio requirement. According to Basic Circuit Theory, if LX = (RSX // RPX) x CX then RLX RPX VX = x ILX x RLX RSX+RPX ΔVCORE 8 x RADJ x RLX = ΔICORE N x RCOMM DS9246A-04 March 2007 www.richtek.com 11 RT9246A LX RSX RLX + ILX Phase Current Balance 40 35 Phase Current (A) With other phase kept unchanged, this phase would share (RPX+RSX)/RPX times current than other phases. Figure 8 and 9 show different current ratio setting for the power stage when Phase 3 is programmed 2 times current than other phases. Figure 10 and 11 compare the above current ratio setting results. VX CX 30 25 20 15 10 5 0 RPX 0 15 30 45 60 75 60 75 I CORE (A) VCORE Figure 10 + T Current Ratio Function 35 Figure 7 30 I L (A) 25 20 15 10 5 Figure 8. Phase 3 Setting for current ratio function 0 0 15 30 45 I OUT (A) Figure 11 Dead Zone Elimination Figure 9. Phase 1~2 Setting for current ratio function www.richtek.com 12 RT9246A samples and holds inductor valley current by time-sharing sourcing a current IX to RCOMM. At light load condition when averaged inductor current is smaller than half of peak-to-peak inductor ripple current, voltage VX across the sensing capacitor is negative at valley. It needs a negative IX to sense the voltage. However, RT9246A CANNOT provide a negative IX and consequently cannot sense negative valley inductor current. This results in dead zone of load line performance as shown in Figure 12. Therefore a technique as shown in Figure 13 is required to eliminate the dead zone of load line at light load condition. DS9246A-04 March 2007 RT9246A Load Line without dead zone at light loads 1.31 1.3V -5A × 1m Ω ≥ RCSN 330Ω 1.3 w/o Dead Zone Compensation RCSN open V CORE (V) 1.29 RCOMM = 330Ω, RADJ = 160Ω, VOUT = 1.300V RCSN ≤ 85.8kΩ 1.28 Choose RCSN = 82kΩ 1.27 Figure 12 shows that dead zone of load line at light load is eliminated by applying this technique. 1.26 RCSN = 82k w/i Dead Zone Compensation 1.25 Error Amplifier Characteristic 1.24 1.23 0 5 10 15 20 25 I OUT (A) For fast response of converter to meet stringent output current transient response, RT9246A provides large slew rate capability and high gain-bandwidth performance. Figure 12 ILX EA Falling Slew Rate LX RLX RX CX + V X VOUT VFB + - RCOMM GMx Ix 500mV/Div) (2V/Div) RCSN VCOMP Figure13. Application circuit of GM Time (250ns/Div) Referring to Figure 13, IX is expressed as: IX = VOUT ILX_V x RLX ILX_V x RLX + + RCSN RCSN RCOMM (1) EA Rising Slew Rate where ILX_V is the valley of inductor current. To make sure RT9246A could sense the valley current, right hand side of Equation (1) should always be positive: VOUT ILX_V x RLX ILX_V x RLX + + ≥ 0 RCSN RCSN RCOMM Figure 14. EA Rising Transient with 10pF Loading; Slew Rate=8V/us VFB (500mV/Div) (2) Since RCSN >> RCOMM in practical application, Equation (2) could be simplified as: VOUT ILX_V x RLX ≥ RCSN RCOMM For example, assuming the negative inductor valley current is −5A at no load, then for DS9246A-04 March 2007 VCOMP (2V/Div) Time (250ns/Div) Figure 15. EA Falling Transient with 10pF Loading; Slew Rate=8V/us www.richtek.com 13 RT9246A 4.7k B 4.7k EA + A VREF Figure 16. Gain-Bandwidth Measurement by signal A divided by signal B Design Procedure Suggestion a.Output filter pole and zero (Inductor, output capacitor value & ESR). DCR = 1mΩ of inductor at 25°C b.Error amplifier compensation & sawtooth wave amplitude (compensation network). COUT = 8000μF with 5mΩ equivalent ESR. L = 1.5μH 1. Compensation Setting Current Loop Setting a.GM amplifier S/H current (current sense component DCR, ISPX and ICOMMON pin external resistor value). b.Over-current protection trip point (RIMAX resistor). a. Modulator Gain, Pole and Zero: From the following formula: Modulator Gain =VIN/VRAMP =12/1.9 = 6.3 (i.e 16dB) where VRAMP : ramp amplitude of saw-tooth wave VRM Load Line Setting a.Droop amplitude (ADJ pin resistor). b.No load offset (RCSN) c.DAC offset voltage setting (VOSS pin and compensation network resistor RB1) Power Sequence & SS DVD pin external resistor and SS pin capacitor. LC Filter Pole = 1.45kHz and ESR Zero =3.98kHz b. EA Compensation Network: Select R1 = 4.7k, R2 = 15k, C1 = 12nF, C2 = 68pF and use the Type 2 compensation scheme shown in Figure 17. By calculation, the F Z = 0.88kHz, FP = 322kHz and Middle Band Gain is 3.19 (i.e 10.07dB). PCB Layout a.Sense for current sense GM amplifier input. C2 68pF b.Refer to layout guide for other items. Voltage Loop Setting RB2 RB1 4.7k C1 15k 12nF EA + Design Example Given: Figure 17. Type 2 compensation network of EA Apply for four phase converter VIN = 12V VCORE = 1.5V ILOAD(MAX) = 100A VDROOP = 100mV at full load (1mΩ Load Line) OCP trip point set at 35A for each channel (S/H) www.richtek.com 14 DS9246A-04 March 2007 RT9246A Layout Guide Place the high-power switching components first, and separate them from sensitive nodes. 1. Most critical path: The current sense circuit is the most sensitive part of the converter. The current sense resistors tied to ISP1,2,3 and ICOMMON should be located not more than 0.5 inch from the IC and away from the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible. R&C filter of choke should place close to PWM and the R & C connect directly to the pin of each output choke, use 10 mil differencial pair, and 20 mil gap to other phase pair. Less via as possible. 2. Switching ripple current path: a. Input capacitor to high side MOSFET. b. Low side MOSFET to output capacitor. c. The return path of input and output capacitor. d. Separate the power and signal GND. e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points.Keep them away from sensitive small-signal node. f . Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via. 3. MOSFET driver should be closed to MOSFET. SW1 L1 VOUT VIN RIN V COUT CIN SW2 RL L2 Figure 18. Power Stage Ripple Current Path DS9246A-04 March 2007 www.richtek.com 15 RT9246A Outline Dimension D L E1 E e A2 A A1 b Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.850 1.200 0.033 0.047 A1 0.050 0.152 0.002 0.006 A2 0.800 1.050 0.031 0.041 b 0.178 0.305 0.007 0.012 D 9.601 9.804 0.378 0.386 e 0.650 0.026 E 6.300 6.500 0.248 0.256 E1 4.293 4.496 0.169 0.177 L 0.450 0.762 0.018 0.030 28-Lead TSSOP Plastic Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)89191466 Fax: (8862)89191465 Email: [email protected] www.richtek.com 16 DS9246A-04 March 2007