STMICROELECTRONICS STW75NF30

STW75NF30
N-channel 300 V, 0.037 Ω, 60 A, TO-247
low gate charge STripFET™ Power MOSFET
Features
Type
VDSS
RDS(on)
max
ID
pW
STW75NF30
300 V
< 0.045 Ω
60 A
320 W
■
Exceptional dv/dt capability
■
Low gate charge
■
100% Avalanche tested
2
1
Application
■
3
TO-247
Switching applications
Description
This Power MOSFET series realized with
STMicroelectronics unique STripFET™ process
has specifically been designed to minimize input
capacitance and gate charge. It is therefore
suitable as primary switch in advanced highefficiency isolated DC-DC converters
Table 1.
July 2008
Figure 1.
Internal schematic diagram
Device summary
Order code
Marking
Package
Packaging
STW75NF30
75NF30
TO-247
Tube
Rev 3
1/12
www.st.com
12
Contents
STW75NF30
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
.......................... 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/12
.............................................. 8
STW75NF30
1
Electrical ratings
Electrical ratings
Table 1.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage (VGS = 0)
300
V
VGS
Gate-source voltage
± 20
V
ID
Drain current (continuous) at TC = 25 °C
60
A
ID
Drain current (continuous) at TC = 100 °C
37.8
A
Drain current (pulsed)
240
A
Derating factor
2.56
W/°C
Peak diode recovery voltage slope
12
V/ns
PTOT
Total dissipation at TC = 25 °C
320
W
TJ
Tstg
Operating junction temperature
Storage temperature
-55 to 150
°C
Value
Unit
0.39
°C/W
IDM
(1)
dv/dt(2)
1. Pulse width limited by safe operating area
2. ISD ≤ 60A, di/dt ≤ 200A/µs, VDD ≤ 80% V(BR)DSS
Table 2.
Symbol
Thermal resistance
Parameter
Rthj-case
Thermal resistance junction-case max
Rthj-amb
Thermal resistance junction-ambient max
50
°C/W
Tl
Maximum lead temperature for soldering
purpose
300
°C
Table 3.
Avalanche characteristics
Symbol
Parameter
Max. value
Unit
IAR
Avalanche current, repetitive or not-repetitive
(pulse width limited by TJ max)
50
A
EAS
Single pulse avalanche energy
(starting TJ = 25 °C, ID = IAR, VDD = 50 V)
400
mJ
3/12
Electrical characteristics
2
STW75NF30
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 4.
Symbol
On/off states
Parameter
Test conditions
Drain-source breakdown
voltage
ID = 1 mA, VGS = 0
IDSS
Zero gate voltage drain
current (VGS = 0)
VDS = Max rating,
VDS = Max rating @125 °C
IGSS
Gate body leakage current
(VDS = 0)
VDS = ± 20 V
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250 µA
RDS(on)
Static drain-source on
resistance
VGS= 10 V, ID= 30 A
V(BR)DSS
Table 5.
Symbol
Parameter
Forward transconductance
Ciss
Input capacitance
Output capacitance
Reverse Transfer
Capacitance
Crss
Typ.
Max.
Unit
300
2
V
1
10
µA
µA
±100
nA
3
4
V
0.037
0.045
Ω
Typ.
Max.
Unit
Dynamic
gfs(1)
Coss
Min.
Test conditions
VDS = 15 V, ID = 30 A
VDS = 25 V, f = 1 MHz,
VGS = 0
Min.
40
S
5930
837
110
pF
pF
pF
Equivalent output
capacitance
VDS = 0 to 240 V, VGS = 0
462
pF
RG
Intrinsic gate resistance
f = 1 MHz open drain
1.55
Ω
Qg
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 240 V, ID = 30 A,
164
36
69
nC
nC
nC
Coss eq.(2)
Qgs
Qgd
VGS = 10 V
(see Figure 15)
1. Pulsed: pulse duration = 300µs, duty cycle 1.5%
2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS
4/12
STW75NF30
Electrical characteristics
Table 6.
Symbol
td(on)
tr
td(off)
tf
Table 7.
Symbol
ISD
ISDM
(1)
VSD(2)
trr
Qrr
IRRM
trr
Qrr
IRRM
Switching times
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
Min.
Typ.
Max.
115
87
141
101
VDD = 150 V, ID = 30 A
RG = 4.7 Ω, VGS = 10 V,
(see Figure 14)
Unit
ns
ns
ns
ns
Source drain diode
Parameter
Test conditions
Min.
Typ.
Source-drain current
Source-drain current
(pulsed)
Max.
Unit
60
240
A
A
1.6
V
Forward on voltage
ISD = 60 A, VGS = 0
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 60 A,VDD = 60 V
di/dt = 100 A/µs
(see Figure 19)
252
2.5
20
ns
µC
A
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD =60 A, VDD = 60 V
di/dt = 100 A/µs
Tj = 150°C (see Figure 19)
316
3.7
23.2
ns
µC
A
1. Pulse with limited by maximum temperature
2. Pulsed: pulse duration = 300µs, duty cycle 1.5%
5/12
Electrical characteristics
STW75NF30
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
Figure 5.
Transfer characteristics
AM00116v1
ID
(A)
10µs
10
2
is
ea )
ar (on
ih s DS
t R
in x
n a
it o y m
ra b
pe d
O mite
li
10 1
100µs
1ms
10ms
10 0
10-1
10-1
Figure 4.
10 0
10 1
10 2
VDS(V)
Output characteristics
AM00117v1
ID(A)
VGS=10V
180
AM00118v1
ID(A)
180
160
160
140
140
6V
120
120
100
100
80
80
5V
60
60
40
40
20
20
4V
0
Figure 6.
10
20
0
VDS(V)
Normalized BVDSS vs temperature
Figure 7.
4
2
6
VGS(V)
Static drain-source on resistance
AM00124v1
BVDSS
(norm)
AM00122v1
RDS(on)
(Ω)
1.15
0.035
1.05
1.0
0.0345
0.95
0.9
0.034
0.85
0.8
-75 -50 -25
6/12
0.0335
0
25 50 75 100 125 150 TJ(°C)
5
10
15
20
25
30
ID(A)
STW75NF30
Figure 8.
Electrical characteristics
Gate charge vs gate-source voltage Figure 9.
AM00119v1
VGS
(V)
VGS=10V
ID=60A
VDD=240V
12
Capacitance variations
AM00120v1
C
(pF)
10 4
10
Ciss
8
10 3
6
Coss
4
10 2
Crss
2
0
50
100
150
Qg(nC)
200
Figure 10. Normalized gate threshold volatge
vs temperature
AM00125v1
VGS(th)
(norm)
1.1
101
10-1
10 0
10 2 VDS(V)
10 1
Figure 11. Normalized on resistancevs
temperature
RDS(on)
AM00126v1
2.5
1.0
2.0
0.9
1.5
0.8
1.0
0.7
0.6
0.5
0.5
-75 -50 -25 0
25 50 75 100 125 150 TJ(°C)
Figure 12. Source-drain diode forward
characteristics
0
-75 -50 -25
0
25
50
75 100 125 150 TJ(°C)
Figure 13. Maximum avalanche energy vs
temperature
AM00123v1
VDS
(V)
TJ=-50°C
0.9
AM00121v1
EAS
(mJ)
400
25°C
0.8
350
300
150°C
0.7
250
200
0.6
150
100
0.5
50
0.4
0
0
10
20
30
40
50
60
ISD(A)
0
30
60
90
120 TJ(°C)
7/12
Test circuits
3
STW75NF30
Test circuits
Figure 14. Switching times test circuit for
resistive load
Figure 15. Gate charge test circuit
Figure 16. Test circuit for inductive load
Figure 17. Unclamped inductive load test
switching and diode recovery times
circuit
Figure 18. Unclamped inductive waveform
8/12
Figure 19. Switching time waveform
STW75NF30
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
9/12
Package mechanical data
STW75NF30
TO-247 Mechanical data
mm.
Dim.
A
Min.
4.85
A1
2.20
2.60
b
1.0
1.40
b1
2.0
2.40
b2
3.0
3.40
c
0.40
0.80
D
19.85
20.15
E
15.45
15.75
e
Max.
5.15
5.45
L
14.20
14.80
L1
3.70
4.30
L2
18.50
øP
3.55
3.65
øR
4.50
5.50
S
10/12
Typ
5.50
STW75NF30
5
Revision history
Revision history
Table 8.
Document revision history
Date
Revision
Changes
23-Oct-2007
1
First release
27-May-2008
2
New value inserted in Table 5: Dynamic
15-Jul-2008
3
Document status promoted from preliminary data to datasheet
11/12
STW75NF30
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