ESDAULC6-3BP6 ESDAULC6-3BF2 ESD protection for high speed interface Main applications Where transient overvoltage protection in ESD sensitive equipment is required, such as: ■ Computers ■ Printers ■ Communication systems ■ Cellular phones handsets and accessories ■ Video equipment SOT-666 ESDAULC6-3BP6 Figure 1. Flip-Chip ESDAULC6-3BF2 Functional diagram Features ■ Ultra low capacitance 1.25 pF max. ■ Bi-directional protection ■ RoHS package 1 6 GND NC 2 5 NC I/O2 3 4 I/O3 Top view ESDAULC6-3BP6 Description The ESDAULC6-3Bxx is a monolithic application specific discrete device dedicated to ESD protection of high speed interfaces such as USB2.0. I/O1 Figure 2. A B I/O1 GND 1 I/O2 I/O3 2 Bump side view ESDAULC6-3BF2 Pin configuration I/O1 I/O2 I/O3 The device is ideal for applications where both reduced print circuit board space and power absorption capability are required. Benefits ■ Ultra low capacitance bidirectional ESD protection ■ Low PCB space consumption: 2.5 mm2 max footprint (1.7 mm2 for Flip-Chip) ■ Enhanced ESD protection: – 15 kV contact discharge – 15 kV air discharge ■ No insertion loss to 3.0 GHz ■ Ultra low leakage current ■ High reliability offered by monolithic integration GND Table 1. Order codes Part number Marking ESDAULC6-3BP6 3 ESDAULC6-3BF2 3B Complies with the following standards: IEC 61000-4-2 level 4: 8 kV (contact discharge) 15 kV (air discharge) MIL STD 883G-Method 3015-7: class 3B HBM (Human Body Model) July 2007 Rev 1 1/11 www.st.com 11 Characteristics 1 ESDAULC6-3BP6, ESDAULC6-3BF2 Characteristics Table 2. Absolute maximum ratings Symbol Parameter Peak pulse voltage (1) VPP Value (min.) Unit IEC 61000-4-2 contact discharge IEC 61000-4-2 air discharge 15 15 kV 150 °C -55 to +150 °C 260 °C Maximum operating junction temperature Tj Tstg Storage temperature range Maximum lead temperature for soldering during 10 s at 5 mm for case TL 1. For a surge greater than the maximum values, the diode will fail in short-circuit. Table 3. Electrical characteristics (Tamb = 25° C) Symbol Parameter VRM Stand-off voltage VBR Breakdown voltage VCL Clamping voltage IRM Leakage current IPP Peak pulse current αT Voltage temperature coefficient C Capacitance Rd Dynamic resistance Parameter VBR (1) I VCL VBR VRM IRM Slope: 1/Rd Test condition Min IR = 1 mA IRM VRM = 5 V Rd Square pulse, IPP = 6 A, tp = 2.5 µs IPP Typ 6.0 Unit 9.2 V 0.5 µA 1.2 -4/°C Ω SOT-666 1.0 1.25 Flip-Chip 1.25 1.5 SOT-666 0.75 0.9 Flip-Chip 0.9 1.20 10 pF Ci/o-i/o VI/O = 1.65 V, VCC = 4.3 V, F = 1 MHz, VOSC = 400 mV 1. Same value for I/O to I/O and I/O to GND 2/11 Max 1.4 αT VI/O = 0 V, F = 1 MHz, VOSC = 30 mV V VRM VBR VCL ESDAULC6-3BP6, ESDAULC6-3BF2 Figure 3. Characteristics Relative variation of peak pulse power versus initial junction temperature (SOT-666) Figure 4. PPP[Tj initial] / PPP[Tj initial=25°C) Relative variation of peak pulse power versus initial junction temperature (Flip-Chip) PPP [T j initial] / PPP [T j initial=25°C] 1.1 1.1 1.0 1.0 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 Tj(°C) Tj(°C) 0.0 0.0 0 0 25 Figure 5. 50 75 100 125 25 50 75 100 125 150 150 Peak pulse power versus exponential pulse duration (SOT-666) Figure 6. PPP(W) 1000 Peak pulse power versus exponential pulse duration (Flip-Chip) PPP (W) 1000 Tj initial=25°C Tj initial = 25 °C 100 100 tP(µs) tp(µs) 10 10 1 1 10 Figure 7. 10 100 100 Clamping voltage versus peak pulse current (typical values) (SOT-666) Figure 8. IPP(A) 10.0 10.0 Clamping voltage versus peak pulse current (typical values) (Flip-Chip) IPP(A) Square wave 2.5 µs Tj initial =25° C 8/20µs Tj initial=25°C 1.0 1.0 VCL(V) VCL(V) 0.1 0.1 5 5 10 15 20 25 10 15 20 25 30 30 3/11 Characteristics Figure 9. ESDAULC6-3BP6, ESDAULC6-3BF2 Junction capacitance versus reverse voltage applied (typical values) (SOT-666) Figure 10. Junction capacitance versus reverse voltage applied (typical values) (Flip-Chip) C(pF) C(pF) 2 1 F=1MHz VOSC=30mVRMS Tj=25°C F=1MHz VOSC=30mVRMS Tj=25°C 1 VLINE(V) VLINE(V) 0 0 0 1 2 3 4 5 0 1 2 4 5 Figure 12. Relative variation of leakage current versus junction temperature (typical values) (Flip-Chip) Figure 11. Relative variation of leakage current versus junction temperature (typical values) (SOT-666) IR [T j] / IR [Tj=25°C] IR[Tj] / IR[Tj=25°C] 100 100 VR =5V VR=5V 10 10 T j(°C) Tj(°C) 1 1 25 50 75 100 125 150 25 50 75 100 Figure 14. Remaining voltage after ESDAULC6-3BF2 during ESD 15 kV positive surge (air discharge) (Flip-Chip) 10 V/div 10 V/div Figure 13. Remaining voltage after ESDAULC6-3BP6 during ESD 15 kV positive surge (air discharge) (SOT-666) 0.1 µs/div 4/11 3 0.1 µs/div 125 ESDAULC6-3BP6, ESDAULC6-3BF2 Characteristics 10 V/div Figure 16. Remaining voltage after ESDAULC6-3BF2 during ESD 15 kV negative surge (air discharge) (Flip-Chip) 10 V/div Figure 15. Remaining voltage after ESDAULC6-3BP6 during ESD 15 kV negative surge (air discharge) (SOT-666) 0.1 µs/div 0.1 µs/div Figure 17. S21 attenuation measurement Figure 18. S21 attenuation measurement results of each channel (SOT-666) results of channel 1 (Flip-Chip) 0.00 dB 0.00 - 5.00 - 5.00 - 10.00 - 10.00 - 15.00 dB - 15.00 F (Hz) F (Hz) - 20.00 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M Line 1 Line 3 1.0G 3.0G 1.0M dB 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G Figure 20. Analog crosstalk measurements between channels (Flip-Chip) 0.00 - 20.00 - 20.00 - 40.00 - 40.00 - 60.00 - 60.00 - 80.00 - 80.00 - 100.00 - 100.00 - 120.00 3.0M Line 1 Figure 19. Analog crosstalk measurements between channels (SOT-666) 0.00 - 20.00 Line 2 dB - 120.00 F (Hz) F (Hz) - 140.00 - 140.00 1.0M Xtalk 3.0M 1/2 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G 1.0M Xtalk 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G 1/2 5/11 Application examples 2 ESDAULC6-3BP6, ESDAULC6-3BF2 Application examples USB 2.0 CONNECTOR Figure 21. USB2.0 (high speed) protection application schematic V BUS D+ IC to Protect DGND Figure 22. Audio jack protection application schematic Audio jack 100pF 330nH FM Tuner MEMORY CONNECTOR Figure 23. SIM card protection application schematic 6/11 RST CLK DATA GND SIM CARD PROCESSOR ESDAULC6-3BP6, ESDAULC6-3BF2 3 Ordering information scheme Ordering information scheme ESDA ULC 6 - 3 B xx ESD Array Ultra low capacitance Breakdown Voltage 6 = 6 Volts Number of lines protected 3 = 3 lines Type B = Bidirectional Packages F2 = Flip-Chip P6 = SOT-666 7/11 Package information 4 ESDAULC6-3BP6, ESDAULC6-3BF2 Package information ● Epoxy meets UL 94, V0 Table 4. SOT-666 dimensions Dimensions b1 Ref. Millimeters Inches L1 Min. L3 Typ. Max. Min. Typ. Max. A 0.45 0.60 0.018 0.024 A3 0.08 0.18 0.003 0.007 b 0.17 0.34 0.007 0.013 b1 0.19 D 1.50 1.70 0.059 0.067 E 1.50 1.70 0.059 0.067 E1 1.10 1.30 0.043 0.051 b D E1 0.27 0.34 0.007 0.011 0.013 A L2 E A3 e 0.50 0.020 L1 0.19 0.007 L2 0.10 0.30 0.004 0.012 e L3 0.10 Figure 24. SOT-666 footprint (dimensions in mm) 0.50 0.62 0.99 0.30 8/11 2.60 0.004 ESDAULC6-3BP6, ESDAULC6-3BF2 Package information Figure 25. Flip-Chip dimensions 650 µm ± 65 1.6 mm ± 50µm 1.0 mm ± 50 µm 500 µm ± 50 315 µm ± 50 1.1 mm ± 50 µm Figure 26. Flip-Chip footprint Figure 27. Flip-Chip marking Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week) Copper pad Diameter: 220 µm recommended Solder stencil opening: 330 µmrecommended E x x z y ww Solder mask opening recommendation: 300 µmrecommended Figure 28. Flip-Chip tape and reel specifications Dot identifying Pin A1 location 3.5 +/- 0.1 xxz yww xxz yww ST E ST E xxz yww All dimensions in mm ST E 8 +/- 0.3 0.71 +/- 0.05 1.75 +/- 0.1 Ø 1.5 +/- 0.1 4 +/- 0.1 4 +/- 0.1 User direction of unreeling In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 9/11 Ordering information 5 Ordering information Table 5. 6 Ordering information Part number Marking Package Weight Base qty Delivery mode ESDAULC6-3BP6 3 SOT-666 2.9 mg 5000 Tape and reel ESDAULC6-3BF2 3B Flip-Chip 2.22 mg 5000 Tape and reel Revision history Table 6. 10/11 ESDAULC6-3BP6, ESDAULC6-3BF2 Revision history Datet Revision 03-Jul-2007 1 Changes Initial release ESDAULC6-3BP6, ESDAULC6-3BF2 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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