SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999 D D D D D D D D D Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV Designed for Signaling Rates up to 630 Mbps Operates From a Single 3.3-V Supply Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100-Ω Load Propagation Delay Time – SN65LVDS105 . . . 2.2 ns (Typ) – SN65LVDS104 . . . 3.1 ns (Typ) Electrically Compatible With LVDS, PECL, LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT, SSTL, or HSTL Outputs With External Networks Driver Outputs Are High Impedance When Disabled or With VCC <1.5 V Bus-Pin ESD Protection Exceeds 16 kV SOIC and TSSOP Packaging SN65LVDS104 D OR PW PACKAGE (TOP VIEW) EN1 EN2 EN3 VCC GND A B EN4 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1Y 1Z 2Y 2Z 3Y 3Z 4Y 4Z SN65LVDS105 D OR PW PACKAGE (TOP VIEW) EN1 EN2 EN3 VCC GND A NC EN4 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 logic diagram (positive logic) ’LVDS104 1Y 1Z EN1 EN2 2Y 2Z EN3 3Y 3Z A B 4Y 4Z EN4 description The SN65LVDS104 and SN65LVDS105 are a differential line receiver and a LVTTL input (respectively) connected to four differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644 is a data signaling technique that offers low-power, lownoise coupling, and switching speeds to transmit data at speeds up to 655 Mbps at relatively long distances. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.) 1Y 1Z 2Y 2Z 3Y 3Z 4Y 4Z ’LVDS105 1Y 1Z EN1 EN2 2Y 2Z EN3 3Y 3Z A 4Y 4Z EN4 The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. Having the drivers integrated into the same substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input. This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream. The SN65LVDS104 and SN65LVDS105 are characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999 description (continued) The SN65LVDS104 and SN65LVDS105 are members of a family of LVDS repeaters. A brief overview of the family is provided in the table below. Selection Guide to LVDS Repeaters NO. INPUTS NO. OUTPUTS 2 LVDS 2 LVDS 16-pin D Dual multiplexed LVDS repeater SN65LVDS104 1 LVDS 4 LVDS 16-pin D 4-Port LVDS repeater SN65LVDS105 1 LVTTL 4 LVDS 16-pin D 4-Port TTL-to-LVDS repeater SN65LVDS108 1 LVDS 8 LVDS 38-pin DBT 8-Port LVDS repeater SN65LVDS109 2 LVDS 8 LVDS 38-pin DBT Dual 4-port LVDS repeater SN65LVDS116 1 LVDS 16 LVDS 64-pin DGG 16-Port LVDS repeater SN65LVDS117 2 LVDS 16 LVDS 64-pin DGG Dual 8-port LVDS repeater DEVICE SN65LVDS22 PACKAGE COMMENT Function Tables SN65LVDS104 SN65LVDS105 OUTPUT INPUT VID = VA - VB X INPUT OUTPUT #EN #Y #Z A #EN #Y #Z X Z Z L H L H X L Z Z H H H L VID ≥ 100 mV –100 mV < VID < 100 mV H H L Open H L H H ? ? X L Z Z VID ≤ –100 mV H L H X X H = high level, L = low level, Z = high impedance, ? = indeterminate, X = don’t care Z Z equivalent input and output schematic diagrams VCC VCC VCC 300 kΩ 300 kΩ EN and A (’LVDS105) Input A Input B Input 50 Ω 10 kΩ 7V 300 kΩ 7V 2 7V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5Ω Y or Z Output 7V SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to 4 V Voltage range, Enable inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to 6 V A, B, Y or Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to 4 V Electrostatic discharge (see Note 2); Y, Z, and GND . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:16 kV, B: 600 V All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:7 kV, B: 500 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. 2. Tested in accordance with MIL-STD-883C Method 3015.7 DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING OPERATING FACTOR‡ ABOVE TA = 25°C TA = 85°C POWER RATING D 950 mW 7.6 mW/°C 494 mW PW 774 mW 6.2 mW/°C 402 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow. recommended operating conditions MIN NOM Supply voltage, VCC 3 3.3 High-level input voltage, VIH 2 Low-level input voltage, VIL Magnitude of differential input voltage, VID 0.1 V Ť Ť g VIC Common-mode input voltage, ID 2 Operating free-air temperature, TA –40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT 3.6 V V 0.8 V 3.6 V V Ť Ť ID 2 VCC–0.8 V 85 °C 2.4 – V 3 SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999 SN65LVDS104 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VITH+ VITH– Positive-going differential input voltage threshold VOD Differential output voltage magnitude ∆VOD Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage ∆VOC(SS) Change in steady-state common-mode output voltage between logic states VOC(PP) Peak-to-peak common-mode output voltage See Figure 1 and Table 1 Negative-going differential input voltage threshold RL= 100Ω,, VID= ± 100 mV, See Figure 1 and Figure 2 See Figure 3 MIN Supply current II Input current (A or B inputs) –100 247 II(OFF) IIH Power-off Input current IIL Low-level input current (enables) IOS Short circuit output current Short-circuit IOZ IO(OFF) High-impedance output current CIN Input capacitance (A or B inputs) CO Output capacitance (Y or Z outputs) VCC= 1.5 V, VIH = 2 V High-level input current (enables) 340 mV 454 mV 50 1.125 1.375 –50 50 mV 25 150 mV 23 35 mA 3 8 mA –2 –11 –20 –1.2 –3 VI= 2.4 V VIL = 0.8 V VOY or VOZ = 0 V VOD = 0 V VO = 0 V or 2.4 V Power-off output current UNIT –50 Disabled VI = 0 V VI = 2.4 V MAX 100 Enabled, RL = 100Ω ICC TYP† VCC = 1.5 V, VO = 2.4 V VI = 0.4 sin (4E6πt) + 0.5 V VI = 0.4 sin (4E6πt) + 0.5 V, Disabled V µA 20 µA 20 µA 10 µA ±10 mA ±10 mA ±1 µA ±1 µA 3 pF 9.4 pF † All typical values are at 25°C and with a 3.3 V supply. SN65LVDS104 switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tPLH tPHL Propagation delay time, low-to-high-level output tr tf Differential output signal rise time tsk(p) tsk(o) Pulse skew (|tPHL – tPLH|) tsk(pp) tPZH tPZL tPHZ Propagation delay time, high-to-low-level output RL = 100Ω, CL = 10 pF pF, See Figure 4 Differential output signal fall time MIN TYP† MAX 2.4 3.2 4.2 ns 2.2 3.1 4.2 ns 0.3 0.8 1.2 ns 0.8 1.2 ns 150 500 ps Channel-to-channel output skew‡ Part-to-part skew§ 20 100 ps 1.5 ns Propagation delay time, high-impedance-to-high-level output 7.2 15 ns Propagation delay time, high-impedance-to-low-level output 8.4 15 ns 3.6 15 ns Propagation delay time, high-level-to-high-impedance output See Figure 5 0.3 UNIT tPLZ Propagation delay time, low-level-to-high-impedance output 6 15 ns † All typical values are at 25°C and with a 3.3 V supply. ‡ tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all drivers of a single device with all of their inputs connected together. § tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999 SN65LVDS105 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VOD Differential output voltage magnitude ∆VOD Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage ∆VOC(SS) Change in steady-state common-mode output voltage between logic states VOC(PP) Peak-to-peak common-mode output voltage ICC Supply current IIH IIL High-level input current IOS Short circuit output current Short-circuit IOZ IO(OFF) High-impedance output current CIN Input capacitance CO Output capacitance (Y or Z outputs) RL= 100Ω,, VID= ± 100 mV, See Figure 6 and Figure 7 See Figure 8 MIN TYP† MAX 247 340 454 50 1.125 1.375 –50 50 mV V 25 150 mV Enabled, RL = 100Ω 23 35 mA Disabled 0.7 6.4 mA 20 µA 10 µA ±10 mA ±10 mA ±1 µA ±1 µA VOY or VOZ = 0 V VOD = 0 V VO = 0 V or 2.4 V VCC = 1.5 V, VO = 2.4 V Power-off output current mV –50 VIH = 2 V VIL = 0.8 V Low-level input current UNIT 0.3 VI = 0.4 sin (4E6πt) + 0.5 V VI = 0.4 sin (4E6πt) + 0.5 V, Disabled 5 pF 9.4 pF † All typical values are at 25°C and with a 3.3 V supply. SN65LVDS105 switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT tPLH tPHL Propagation delay time, low-to-high-level output 1.7 2.2 3 ns Propagation delay time, high-to-low-level output 1.4 2.3 3.5 ns tr tf Differential output signal rise time 0.3 0.8 1.2 ns tsk(p) tsk(o) Pulse skew (|tPHL – tPLH|) tsk(pp) tPZH tPZL tPHZ RL = 100Ω, CL = 10 pF pF, See Figure 9 Differential output signal fall time 0.8 1.2 ns 150 500 ps Channel-to-channel output skew‡ Part-to-part skew§ 20 100 ps 1.5 ns Propagation delay time, high-impedance-to-high-level output 7.2 15 ns 8.4 15 ns 3.6 15 ns Propagation delay time, high-impedance-to-low-level output Propagation delay time, high-level-to-high-impedance output See Figure 10 0.3 tPLZ Propagation delay time, low-level-to-high-impedance output 6 15 ns † All typical values are at 25°C and with a 3.3 V supply. ‡ tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all drivers of a single device with all of their inputs connected together. § tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION II IOY A Y IIB VID IOZ VOD Z VIA V VOY B OY ) VOZ 2 VOC VIB VOZ Figure 1. ’LVDS104 Voltage and Current Definitions Table 1. SN65LVDS104 Minimum and Maximum Input Threshold Test Voltages APPLIED VOLTAGES RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMON-MODE INPUT VOLTAGE VIA 1.25 V VIB 1.15 V VID 100 mV VIC 1.2 V 1.15 V 1.25 V –100 mV 1.2 V 2.4 V 2.3 V 100 mV 2.35 V 2.3 V 2.4 V –100 mV 2.35 V 0.1 V 0V 100 mV 0.05 V 0V 0.1 V –100 mV 0.05 V 1.5 V 0.9 V 600 mV 1.2 V 0.9 V 1.5 V –600 mV 1.2 V 2.4 V 1.8 V 600 mV 2.1 V 1.8 V 2.4 V –600 mV 2.1 V 0.6 V 0V 600 mV 0.3 V 0V 0.6 V –600 mV 0.3 V 3.75 kΩ Y VOD Input Z 100 Ω 3.75 kΩ ± Figure 2. ’LVDS104 VOD Test Circuit 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0 V ≤ VTEST ≤ 2.4 V SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION 49.9 Ω ± 1% (2 Places) Y Input Input VI 1.4 V VI 1V Z VOC(PP) VOC CL = 10 pF (2 Places) VOC(SS) VO NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of VOC(PP) is made on test equipment with a –3 dB bandwidth of at least 300 MHz. Figure 3. ’LVDS104 Test Circuit and Definitions for the Driver Common-Mode Output Voltage A Y B Z Input 1.4 V 1.2 V 1V VIB Input VIA tPLH VOD tPHL 100 Ω ± 1 % VOD(H) Output CL = 10 pF (2 Places) 100% 80% 0V VOD(L) 20% 0% tf tr NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulsewidth = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 4. ’LVDS104 Test Circuit, Timing, and Voltage Definitions for the Differential output Signal POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION 49.9 Ω ± 1% (2 Places) Y 1 V or 1.4 V Z 1.2 V 1.2 V EN CL = 10 pF (2 Places) (see Note B) VOY VOZ 3V 1.5 V 0V EN VOY or VOZ tPZH tPHZ ≅ 1.4 V 1.25 V 1.2 V tPZL tPLZ 1.2 V VOZ 1.15 V or ≅1V VOY NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 5. ’LVDS104 Enable and Disable Time Circuit and Definitions IOY II Y A IOZ VOD V VOY Z OY ) VOZ 2 VOC VIA VOZ Figure 6. ’LVDS105 Voltage and Current Definitions 3.75 kΩ Y VOD Input Z 100 Ω 3.75 kΩ ± Figure 7. ’LVDS105 VOD Test Circuit 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0 V ≤ VTEST ≤ 2.4 V SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION 49.9 Ω ± 1% (2 Places) 3V Y A Input Input 0V Z VOC(PP) VOC CL = 10 pF (2 Places) VOC(SS) VO NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of VOC(PP) is made on test equipment with a –3 dB bandwidth of at least 300 MHz. Figure 8. ’LVDS105 Test Circuit and Definitions for the Driver Common-Mode Output Voltage Y Input Z 3V 1.5 V 0V Input VIA tPLH VOD tPHL 100 Ω ± 1 % VOD(H) Output CL = 10 pF (2 Places) 100% 80% 0V VOD(L) 20% 0% tf tr NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulsewidth = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 9. ’LVDS105 Test Circuit, Timing, and Voltage Definitions for the Differential output Signal POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION Y 49.9 Ω ± 1% (2 Places) 0.8 V or 2 V Z 1.2 V EN CL = 10 pF (2 Places) (see Note B) VOY VOZ 3V 1.5 V 0V EN VOY or VOZ tPZH tPHZ ≅ 1.4 V 1.25 V 1.2 V tPZL tPLZ 1.2 V VOZ 1.15 V or ≅1V VOY NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 10. ’LVDS105 Enable and Disable Time Circuit and Definitions 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999 TYPICAL CHARACTERISTIC SN65LVDS104 SUPPLY CURRENT vs SWITCHING FREQUENCY SN65LVDS105 SUPPLY CURRENT vs SWITCHING FREQUENCY 60 50 45 I CC – Supply Current – mA I CC – Supply Current – mA 55 50 VCC = 3.6 V 45 VCC = 3 V 40 35 VCC = 3.3 V 40 VCC = 3.6 V 35 VCC = 3 V 30 VCC = 3.3 V 25 30 All Outputs Loaded and Enabled 25 50 100 150 200 250 300 All Outputs Loaded and Enabled 20 350 50 100 150 f – Frequency – MHz 250 300 350 Figure 12 Figure 11 DRIVER DRIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 4 3.5 VCC = 3.3 V TA = 25°C VOH – High-Level Output Voltage – V VOL – Low-Level Output Voltage – V 200 f – Frequency – MHz 3 2 1 0 0 2 4 6 IOL – Low-Level Output Current – mA VCC = 3.3 V TA = 25°C 3 2.5 2 1.5 1 0.5 0 –4 –3 –2 –1 0 IOH – High-Level Output Current – mA Figure 13 Figure 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999 TYPICAL CHARACTERISTIC 3.6 3.5 3.4 VCC = 3.3 V 3.3 3.2 VCC = 3 V 3.1 VCC = 3.6 V 3.0 2.9 2.8 –50 –25 0 25 50 SN65LVDS104 HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE t PHL – High-To-Low Propagation Delay Time – ns t PLH – Low-To-High Propagation Delay Time – ns SN65LVDS104 LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 75 100 3.6 3.5 3.4 3.3 VCC = 3 V 3.2 VCC = 3.3 V 3.1 VCC = 3.6 V 3.0 2.9 2.8 –50 TA – Free–Air Temperature – °C –25 2.7 2.6 2.5 2.4 VCC = 3 V 2.3 2.2 VCC = 3.3 V VCC = 3.6 V –25 0 25 75 100 50 75 100 2.7 2.6 2.5 VCC = 3 V 2.4 2.3 VCC = 3.3 V 2.2 VCC = 3.6 V 2.1 2 –50 TA – Free–Air Temperature – °C –25 0 25 Figure 18 POST OFFICE BOX 655303 50 TA – Free–Air Temperature – °C Figure 17 12 50 SN65LVDS105 HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE t PHL – High-To-Low Propagation Delay Time – ns t PLH – Low-To-High Propagation Delay Time – ns SN65LVDS105 LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 2 –50 25 Figure 16 Figure 15 2.1 0 TA – Free–Air Temperature – °C • DALLAS, TEXAS 75265 75 100 SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999 APPLICATION INFORMATION A LVDS receiver can be used to receive various other types of logic signals. Figure 19 through Figure 28 show the termination circuits for SSTL, HSTL, GTL, BTL, LVPECL, PECL, CMOS, and TTL. VDD 25 Ω 50 Ω A 50 Ω 1/2 VDD B 0.1 µF LVDS Receiver Figure 19. Stub-Series Terminated (SSTL) or High-Speed Transceiver Logic (HSTL) VDD 50 Ω A 50 Ω B 1.35 V < VTT < 1.65 V 0.1 µF LVDS Receiver Figure 20. Center-Tap Termination (CTT) 1.14 V < VTT < 1.26 V VDD 1 kΩ 50 Ω 50 Ω A B 2 kΩ 0.1 µF LVDS Receiver Figure 21. Gunning Transceiver Logic (GTL) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999 APPLICATION INFORMATION Z0 Z0 A B 1.47 V < VTT < 1.62 V 0.1 µF LVDS Receiver Figure 22. Backplane Transceiver Logic (BTL) 3.3 V 3.3 V 50 Ω ECL 120 Ω 120 Ω 33 Ω 33 Ω A 50 Ω B 51 Ω 51 Ω LVDS Receiver Figure 23. Low-Voltage Positive Emitter-Coupled Logic (LVPECL) 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999 APPLICATION INFORMATION 5V 5V 50 Ω ECL 82 Ω 82 Ω 100 Ω 100 Ω A 50 Ω B 33 Ω 33 Ω LVDS Receiver Figure 24. Postive Emitter-Coupled Logic (PECL) 3.3 V 3.3 V 7.5 kΩ A B 7.5 kΩ 0.1 µF LVDS Receiver Figure 25. 3.3-V CMOS POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999 APPLICATION INFORMATION 5V 5V 10 kΩ 560 Ω A B 560 Ω 3.32 kΩ 0.1 µF LVDS Receiver Figure 26. 5-V CMOS 5V 5V 10 kΩ 470 Ω A B 3.3 V 4.02 kΩ 0.1 µF LVDS Receiver Figure 27. 5-V TTL 3.3 V 3.3 V 4.02 kΩ 560 Ω A B 3.01 kΩ 0.1 µF Figure 28. LVTTL 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 LVDS Receiver SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999 APPLICATION INFORMATION fail safe One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how it handles the open-input circuit situation, however. Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver will pull each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 10. The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the output to a high-level regardless of the differential input voltage. VCC 300 kΩ 300 kΩ A Rt = 100 Ω (Typ) Y B VIT ≈ 2.3 V Figure 29. Open-Circuit Fail Safe of the LVDS Receiver It is only under these conditions that the output of the receiver will be valid with less than a 100 mV differential input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeat the pullup currents from the receiver and the fail-safe feature. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999 MECHANICAL INFORMATION D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. 18 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999 MECHANICAL INFORMATION PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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