SN65LVDS22, SN65LVDM22 DUAL MULTIPLEXED LVDS REPEATERS SLLS315– DECEMBER 1998 D D D D D D D D D D Meets or Exceeds the Requirements of ANSI TIA/EIA–644–1995 Standard Designed for Signaling Rates Up to 400 Mbit/s ESD Protection Exceeds 12 kV on Bus Pins Operates from a Single 3.3-V Supply Low-Voltage Differential Signaling with Output Voltages of 350 mVinto: – 100-Ω Load (SN65LVDS22) – 50-Ω Load (SN65LVDM22) Propagation Delay Time; 4 ns Typ Power Dissipation at 400 Mbit/s of 150 mW Bus Pins are High Impedance When Disabled or With VCC Less Than 1.5 V LVTTL Levels are 5 V Tolerant Open-Circuit Fail Safe Receiver D PACKAGE (TOP VIEW) 1B 1A S0 1DE S1 2A 2B GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC VCC 1Y 1Z 2DE 2Z 2Y GND logic diagram (positive logic) 1A 1B 2 + _ 1 14 0 13 description 1 The SN65LVDS22 and SN65LVDM22 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The receiver outputs can be switched to either or both drivers through the multiplexer control signals S0 and S1. This allows the flexibility to perform splitter or signal routing functions with a single device. The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100-Ω load and receipt of 100 mV signals with up to 1 V of ground potential difference between a transmitter and receiver. The SN65LVDM22 doubles the output drive current to achieve LVDS levels with a 50 Ω load. 1DE 2DE S0 S1 2B 1Z 4 12 3 5 10 0 2A 1Y 6 11 + _ 7 1 2Y 2Z MUX Truth Table INPUT OUTPUT FUNCTION S1 S0 1Y/1Z 2Y/2Z 0 0 1A/1B 1A/1B Splitter 0 1 2A/2B 2A/2B Splitter The intended application of these devices and 1 0 1A/1B 2A/2B Router signaling technique is for both point–to–point baseband (single termination) and multipoint 1 1 2A/2B 1A/1B Router (double termination) data transmissions over controlled impedance media. The transmission media may be printed circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics). The SN65LVDS22 and SN65LVDM22 are characterized for operation from –40 C to 85 C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN65LVDS22, SN65LVDM22 DUAL MULTIPLEXED LVDS REPEATERS SLLS315– DECEMBER 1998 equivalent input and output schematic diagrams VCC VCC 300 kΩ 50 Ω S0, S1 Input 50 Ω 1DE, 2DE Input 7V 300 kΩ 7V VCC 300 kΩ VCC 300 kΩ 5Ω 10 kΩ A Input Y or Z Output B Input 7V 7V 2 7V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS22, SN65LVDM22 DUAL MULTIPLEXED LVDS REPEATERS SLLS315– DECEMBER 1998 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V Voltage range (DE, S0, S1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Input voltage range, VI (A or B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to Vcc+0.5 V Electrostatic discharge: A, B, Y, Z and GND (see Note 2) . . . . . . . . . . . . . . . . . . . . Class 3, A:12 kV, B:600 V All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:5 kV, B:500 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. 2. Tested in accordance with MIL-STD-883C Method 3015.7. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR‡ ABOVE TA = 25°C TA = 85°C POWER RATING D16 950 mW 7.6 mW/°C 494 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. recommended operating conditions MIN NOM MAX 3 3.3 3.6 Supply voltage, VCC High-level input voltage, VIH S0, S1, 1DE, 2DE Low-level input voltage, VIL S0, S1, 1DE, 2DE 2 Magnitude of differential input voltage, VID V Ť Operating free-air temperature, TA –40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0.8 V 0.6 V V Ť Ť ID 2 V V 0.1 Common-mode input voltage, VIC (see Figure 1) UNIT 2.4 – ID 2 Ť VCC–0.8 85 V V °C 3 SN65LVDS22, SN65LVDM22 DUAL MULTIPLEXED LVDS REPEATERS SLLS315– DECEMBER 1998 COMMON-MODE INPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE VIC – Common-Mode Input Voltage – V 2.5 MAX at VCC > 3.15 V MAX at VCC = 3 V 2 1.5 1 0.5 Min 0 0 0.1 0.2 0.3 0.4 0.5 0.6 VID – Differential Input Voltage – V Figure 1. Common-Mode Input Voltage vs Differential Input Voltage receiver electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VITH+ VITH– Positive-going differential input voltage threshold II Input current (A or B inputs) VI = 0 V VI = 2.4 V II(OFF) Power-off input current (A or B inputs) VCC = 0 V 4 Negative-going differential input voltage threshold POST OFFICE BOX 655303 MIN TYP† MAX UNIT 100 mV –100 • DALLAS, TEXAS 75265 –2 mV –20 –1.2 20 µA µA SN65LVDS22, SN65LVDM22 DUAL MULTIPLEXED LVDS REPEATERS SLLS315– DECEMBER 1998 receiver/driver electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VOD ∆VOD TEST CONDITIONS Differential output voltage magnitude Change in differential output out ut voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage ∆VOC(SS) Change in steady-state common-mode output voltage between logic states VOC(PP) Peak-to-peak common-mode output voltage See Figure 2 RL = 100 Ω (’LVDS22) (’LVDS22), RL = 50 Ω( LVDM22) Ω(’LVDM22) See Figure 3 MIN TYP† MAX UNIT 247 340 454 mV 50 –50 50 mV 1.125 1.375 –50 No Load ICC Supply current IIH High level input current High-level IIL Low level input current Low-level IOS IOZ S0, S1 DE S0, S1 Short circuit output current Short-circuit IO(OFF) Power-off output current CIN Input capacitance † All typical values are at 25°C and with a 3.3 V supply. mV 150 mV 8 12 13 20 RL = 50 Ω (‘LVDM22) 21 27 3 VIH = 5 20 –10 VIL = 0 0.8 8V 10 VOY or VOZ = 0 V, VOD = 0 V, ((’LVDS22) LVDS22) VOY or VOZ = 0 V, VOD = 0 V, ((’LVDM22) LVDM22) VCC = 0 V, mA 6 –10 µA µA –10 –10 –10 mA –10 VOD = 600 mV VO = 0 V or VCC High impedance output current High-impedance 50 RL = 100 Ω (‘LVDS22) Disabled DE 3 V VO = 3.6 V 0.015 ±1 0.015 ±1 0.015 ±1 3 µA µA pF differential receiver to driver switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT tPLH tPHL Differential propagation delay, low-to-high 4 6 ns Differential propagation delay, high-to-low 4 6 ns tsk(p) tr Pulse skew (|tPHL – tPLH|) Transition, low-to-high SN65LVDS22 tr tf Transition, low-to-high SN65LVDM22 Transition, high-to-low tf tPHZ Transition, high-to-low tPLZ tPZH tPZL tPHL_R1_Dx Propagation delay time, high-impedance-to-low-level output tPLH_R1_Dx tPHL_R2_Dx 0.5 CL = 10 pF, See Figure 4 ns 1 1.5 ns 0.8 1.3 ns SN65LVDS22 1 1.5 ns SN65LVDM22 0.8 1.3 ns Propagation delay time, high-level-to-high-impedance output 4 10 ns Propagation delay time, low-level-to-high-impedance output 5 10 ns 5 10 ns 6 10 ns Propagation delay time, high-impedance-to-high-level output See Figure 5 0.2 0.2 Channel to channel skew Channel-to-channel skew, receiver to driver‡ 0.2 tPLH_R2_Dx † All typical values are at 25°C and with a 3.3 V supply. ‡ These parametric values are measured over supply voltage and temperature ranges recommended for the device. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns 0.2 5 SN65LVDS22, SN65LVDM22 DUAL MULTIPLEXED LVDS REPEATERS SLLS315– DECEMBER 1998 PARAMETER MEASUREMENT INFORMATION DE A Y B Z Pulse Generator VI(B) 1.4 V VI(A) 1V Input (see Note A) VOD RL (see Note B) CL = 10 pF (2 Places) (see Note C) 100% 80% VOD 0 20% 0% tf tr NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. NOTES: B. RL = 100 Ω or 50 Ω ±1% C. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T. Figure 2. Test Circuit and Voltage Definitions for the Differential Output Signal DE A Y B Z Pulse Generator RL (see Note B) (2 Places) Input (see Note A) 1.4 V VI(A) 1V VOC(PP) (see Note D) VOC CL = 10 pF (2 Places) (see Note C) VI(B) VOC(SS) VCC NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. NOTES: B. RL = 100 Ω or 50 Ω ±1% C. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T. D. The measurement of VOC(PP) is made on test equipment with a –3 dB bandwidth of at least 300 MHz. Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS22, SN65LVDM22 DUAL MULTIPLEXED LVDS REPEATERS SLLS315– DECEMBER 1998 PARAMETER MEASUREMENT INFORMATION DE Y A Pulse Generator R D RL (see Note A) B Z 10 pF VIB 10 pF 1.4 V 0-V Differential 1.2-V CM VIA 1V tPLH tPHL VOZ 1.4 V 0-V Differential 1.2-V CM VOY 1V 80% 0-V Differential 20% VOY – VOZ tf tr NOTES: A. RL = 100 Ω or 50 Ω ±1% B. All input pulses are supplied by a generator having the following characteristics: pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. Figure 4. Differential Receiver to Driver Propagation Delay and Driver Transition Time Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN65LVDS22, SN65LVDM22 DUAL MULTIPLEXED LVDS REPEATERS SLLS315– DECEMBER 1998 PARAMETER MEASUREMENT INFORMATION DE 1 V or 1.4 V R 1.2 V RL/2 (see Note A) A D 1.2 V B RL/2 (see Note A) 2V DE 1.4 V 0.8 V tPZH tPHZ ≈ 1.4 V VOY or VOZ 1.25 V 1.2 V tPZL tPLZ 1.2 V 1.15 V VOY or VOZ ≈1 V NOTES: A. RL = 100 Ω or 50 Ω ±1% B. All input pulses are supplied by a generator having the following characteristics: pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. Figure 5. Enable and Disable Timing Circuit 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS22, SN65LVDM22 DUAL MULTIPLEXED LVDS REPEATERS SLLS315– DECEMBER 1998 TYPICAL CHARACTERISTICS SN65LVDS22 SN65LVDS22 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4 VCC = 3.3 V TA = 25°C 3 V OL – Low-Level Output Voltage – V V OH – High-Level Ouptut Voltage – V 3.5 2.5 2 1.5 1 VCC = 3.3 V TA = 25°C 3 2 1 .5 0 0 –4 –3 –2 0 0 –1 IOH – High-Level Output Current – mA 6 Figure 7 Figure 6 SN65LVDM22 SN65LVDM22 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4 3.5 VCC = 3.3 V TA = 25°C 3 V OL – Low-Level Output Voltage – V V OH – High-Level Output Voltage – V 4 2 IOL – Low-Level Output Current – mA 2.5 2 1.5 1 .5 VCC = 3.3 V TA = 25°C 3 2 1 0 0 –8 –6 –4 –2 0 IOH – High-Level Output Current – mA 0 2 4 6 8 10 12 IOL – Low-Level Output Current – mA Figure 9 Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN65LVDS22, SN65LVDM22 DUAL MULTIPLEXED LVDS REPEATERS SLLS315– DECEMBER 1998 APPLICATION INFORMATION The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground differences are less than 1 V with a low common–mode output and balanced interface for very low noise emissions. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/Receivers maintain ECL speeds without the power and dual supply requirements. Transmission Distance – m 1000 30% Jitter 100 5% Jitter 10 1 24 AWG UTP 96 Ω (PVC Dielectric) 0.1 100k 1M 10M Data Rate – Hz Figure 10. Data Transmission Distance Versus Rate 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100M SN65LVDS22, SN65LVDM22 DUAL MULTIPLEXED LVDS REPEATERS SLLS315– DECEMBER 1998 APPLICATION INFORMATION fail safe One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how it handles the open-input circuit situation, however. Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver will pull each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 11. The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the output to a high-level regardless of the differential input voltage. VCC 300 kΩ 300 kΩ A Rt = 100 Ω (Typ) Y B VIT ≈ 2.3 V Figure 11. Open-Circuit Fail Safe of the LVDS Receiver It is only under these conditions that the output of the receiver will be valid with less than a 100 mV differential input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeat the pull-up currents from the receiver and the fail-safe feature. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN65LVDS22, SN65LVDM22 DUAL MULTIPLEXED LVDS REPEATERS SLLS315– DECEMBER 1998 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. 12 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). 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