TI SN74LVC10APW

SN74LVC10A
TRIPLE 3-INPUT POSITIVE-NAND GATE
SCAS284G – JANUARY 1993 – REVISED OCTOBER 1998
D
D
D
D
D
D
D
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Inputs Accept Voltages to 5.5 V
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
D, DB, OR PW PACKAGE
(TOP VIEW)
1A
1B
2A
2B
2C
2Y
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
1C
1Y
3C
3B
3A
3Y
description
This triple 3-input positive-NAND gate is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC10A performs the Boolean function Y = A • B • C or Y = A + B + C in positive logic.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
The SN74LVC10A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
A
B
C
OUTPUT
Y
H
H
H
L
L
X
X
H
X
L
X
H
X
X
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN74LVC10A
TRIPLE 3-INPUT POSITIVE-NAND GATE
SCAS284G – JANUARY 1993 – REVISED OCTOBER 1998
logic symbol†
1A
1B
1C
2A
2B
2C
3A
3B
3C
1
&
2
12
1Y
13
3
4
6
2Y
5
9
10
8
3Y
11
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram, each gate (positive logic)
A
Y
B
C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
2
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SN74LVC10A
TRIPLE 3-INPUT POSITIVE-NAND GATE
SCAS284G – JANUARY 1993 – REVISED OCTOBER 1998
recommended operating conditions (see Note 4)
Operating
VCC
Supply voltage
VIH
High-level input voltage
VIL
Data retention only
Low-level input voltage
VI
VO
MIN
MAX
1.65
3.6
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.65 × VCC
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
2
0.35 × VCC
0.8
0
5.5
V
0
VCC
–4
V
VCC = 1.65 V
VCC = 2.3 V
–8
VCC = 2.7 V
VCC = 3 V
Low level output current
Low-level
V
0.7
Output voltage
IOL
V
1.7
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
High level output current
High-level
V
1.5
Input voltage
IOH
UNIT
mA
–12
–24
VCC = 1.65 V
VCC = 2.3 V
4
VCC = 2.7 V
VCC = 3 V
12
8
mA
24
TA
Operating free-air temperature
–40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
IOH = –100 µA
IOH = –4 mA
VOH
IOH = –8 mA
12 mA
IOH = –12
IOH = –24 mA
IOL = 100 µA
VOL
MIN
TYP†
1.65 V
VCC–0.2
1.2
2.3 V
1.7
2.7 V
2.2
3V
2.4
3V
2.2
MAX
V
1.65 V to 3.6 V
0.2
IOL = 4 mA
IOL = 8 mA
1.65 V
0.45
2.3 V
0.7
IOL = 12 mA
IOL = 24 mA
2.7 V
0.4
3V
0.55
II
ICC
VI = 5.5 V or GND
VI = VCC or GND,
∆ICC
Ci
One input at VCC – 0.6 V,
IO = 0
Other inputs at VCC or GND
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±5
µA
3.6 V
10
µA
500
µA
3.3 V
• DALLAS, TEXAS 75265
V
3.6 V
2.7 V to 3.6 V
VI = VCC or GND
† All typical values are at VCC = 3.3 V, TA = 25°C.
UNIT
5
pF
3
SN74LVC10A
TRIPLE 3-INPUT POSITIVE-NAND GATE
SCAS284G – JANUARY 1993 – REVISED OCTOBER 1998
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
tpd
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
TYP
MIN
MAX
A
Y
13.8
1
7.8
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
UNIT
MAX
MIN
MAX
5.8
1
4.9
ns
1
ns
tsk(o)†
† Skew between any two outputs of the same package switching in the same direction
operating characteristics, TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
4
Power dissipation capacitance per gate
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VCC = 1.8 V
TYP
f = 10 MHz
• DALLAS, TEXAS 75265
9
VCC = 2.5 V
TYP
10
VCC = 3.3 V
TYP
11
UNIT
pF
SN74LVC10A
TRIPLE 3-INPUT POSITIVE-NAND GATE
SCAS284G – JANUARY 1993 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
Open
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
Output
Control
(low-level
enabling)
VCC
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
VOH
VCC/2
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
tPHL
VCC/2
0V
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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SN74LVC10A
TRIPLE 3-INPUT POSITIVE-NAND GATE
SCAS284G – JANUARY 1993 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
6
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SN74LVC10A
TRIPLE 3-INPUT POSITIVE-NAND GATE
SCAS284G – JANUARY 1993 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
GND
CL = 50 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
Open
500 Ω
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
Output
Control
(low-level
enabling)
2.7 V
1.5 V
1.5 V
0V
tPLH
tPHL
VOH
1.5 V
1.5 V
VOL
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
0V
tPZL
2.7 V
Output
1.5 V
1.5 V
tsu
Input
1.5 V
Input
tPLZ
3V
1.5 V
tPZH
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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