APW7093 3A, 1MHz, Step Down DC/DC Regulator General Description Features • • • • Source/Sink 3A The APW7093 is a reversible energy flow, constantoff-time, pulse-width modulated (PWM), step-down DC-DC converter. It is ideal for use in notebook and sub-notebook computers that require 1.1V to 5V active termination power supplies. This device features an internal PMOS power switch and internal synchronous rectifier for high efficiency and reduced Up to 1MHz Switches Frequency Up to 94% Efficiency Internal PMOS/NMOS Switches - 70mΩ/40mΩ On-Resistance at VIN = 4.5V - 90mΩ/60mΩ On-Resistance at VIN = 3V • • • • • • • • • ±1% Output Accuracy component count. The internal 90mΩ PMOS power 1.1V to VIN Adjustable Output Voltage switch and 60mΩ NMOS synchronous-rectifier switch 3V to +5.5V Input Voltage Range easily deliver continuous load currents up to 3A. The APW7093 accurately tracks an external reference voltage, produces an adjustable output from 1.1V to VIN, and achieves efficiencies as high as 94%. <1µA Shutdown Supply Current Programmable Constant-Off-Time Operation Thermal Shutdown The APW 7093 uses a unique current-mode, constant-off-time, PWM control scheme that allows the output to source or sink current. This feature allows energy to return to the input power supply that otherwise would be wasted. The programmable constant-off-time architecture sets switching frequencies up to 1MHz, allowing the user to optimize performance trade-offs between efficiency, output switching noise, component size, and cost. The APW7093 features an adjustable soft-start to limit surge currents during Adjustable Soft-Start Inrush Current Limiting Output Short-Circuit Protection Lead Free Available (RoHS Compliant) Applications • • • • • • • Motherboard Graphics Cards startup, a 100% duty-cycle mode for low-dropout operation, and a low-power shutdown mode that disables Cable or DSL Modems, Set Top Boxes DSP Supplies Memory Supplies the power switches and reduces supply current below 1µA. The APW7093 is available in a 32-pin QFN with 5V Input DC-DC Regulators an exposed backside pad or a 16-pin SSOP. Distributed Power Supplies ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 1 www.anpec.com.tw APW7093 N.C N.C LX N.C LX N.C SHDN 32 N.C Pin Description 25 1 24 N.C PGND IN PGND LX LX LX IN APW7093 SS N.C N.C VCC EXTREF 16 LX 2 15 PGND LX 3 14 IN 4 LX VCC EXTREF 6 11 GND TOFF 7 10 REF FB 8 9 GND SS GND 8 1 IN 13 APW7093 12 5 PGND N.C SHDN PGND N.C REF GND N.C FB N.C TOFF 9 N.C 17 16 SSOP - 16 QFN - 32 Ordering and Marking Information APW7093 Lead Free Code Handling Code Temp. Range Package Code APW7093 N : APW7093 QA : Package Code N : SSOP-16 QA : QFN -32 Operating Ambient Temp. Range I : -45 to 85 °C Handling Code TU : TubeTR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device APW7093 XXXXX XXXXX - Date Code APW7093 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature. Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 2 www.anpec.com.tw APW7093 Block Diagram 0.01 µ F SS V IN VC C V IN +3.0V TO +5.5V FB IN C IN CURRENT SENSE + _ EXTREF PWM LOGIC AND DRIVERS SHDN REF REF LX L CO U T TIMER GND PGND R TOFF Fig1. Block Diagram Absolute Maximum Ratings Parameter Rating Unit -0.3 ~ +6 V IN to VCC ±0.3 V GND to PGND ±0.3 V -0.3 ~ VCC+0.3 V VCC to GND SHDN , SS, FB, T OFF, VREF to GND EXTREF to GND -0.3 ~ VIN-1.7 V 2 1.6 W 2 1 W LX Current -3.5 ~ +4.1 A Operating Temperature Range -40 ~ +85 °C +150 °C -65~+150 °C +300 °C Power dissipation; Part mount on 1in of 1oz copper; QFN-28 Power dissipation; Part mount on 1in of 1oz copper; SSOP-16 Junction Temperature Storage Temperature Range Lead Temperature (soldering,10s) Recommend Operating Condition Recommend Operating Condition Symbol Parameter VIN Input Voltage Range VOUT Output Voltage Range COUT Output Capacitor CIN Input Capacitor L Inductor RTOFF Programmed off-time Resistance Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 MIN TYP 3 1.1 220 22 0.56 330 33 1 – – 3 MAX UNIT 5.5 VIN V V uF uF uH – KΩ NOTE VEXTREF<= VIN-1.7V Low ESR Capacitor Refer to Application section for further Information. www.anpec.com.tw APW7093 Electrical Characteristics (VIN=VCC=3.3V, VEXTREF=+1.1V, TA=-45 to +85oC, unless otherwise noted, Typical values are at TA =+25oC.) Symbol Parameter Test Conditions VIN, VCC Input Voltage ∆VFB Feedback Voltage Accuracy (VFB –VEXTREF) VIN=VCC=+3.0V to +5.5V, ILOAD=0,VEXTREF=1.25V (Note2) Feedback Load Regulation Error ILOAD=-3A to +3A, VEXTREF=+1.25V Min Typ Max 3.0 5.5 V -12 +12 mV 20 1.07 1.10 1.12 8 0 2 V 0.3 2 mV VIN=+4.5V 70 140 VIN=+3.0V 90 180 VIN=+4.5V 50 100 VIN=+3.0V 60 120 4.1 4.7 A 1 MHz IREF= -1µA to +10µA RPMOS PMOS Switch On-Resistance ILX=0.5A RNMOS NMOS Switch On-Resistance ILX=0.5A ILIMIT Current Limit Threshold VIN > VLX fSW Switching Frequency (Note3) No Load Supply Current fSW =500kHz fSW =500kHz 32 Shutdown Supply Current SHDN = GND, ICC+ IIN <1 Thermal Shutdown Threshold Hysteresis =15°C 150 Under Voltage Lockout Threshold VCC falling, hysteresis = 90mV FB Input Current VFB=VEXTREF+0.1V IIN I SHDN UVLO IFB TOFF Off-Time 3.5 1 On-Time °C 2.7 V 0 60 250 nA RTOFF=110kΩ 1.10 1.20 1.30 RTOFF=499kΩ 4.3 4.8 µs µs 0.34 SS Source Current 4 ISS SS Sink Current VSS=1V 2 SHDN Input Current V SHDN =0, VCC -1 VIL 5 6 Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 µA mA +1 0.8 2.0 µs 5.3 4×TOFF IOUT(RMS) Maximum Output RMS Current µA 2.6 ISS VIH 15 0.40 0.44 0.48 SHDN Logic Levels mΩ mA RTOFF=30.1kΩ (Note3) mΩ 2.5 Startup Off-Time TON mV V Reference Voltage VREF 0.01 Reference Load Regulation ICC Unit VIN 1.7 VEXTREF External Reference Voltage Range VIN=VCC=+3.0 to +5.5V VREF APW7093 µA V 3.1 ARMS 4 www.anpec.com.tw APW7093 Electrical Characteristics (Cont.) (VIN=VCC=3.3V, VEXTREF=+1.1V, TA = -45 to +85oC, unless otherwise noted, Typical values are at TA =+25oC.) Symbol Parameter Test Conditions APW7093 Min Typ Max 0.8 VIL VIH SHDN Logic Levels 2.0 IOUT(RMS) Maximum Output RMS Current Unit V 3.1 ARMS Note2: The output voltage will have a DC-regulation level lower than the feedback error comparator threshold by 50% of the ripple. Note3: Recommended operating frequency, not production tested. Functional Pin Description Name PIN (QFN) PIN (QSOP) N.C 1,5,7,9,11,13,16,19, 25,26,28,30,32 X IN 2,4 2,4 LX 3,21,22,27,29 3,14,16 SS 6 5 EXTREF 8 6 TOFF 10 7 FB 12 8 GND 14,17,backside pad, corner tabs 9 Analog Ground. Connect exposed backside pad and corner tabs to analog GND. REF 15 10 Reference Output. Bypass REF to GND with a 0.1µF capacitor. GND 17 11 VCC 18 12 PGND 20,23,24 13,15 SHDN 31 1 Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 FUNCTION No Connection, Not internally connected. Supply Voltage Input for the internal PMOS Power Switch. Not internally connected. Externally connect all pins for proper operation. Inductor Connection. Connection for the drains of the PMOS power switch and NMOS synchronous-rectifier switch. Connect the inductor from this node to the output filter capacitor and load. Not internally connected. Externally connect all pins for proper operation. Soft-Start Connect a capacitor from SS to GND to limit inrush current during startup. External Reference Input Feedback input regulates to VEXTREF. The PWM controller remains off until EXTREF is greater than REF. Off-Time Select Input. Sets the PMOS power switch constant-off-time. Connect a resistor from TOFF to GND to adjust the PMOS switch off-time. Feedback Input. Connect directly to output for fixed-voltage operation or to a resistive-divider for adjustable operating modes. Tie to GND (pin 13 QFN; pin 9 SSOP) Analog Supply Voltage Input. Supplies internal analog circuitry. Bypass VCC with a 10Ω and 1µF low-pass filter. See Figure2. Power Ground. Internally connected to the internal NMOS synchronous-rectifier switch. Shutdown control Input Drive SHDN low to disable the reference, control circuitry, and internal MOSFETs. Drive high or connect to VCC for normal operation. 5 www.anpec.com.tw APW7093 Typical Application APW7093 L V IN 10Ω LX IN 33 µF VOUT 220µF 15mΩ PGND GND VCC 1 µF R2 SHDN FB VEXTREF REF EXTREF 50KΩ SS TOFF 0.1 µF 0.01µF R TOFF FOR VIN =5V: L=1mH, RTOFF=100kW FOR VIN=3.3V: L=0.68mH, RTOFF=68kW Fig2. Typical Applicatin Circuit Typical Characteristics (Circuit of Figure2, VOUT=1.25V, for VIN=3.3V: L: 0.68µH, RTOFF=68kΩ; for VIN=5V: L=1µH, TOFF=100kΩ. TA=25C if not specially) Effienciency vs. Output Current No Load Supply Current vs. Input Voltage 100 50 No Load Supply Current(mA) VIN=5V, VOUT=3.3V 95 90 Efficiency(%) 85 80 75 VIN=5V, VOUT=1.25V 70 65 VIN=5V, VOUT=2.5V 60 VIN=3.3V, VOUT=1.25V 55 50 45 40 30 VOUT=1.25V RTOFF=68kΩ 20 10 0 40 0 1 2 0 3 Output Current(A) Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 1 2 3 4 5 6 Input Voltage(V) 6 www.anpec.com.tw APW7093 Typical Characteristics (Cont.) (Circuit of Figure2, VOUT=1.25V, for VIN=3.3V: L: 0.68µH, RTOFF=68kΩ; for VIN=5V: L=1µH, TOFF=100kΩ. TA=25C if not specially) OFF-TIME vs. RTOFF Switching Frequency vs. Output Current 6 800 5 700 VIN=3.3V OFF-TIME(µs) Switching Frequency(kHz) 900 600 500 400 VIN =5V 300 4 3 2 200 1 100 0 0 0 1 2 3 0 100 200 300 400 500 600 RTOFF(kΩ) Output Current(A) Start Up and Shut Down VREF vs. Input Voltage 1.114 SHDN=2V/DIV VREF(V) 1.113 1.112 VSS=2V/DIV 1.111 IN=1A/DIV 1.110 3.0 3.5 4.0 4.5 5.0 TIME 2ms/DIV 5.5 VIN=3.3V, VOUT=1.25V, ROUT=0.4Ω Input Voltage(V) Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 7 www.anpec.com.tw APW7093 Typical Characteristics (Cont.) (Circuit of Figure2, VOUT=1.25V, for VIN=3.3V: L= 0.68µH, RTOFF=68kΩ; for VIN=5V: L=1µH, TOFF=100kΩ. TA=25°C if not specially) Load Transient Response Load Transient Response IOUT=3A IOUT= 3A IOUT=3A IOUT =0A 0A IOUT= IOUT=0A VOUT 100mV/DIV VOUT 100mV/DIV TIME 20µs/DIV TIME 20µs/DIV TIME 20us/DIV di VIN=5V, VOUT=1.25V, dt VOUT 100mV/DIV = di 3A VIN=5V, VOUT=2.5V, µs Load Transient Response dt = 3A µs Line Transient Response IOUT=3A VIN=5.0V IOUT=0A VIN=3.0V VOUT 100mV/DIV VOUT 100mV/DIV TIME 20µs/DIV VIN=3.3V, VOUT=1.25V, di dt TIME 40µs/DIV = 3A µs Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 8 www.anpec.com.tw APW7093 Typical Characteristics (Cont.) (Circuit of Figure2, VOUT=1.25V, for VIN=3.3V: L= 0.68µH, RTOFF=68kΩ; for VIN=5V: L=1µH, TOFF=100kΩ. TA=25°C if not specially) Light Load Waveform Heavy Load Waveform VLX 5V/DIV VLX 5V/DIV ILX 1A/DIV ILX 1A/DIV VOUT 50mV/DIV VOUT 50mV/DIV TIME 1µs/DIV TIME 1µs/DIV IOUT=100mA IOUT=3A VREF vs. Temperature Output Voltage vs. Temperature 1.255 1.118 1.116 1.114 1.253 VIN=3.3V 1.110 VOUT(V) VREF(V) 1.112 1.108 1.106 1.251 VIN=3.3V IOUT=0A 1.249 1.104 1.247 1.102 1.100 1.245 1.098 -50 -25 0 25 50 75 100 -50 125 Temperature(°C) Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 -25 0 25 50 75 100 125 Temperature(°C) 9 www.anpec.com.tw APW7093 Function Descriptions path for current to flow when the inductor is discharging. Replacing the Schottky diode with a low-resistance NMOS synchronous switch reduces conduction losses and improves efficiency. The NMOS synchronous-rectifier switch turns on following a short delay (typ. 20ns) after the PMOS power switch turns off, thus preventing cross-conduction or “shoot-through.” In constant-offtime mode, the synchronous-rectifier switch turns off just prior to the PMOS power switch turning on. While both switches are off, inductor current flows through the internal body diode of the NMOS switch. The APW7093 synchronous, current-mode, constant off-time, PW M DC-DC converter steps down input voltages of 3V to 5.5V to an adjustable output voltage from 1.1V to V IN, as set by the voltage applied at EXTREF. It sources and sinks up to 3A of output current. Internal switches composed of a 90mΩPMOS power switch and a 60m Ω NMOS synchronous-rectifier switch improve efficiency, reduce component count, and eliminate the need for an external Schottky diode across the synchronous switch. The APW7093 operates in a constant-off-time mode under all loads. A single resistor-programmable constant- tradeoffs in efficiency, switching noise, component size, and cost. When power is drawn from a regulated supply, constant-off-time PWM architecture essentially provides constant-frequency operation. This architecture has the inherent advantage of quick response to line and load transients. The APW7093’s current-mode, constant-off-time PWM architecture regulates the output voltage by changing the PMOS switch on-time relative to the constant off-time. Current Sourcing and Sinking By operating in a constant-off-time, pseudo-fixedfrequency mode, the APW7093 can both source and sink current. Depending on the output current requirement, the circuit operates in two modes. In the first mode the output draws current and the APW7093 behaves as a regular buck controller, sourcing current to the output from the input supply rail. However, when the output is supplied by another source, the APW7093 operates in a second mode as a synchronous boost, taking power from the output and returning it to the input. Constant-Off-Time Operation In the constant-off-time architecture, the FB voltage comparator turns the PMOS switch on at the end of each off-time, keeping the device in continuous- Thermal Resistance Junction-to-ambient thermal resistance, θ JA, is highly dependent on the amount of copper area immediately conduction mode. The PMOS switch remains on until the feedback voltage exceeds the external reference voltage (VEXTREF) or the positive current limit is reached. surrounding the IC leads. The APW7093 QFN package has 1in square of copper area and a thermal resistance of 50°C/W with no forced airflow. The APW 7093 16-pin SSOP evaluation kit has 0.5 in square of copper area and a thermal resistance of 80°C/ When the PMOS switch turns off, it remains off for the programmed off-time (TOFF ). To control the current under short-circuit conditions, the PMOS switch remains off for approximately 4 x TOFF when V FB < VEXTREF / 4. W with no forced airflow. Airflow over the board significantly reduces the junction-to-ambient thermal resistance. For heat sinking purposes, it is essential to connect the exposed backside pad of the QFN package to a large analog ground plane. Synchronous Rectification In a step-down regulator without synchronous rectification, an external Schottky diode provides a Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 10 www.anpec.com.tw APW7093 Function Descriptions(Cont.) Shutdown 2 PD(CAP) = C × VIN × fSW Drive SHDN to a logic-level low to place the APW7093 in low-power shutdown mode and reduce supply current less than 1µA. In shutdown, all circuitry and internal MOSFETs turn off, so the LX node becomes where C = 500pF and fSW is the switching frequency. Resistive losses in the two power switches are approximated by: 2 PD(RES) = IOUT × R PMOS high impedance. Drive SHDN to a logic-level high or connect to VCC for normal operation. where RPMOS is the on-resistance of the PMOS switch. The junction-to-ambient thermal resistance required to dissipate this amount of power is calculated by: Power Dissipation θJA = (TJ,MAX - TA,MAX) / (PD(CAP) + PD(RES)) where: θ JA = junction-to-ambient thermal resistance TJ,MAX = maximum junction temperature Power dissipation in the APW7093 is dominated by conduction losses in the two internal power switches. Power dissipation due to charging and discharging the gate capacitance of the internal switches (i.e., switching losses) is approximately: TA,MAX = maximum ambient temperature Application Information For typical applications, use the recommended component values in Figure 2. For other applications, take the following steps: 1. Select the desired PWM-mode switching frequency. See Figure 3 for maximum operating frequency. 2. Select the constant off-time as a function of input voltage, output voltage, and switching frequency. Setting the Output Voltage An external voltage applied to the EXTREF pin sets the output voltage of the APW7093. This can come directly from another voltage source or external reference. When FB is directly tied to the output (Figure 4), the output voltage range is limited by the external reference’s input voltage limits. V EXTREF should be limited to less than VIN-1.7V. Failure to comply can cause the part to operate abnormally and may cause part damage. Alternatively, the output can be adjusted up to VIN by connecting FB to a resistordivider between the output voltage and ground (Figure 3. Select RTOFF as a function of off-time. 4. Select the inductor as a function of output voltage, off-time, and peak-to-peak inductor current. Operation Frequency(KHz) 1400 VOUT=2.5V 1200 VOUT=3.3V 1000 5). Use 50k Ω for R1. R2 is given by: 800 R2 = R1 ⋅ VOUT − 1 V EXTREF 600 VOUT=1.1V 400 VOUT=1.25V 200 0 2.8 3.3 3.8 4.3 4.8 5.3 Input Voltage(V) Fig 3. Maximum Recommended Operation Frequency Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 11 www.anpec.com.tw APW7093 Application Information(Cont.) Setting the Output Voltage (Cont.) TOFF = (VIN − VOUT − VPMOS ) fSW (VIN − VPMOS + VNMOS ) V OUT =V EXTREF where: TOFF = the programmed off-time VIN = the input voltage VOUT = the output voltage VPMOS = the voltage drop across the internal PMOS LX APW7093 power switch |IOUT X RPMOS| V EXTREF EXTREF FB VNMOS = the voltage drop across the internal NMOS synchronous-rectifier switch |IOUT X RNMOS| fSW = switching frequency Make sure that TON and TOFF are greater than 400ns when sourcing current. Select RTOFF according to the formula: 1.1V ≤ VEXTREF ≤ VIN − 1.7V FIG.4 Adjsting the Output Voltage using EXTREF V OUT R TOFF = (TOFF − 0.18 µ s) × (109k Ω /1.00 µ s ) LX Recommended values for RTOFF range from 24k Ω to APW7093 410k Ω for off-times of 0.4µs to 4µs. Often the switching R2 frequency is set as high as possible, and the inductor value is reduced to minimize the energy transferred from inductor to capacitor during load-step recovery. The operating frequency of the APW7093 is determined primarily by TOFF (set by RTOFF), V IN, and V OUT as shown in the following formula: FB REF EXTREF R1 − 1 VEXTREF R 2 = R1 ⋅ V OUT fSW = where V EXTREF = V REF = 1.1V However, as the output current increases, the voltage drop across the NMOS and PMOS switches increases and the voltage across the inductor decreases. This causes the frequency to drop. Assuming RPMOS = FIG.5 Adjsting the Output Voltage using FB Programming the Switching Frequency and Off-Time and On-Time RNMOS, the change in frequency can be approximated with the following formula: The APW7093 features a programmable PWM-mode switching frequency, which is set by the input and output voltage and the value of RTOFF, connected from TOFF to GND. RTOFF sets the PMOS power switch off-time in PWM mode. Use the following equation to ∆fSW = Copyright ANPEC Electronics Corp. − ∆IOUT × RPMOS VIN × TOFF where R PMOS is the resistance of the internal MOSFETs (70m Ω typ). select the off-time while sourcing current according to the desired switching frequency in PWM mode: Rev. A.5 - Jun., 2005 (VIN − VOUT − VPMOS ) TOFF (VIN − VPMOS + VNMOS ) 12 www.anpec.com.tw APW7093 Application Information(Cont.) Programming the Switching Frequency and Off-Time and On-Time (Cont.) Low-ESR and low-ESL Tantalum or ceramic capacitor should be suitable. W hen sinking current, the switching frequency increases due to the on-resistances of the internal switches adding to the voltage across the inductor, reducing the on-time. Calculate TON when sinking current using the equation: TON = TOFF VOUT − VNMOS VIN − VOUT + VPMOS Output Capacitor Selection The output filter capacitor affects the output voltage ripple, output load-transient response, and feedback loop stability. The output filter capacitor must have low enough ESR to meet output ripple and load transient requirements, yet have high enough ESR to satisfy stability requirements. Also, the capacitance value must be high enough to guarantee stability and absorb the inductor energy going from a full-load sourcing to full load sinking condition without exceeding the maximum output tolerance. Inductor Selection The key inductor parameters must be specified: inductor value (L) and peak current (IPEAK). A lower value of inductor allows smaller size but results in higher losses and ripple. A good compromise between size and losses is found at approximately a 25% ripple current In applications where the output is subject to large load transients, the output capacitor’s size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. to load current ratio (∆I/I OUT = 0.25). L= VOUT × TOFF IOUT × 0.25 R ESR ≤ ∆ VOUT / ∆ I OUT(MAX) The peak inductor current at full load is calculated by: IPEAK = IOUT + The actual microfarad capacitance value required is defined by the physical size needed to achieve low ESR, and by the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR, size and voltage rating rather than by capacitance value. VOUT × TOFF 2×L where IOUT is the maximum source or sink current. W hen using low-capacity filter capacitors such as ceramic or polymer types, capacitor size is usually determined by the capacity needed to prevent overshoot Choose an inductor with a saturation current at least as high as the peak inductor current. Additionally, verify the peak inductor current while sourcing output current (IOUT = ISOURCE) does not exceed the positive current limit. The inductor selected should exhibit low and undershoot from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising-load edge is no longer a problem. losses at the chosen operating frequency. Input Capacitor Selection The input filter capacitor reduces peak currents and noise at the voltage source. A 22µF to 47µF capacitor may be required for higher power and dynamic loads. Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 13 www.anpec.com.tw APW7093 Application Information(Cont.) Soft-Start Input Source Soft-start allows a gradual increase of the internal current limit to reduce input surge currents at startup and at exit from shutdown. A timing capacitor, CSS, The output of the APW7093 can accept current due to the reversible properties of the buck and the boost converter. When voltage at the output of the APW7093 (low-voltage port) exceeds or equals the output set voltage the flow of energy reverses, going from the output to the input (high-voltage port). If the input (high voltage port) is not connected to a low-impedance source capable of absorbing energy, the voltage at the input will rise. This voltage can violate the absolute maximum voltage at the input of the APW7093 and destroy the part. This occurs when sinking current because the topology acts as a boost converter, pumping energy from the low-voltage side (the output), to the high-voltage side (the input). The input (highvoltage side) voltage is limited only by the clamping effect of the voltage source connected there. To avoid this problem, make sure the input to the APW7093 is connected to a low impedance, two quadrant supply or that the load (excluding the APW7093) connected to that supply consumes more power than the amount being transferred from the APW7093 output to the placed from SS to GND sets the rate at which the internal current limit is changed. Upon power-up, when the device comes out of under-voltage lockout (2.6V typ.) or after the SHDN pin is pulled high, a 4.7µA constant current source charges the soft-start capacitor and the voltage on SS increases. When the voltage on SS is less than approximately 0.7V, the current limit is set to zero. As the voltage increases from 0.7V to approximately VIN, the current limit is adjusted from 0V to the current-limit threshold. The voltage across the soft-start capacitor changes with time according to the equation: VSS = 4.7 µA × t C SS The output current limit during soft-start varies with the voltage on the soft-start pin, SS, according to the equation: ILIIM(SS)= (VSS − 0.7V) ×ILIMIT , VSS ≤ 1.8V 1.1V input. Current Limit and Short Circuit Protection where ILIMIT is the current-limit threshold from the Electrical Characteristics. The constant-current source stops charging once the voltage across the soft-start capacitor reaches 1.8V. The APW7093 monitors sourcing and sinking current, and limits the maximum output current to prevent damages during overload or short-circuit. Circuit Layout and Grounding SHDN Good layout is necessary to achieve the APW7093’s intended output power level, high efficiency, and low noise. Good layout includes the use of ground planes, careful component placement, and correct routing of traces using appropriate trace widths. The following points are in order of decreasing importance: 0 V IN V SS(A) 1.8V 0.7V 0 I LIMIT I LIMIT (A) 0 t Fig6. Soft-Start Current Limit Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 14 www.anpec.com.tw APW7093 Application Information(Cont.) Circuit Layout and Grounding (Cont.) 1. Minimize switched-current and high-current ground loops. Connect the input capacitor’s ground, the output capacitor’s ground, and P GND close together. Split the ground connections. Use separate traces or planes for the PGND and GND and tie them together at a single point. 2. The output capacitor should be placed close to the output terminals to obtain better smoothing effect on the output ripple. 3. Connect the input filter capacitor less than 5mm away from IN. The connecting copper trace carries large currents and must be at least 1mm wide, preferably 2.5mm. 4.Place the LX node components as close together and as near to the device as possible. This reduces resistive and switching losses as well as noise. 5.G round planes are e ssent ial f o r opti m um performance. In most applications, the circuit is located on a multilayer board and full use of the four or m ore layers is recom m ended. For heat dissipation, connect the exposed backside pad of the QFN package to a large analog ground plane, preferably on a surface of the board that receives good airflow. If the ground plane is located on the top layer, make use of the N.C. pins adjacent to GND to lower thermal resistance to the ground plane. If the ground is located elsewhere, use several vias to lower thermal resistance. Typical applications use multiple ground planes to m inim ize therm al resistance. Avoid large AC currents through the analog ground plane. Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 15 www.anpec.com.tw APW7093 Packaging Information SSOP-16 S D N H GAUGE PLANE E 1 2 3 A 1 A1 B e L Millimeters Inches Dim Min. Max. Min. Max. A 1.350 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 B 0.20 0.30 0.008 0.012 D 4.75 5.05 0.187 0.199 E 3.75 4.05 0.147 0.160 e 0.625 TYP. 0.025 TYP. H 5.75 6.25 0.226 0.246 L 0.4 1.27 0.016 0.050 S 0.05 0.18 0.002 0.007 φ1 0° 8° 0° 8° Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 16 www.anpec.com.tw APW7093 Packaging Information QFN-32 D 32 31 30 29 28 27 26 D2 25 1 24 2 L 31 32 1 23 2 3 22 4 21 E E2 5 20 6 19 7 18 8 17 9 10 11 12 13 14 15 16 e b A A3 A1 Dim Millimeters Inches Min. Max. Min. Max. A - 0.84 - 0.033 A1 0.00 0.04 0.00 0.0015 A3 0.20 REF. 0.008 REF. D 4.90 5.10 0.192 0.200 E 4.90 5.10 0.192 0.200 b 0.18 0.28 0.007 0.011 D2 3.50 3.60 0.138 0.142 E2 3.50 3.60 0.138 0.142 0.500 BSC e L 0.35 Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 0.020 BSC 0.45 0.014 17 0.018 www.anpec.com.tw APW7093 Physical Specifications Terminal Material Lead Solderability Packaging Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. 2500 devices per reel Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone T L to T P Temperature Ramp-up TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25 °C to Peak Time Classificatin Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (T L) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 18 www.anpec.com.tw APW7093 Classificatin Reflow Profiles(Cont.) Table 1. SnPb Entectic Process – Package Peak Reflow Temperature s Package Thickness Volume mm 3 Volume mm 3 <350 ≥350 <2.5 mm 240 +0/-5°C 225 +0/-5°C ≥2.5 mm 225 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0°C* 260 +0°C* 260 +0°C* 1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Reliability test program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C , 5 SEC 1000 Hrs Bias @ 125 °C 168 Hrs, 100 % RH , 121°C -65°C ~ 150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms , Itr > 100mA Carrier Tape & Reel Dimension t E D P Po P1 Bo F W Ao Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 D1 19 Ko www.anpec.com.tw APW7093 Carrier Tape & Reel Dimension T2 J C A B T1 Application SSOP-16 A B D0 6.95 5.4 T T2 W 0.3±0.05 2.2 12.0±0.3 D1 E F P0 P1 P2 1.75±0.1 5.5±0.05 4.0±0.1 8.0±0.1 2.0±0.05 W1 C1 C2 T1 T2 C 9.5 13±0.3 21±0.8 13.5±0.5 2.0±0.2 80±1 1.55±0.05 1.55±0.1 (mm) Cover Tape Dimensions Application SSOP- 16 Carrier Width 16.8 Cover Tape Width 12.3 Devices Per Reel 2500 Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 20 www.anpec.com.tw