APW7199 High-Performance Step-Down PWM Controller with PFM Features General Description • The APW7199 is a single-phase, constant-on-time, and synchronous PWM controller, which drives N-channel Operates from An Input Battery Voltage Range of +3V to +25V • MOSFETs. An internal 0.5V temperature-compensated reference voltage with high accuracy is designed to meet ±0.6% 0.5V Reference - Over Line, Load Regulation, and Operating Temp. • the requirement of low output voltage applications. The APW7199 steps down high voltage to generate low-volt- Drive Dual Low Cost N-Channel MOSFETs age chipset or RAM supplies in notebook computers. The PWM controller operates fixed 300kHz pseudo-con- - Adaptive Shoot-Through Protection • Power-On-Reset Monitoring on VCC Pin • PFM Mode for Increasing Light Load Efficiency • Constant-On-Time Control Scheme stant frequency PWM with an adaptive constant-on-time control. The device provides excellent transient response and accurate DC voltage output in either PFM or PWM Mode. In Pulse Frequency Mode (PFM), the APW7199 pro- - Switching Frequency Compensation for PWM vides very high efficiency over light to heavy loads with loading-modulated switching frequencies. The device Operation • 300kHz Constant Switching Frequency works in ultrasonic mode with PFM at no load. The unique ultrasonic mode maintains the switching frequency above • Integrated MOSFET Drivers and Bootstrap Diode 20kHz, which eliminates noise in audio applications. • Internal Soft-Start and Soft-Stop The APW7199 is equipped with accurate over-current, • Power Good Monitoring • 70% Under-Voltage Protection • 125% Over-Voltage Protection output under-voltage, and output over-voltage protections. A Power-On-Reset function monitors the voltage on VCC to prevent wrong operation during power-on. The APW7199 has a 1.5ms digital soft-start to ramp up the output voltage to reduce the start-up current. A soft-stop - Using Low-Side MOSFET’s RDS(ON) • Over-Temperature Protection function actively discharges the output capacitors with controlled reverse inductor current. • TDFN-10 3mmx3mm Package The APW7199 is available in TDFN3x3-10 package. • Lead Free and Green Devices Available Simplified Application Circuit (RoHS Compliant) 5V Applications • BOOT Low Cost PC • Wide Input DC/DC Regulators VCC UGATE Notebook • VIN Q1 LOUT EN/EXTREF PHASE LGATE/OCSET POK Q2 VOUT COUT ROCSET APW7199 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 1 www.anpec.com.tw APW7199 Ordering and Marking Information Package Code QB : TDFN3x3-10 Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW7199 Assembly Material Handling Code Temperature Range Package Code APW 7199 XXXXX APW7199 QB : XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Pin Configuration BOOT 1 UGATE 2 PHASE 3 GND 4 LGATE/OCSET 5 10 EN/EXTREF 9 POK 8 VOUT 7 FB 6 VCC TDFN3x3-10 (Top View) = Thermal Pad (connected to GND plane for better heat dissipation) Absolute Maximum Ratings Symbol VCC VBOOT-GND VBOOT (Note 1) Parameter Rating VCC Supply Voltage (VCC to GND) -0.3 ~ 7 V BOOT Supply Voltage (BOOT to GND ) -0.3 ~ 32 V BOOT Supply Voltage (BOOT to PHASE) -0.3 ~ 7 V All Other Pins (FB, VOUT, POK, and EN/EXTREF to GND) VPHASE TJ TSTG TSDR Unit -0.3 ~ VCC+0.3 V UGATE Voltage (UGATE to PHASE) <400ns Pulse Width >400ns Pulse Width -5 ~ VBOOT+0.3 -0.3 ~ VBOOT+0.3 V LGATE/OCSET Voltage (LGATE to GND) <400ns Pulse Width >400ns Pulse Width -5 ~ VCC+0.3 -0.3 ~ VCC+0.3 V PHASE Voltage (PHASE to GND) <400ns Pulse Width >400ns Pulse Width -5 ~ 32 -1 ~ 25 V Maximum Junction Temperature Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds 150 o -65 ~ 150 o 260 o C C C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 2 www.anpec.com.tw APW7199 Thermal Characteristics Symbol θJA Parameter Thermal Resistance -Junction to Ambient Typical Value Unit 55 °C/W (Note 2) TDFN3x3-10 Note 2: θJA is measured with the component mounted on a high effective the thermal conductivity test board in free air. The exposed pad of package is soldered directly on the PCB. Recommended Operating Conditions (Note 3) Symbol Parameter VIN Converter Input Voltage Range Unit 3 ~ 25 V VCC VCC Supply Voltage 4.5 ~ 5.5 V VOUT Converter Output Voltage 0.5 ~ 3.3 V IOUT Converter Output Current 0 ~ 25 TA TJ Ambient Temperature Junction Temperature A -40 ~ 85 o -40 ~ 125 o C C Note 3 : Refer to the typical application circuit. Electrical Characteristics Refer to the typical application circuits. These specifications apply over VCC = 5V, and TA = -40 ~ 85°C, unless otherwise specified. Typical values are at TA = 25°C. Symbol Parameter APW7199 Test Conditions Unit Min. Typ. Max. - 400 500 µA SUPPLY CURRENT IVCC-PWM VCC Input Bias Current UGATE and LGATE Open IVCC-PFM VCC Input Bias Current UGATE and LGATE Open - 350 450 µA IVCC_SHDN VCC Shutdown Current VEN/EXTREF = 0V - - 7 µA REFERENCE VOLTAGE VREF IFB Reference Voltage - 0.5 - V Regulation Accuracy TA = -40oC ~ 85oC, IOUT = 0 ~ 20A -0.6 - +0.6 % Line and Load Regulation 0A < IOUT < 20A; 4V < VCC < 5.5V -0.2 - +0.2 % FB Input Bias Current VFB = 0.5V -0.5 - 0.5 µA - 100 - ns PWM CONTROLLER TON(MIN) Minimum On Time of UGATE Over-Temperature and VCC TOFF(MIN) Minimum Off Time of UGATE Over-Temperature and VCC TSS - 300 - ns Internal Soft-Start Time 1 1.5 2 ms VOUT Pin Input Impedance - 130 - kΩ VOUT Discharge Resistance - 20 32 Ω Zero Crossing Voltage Threshold -3 0 +3 mV PWM to PFM Debounce Time - 20 - µs PFM to PWM Debounce Time - 20 - µs Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 3 www.anpec.com.tw APW7199 Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VCC = 5V, and TA = -40 ~ 85°C, unless otherwise specified. Typical values are at TA = 25°C. Symbol Parameter APW7199 Test Conditions Unit Min. Typ. Max. GATE DRIVER UGATE Source Resistance VBOOT = 5V, VBOOT - VUGATE = 0.5V - 1.5 3 Ω UGATE Sink Resistance VBOOT = 5V, VUGATE - VPHASE = 0.5V - 1 2 Ω LGATE Source Resistance VCC = 5V, VCC - VLGATE = 0.5V - 1.5 3 Ω LGATE Sink Resistance VCC = 5V, VLGATE - VGND = 0.5V - 0.8 1.5 Ω Dead Time (Note 4) 20 25 40 ns BOOTSTRAP DIODE VF Forward Voltage VCC - VBOOT-GND, IF = 5mA - 0.8 1 V IR Reverse Leakage VBOOT-GND = 30V, VPHASE = 25V, VCC = 5V - - 0.5 µA Rising VCC POR Threshold Voltage 4.05 4.2 4.35 V VCC POR Hysteresis 0.1 0.2 0.3 V VCC POWER-ON-RESET (POR) THRESHOLD VVCC_THR OSCILLATOR FSW Switching Frequency in PWM Mode DC Output Current, VCC = 4.5V ~ 5.5V 270 300 330 kHz Minimum Ultrasonic Operating Frequency VCC = 4.5V ~ 5.5V 20 25 - kHz CONTROL INPUTS PWM Converter Shutdown Threshold VEN/EXTREF Falling - - 0.4 V External Reference Voltage Input Range VREF = VEN/EXTREF 0.5 - 2.5 V Internal Reference Enable Threshold VREF = 0.5V (typical), VEN/EXTREF Rising 2.75 - - V EN/EXTREF Leakage Current VEN/EXTREF = 0V -0.1 - 0.1 µA Maximum Voltage Slew Rate of VREF External reference voltage used, VREF = VEN/EXTREF 8 - - mV/µs VFB is from low to target value (POK Goes High) 91 95 99 % ~3µs noise filter, VFB Falling (POK Goes Low) 65 70 75 % ~3µs noise filter, VFB Rising (POK Goes Low) 120 125 130 % POWER OK INDICATOR (POK) VPOK POK Threshold IPOK POK Leakage Current VPOK = 5V - 0.1 1.0 µA VPOK POK Output Low Voltage IPOK = -4mA - 0.5 1 V IOCSET Sourcing 9 10 11 µA 230 250 270 mV PROTECTIONS IOCSET VOCP_MAX IOCSET Source Current Built-in Maximum OCP Voltage Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 4 www.anpec.com.tw APW7199 Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VCC = 5V, and TA = -40 ~ 85°C, unless otherwise specified. Typical values are at TA = 25°C. Symbol Parameter Test Conditions APW7199 Unit Min. Typ. Max. Under-Voltage Protection Threshold 65 70 75 % Under-Voltage Protection Debounce Interval - 2 - µs Over-Voltage Protection Rising Threshold 120 125 133 % Over-Voltage Protection Falling Threshold 100 105 110 % Over-Voltage Protection Debounce Interval - 2 - µs Over-Temperature Protection Rising Threshold (Note 4) - 150 - o Over-Temperature Protection Hysteresis (Note 4) - 20 - o PROTECTIONS (CONT.) VUV VOVR TOTR C C Note4: Guaranteed by design. Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 5 www.anpec.com.tw APW7199 Typical Operating Characteristics OCSET Sourcing Current vs. Junction Temperature 10.4 0.506 OCSET Sourcing Current, IOCSET (µA) Reference Voltage Accuracy, VREF (V) Reference Voltage Accuracy vs. Junction Temperature 0.504 0.502 0.500 0.498 0.496 10.2 10 9.8 9.6 -50 -30 -10 10 30 50 70 90 110 130 Junction Temperature, TJ (oC) 0.494 -50 -30 -10 10 30 50 70 90 110 130 Junction Temperature, TJ (oC) Switching Frequency vs. Converter Input Voltage Switching Frequency vs. Converter Output Current 300 330 VIN=19V, VOUT=1.05V Switching Frequency, FSW (kHz) Switching Frequency, FSW (kHz) 350 250 200 150 100 50 0 0.01 0.10 1.00 10.00 310 300 290 280 270 100.00 3 5 7 9 11 13 15 17 19 21 23 25 Converter Output Current, IOUT (A) Converter Input Voltage, VIN (V) Efficiency vs. Load Current , VOUT=1.05V Converter Output Voltage vs. Converter Input Voltage 100 Converter Output Voltage, VOUT (V) 1.060 90 80 Efficiency (%) IOUT=4A PWM MODE 320 70 60 50 40 30 20 10 0 0.01 VIN=8V VIN=19V H-Side:APM4826 x1 L-Side:APM4828 x1 Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 1.056 1.054 1.052 1.050 1.048 1.046 1.044 1.042 1.040 0.10 10.00 1.00 100.00 Converter Output Current, IOUT (A) 6 VCC=5V, VOUT=1.05V, ILOAD=0A 1.058 0 5 10 15 20 Converter Input Voltage, VIN (V) 25 www.anpec.com.tw APW7199 Typical Operating Characteristics (Cont.) Converter Output Voltage vs. Converter Output Current Converter Output Voltage, VOUT (V) 1.060 VIN=19V, VOUT=1.05V, PWM MODE 1.058 1.056 1.054 1.052 1.050 1.048 1.046 1.044 1.042 1.040 0 5 10 15 20 Converter Output Current, IOUT (A) Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 7 www.anpec.com.tw APW7199 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=19V, TA=25oC unless otherwise specified. Enable at Zero Initial Voltage of VOUT Enable Before End of Soft-Stop V E N /E X TREF VE N /E X TRE F 1 1 VOUT 2 2 VPHASE VP H A S E 3 4 VOUT 3 V POK VPOK 4 CH1: VEN/EXTREF, 5V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPHASE, 20V/Div, DC CH4: VPOK, 5V/Div, DC TIME: 5ms/Div CH1: VEN/EXTREF, 5V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPHASE, 20V/Div, DC CH4: VPOK, 5V/Div, DC TIME: 1ms/Div Shutdown at IOUT=20A Shutdown with Soft-Stop at No Load V E N /E X TRE F VE N /E X TRE F 1 1 V OUT VOUT 2 2 VPHASE VP H A S E 3 3 V POK VPOK 4 4 CH1: VEN/EXTREF, 5V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPHASE, 20V/Div, DC CH4: VPOK, 5V/Div, DC TIME: 10µs/Div Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 CH1: VEN/EXTREF, 5V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPHASE, 20V/Div, DC CH4: VPOK, 5V/Div, DC TIME: 20ms/Div 8 www.anpec.com.tw APW7199 Operating Waveforms (Cont.) Refer to the typical application circuit. The test condition is VIN=19V, TA=25oC unless otherwise specified. Load Transient 0A->10A Load Transient 10A->0A VP H A S E VP H A S E 1 1 VLGA TE VLGATE 2 2 VOUT VOUT 3 3 IOUT IOUT 4 4 CH1: VPHASE, 20V/Div, DC CH2: VLGATE, 5V/Div, DC CH3: VOUT, 50mV/Div, AC CH4: IOUT, 10A/Div, DC TIME: 10µs/Div CH1: VPHASE, 20V/Div, DC CH2: VLGATE, 5V/Div, DC CH3: VOUT, 50mV/Div, AC CH4: IOUT, 10A/Div, DC TIME: 10µs/Div Short Circuit Test Current-Limit and UV Protections VP H A S E VP H A S E 1 1 V LGATE VLGATE 2 2 VOUT VOUT 3 3 IL IL 4 4 CH1: VPHASE, 20V/Div, DC CH2: VLGATE, 5V/Div, DC CH3: VOUT, 1V/Div, DC CH4: IL, 10A/Div, DC TIME: 20µs/Div CH1: VPHASE, 20V/Div, DC CH2: VLGATE, 5V/Div, DC CH3: VOUT, 1V/Div, DC CH4: IL, 10A/Div, DC TIME: 20µs/Div Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 9 www.anpec.com.tw APW7199 Operating Waveforms (Cont.) Refer to the typical application circuit. The test condition is VIN=19V, TA=25oC unless otherwise specified. Operating at PFM Mode Operating at ULTRASONIC Mode VP H A S E VP H A S E 1 1 VLGATE V LGA TE 2 2 3 VOUT 3 VOUT IL 4 4 IL CH1: VPHASE, 10V/Div, DC CH2: VLGATE, 5V/Div, DC CH3: VOUT, 50mV/Div, AC CH4: IL, 5A/Div, DC TIME: 10µs/Div CH1: VPHASE, 10V/Div, DC CH2: VLGATE, 5V/Div, DC CH3: VOUT, 50mV/Div, AC CH4: IL, 5A/Div, DC TIME: 2µs/Div Operating at PWM Mode VPHASE 1 VLGATE 2 V OUT 3 4 IL CH1: VPHASE, 10V/Div, DC CH2: VLGATE, 5V/Div, DC CH3: VOUT, 50mV/Div, AC CH4: IL, 5A/Div, DC TIME: 2µs/Div Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 10 www.anpec.com.tw APW7199 Pin Description PIN FUNCTION NO. NAME 1 BOOT This pin provides ground referenced bias voltage to the high-side MOSFET driver. A bootstrap circuit with a diode connected to 5V is used to create a voltage suitable to drive a logic-level N-channel MOSFET. 2 UGATE Connect this pin to the high-side N-channel MOSFET’s gate. This pin provides gate drive for the high-side MOSFET. 3 PHASE The pin provides return path for the high-side MOSFET driver’s pull-low current. Connect this pin to the high-side MOSFET’s source. 4 GND The GND terminal provides return path for the IC’s bias current and the low-side MOSFET driver’s pull-low current. Connect the pin to the system ground via very low impedance layout on PCBs. 5 LGATE/OCSET 6 VCC 7 FB 8 VOUT 9 POK 10 EN/EXTREF Low-side Gate Driver Output and Over-Current Setting Input. This pin is the gate driver for low-side MOSFET. Connect this pin to a 5V supply voltage. This pin provides bias supply for the control circuitry and the low-side MOSFET driver. The voltage at this pin is monitored for the Power-On-Reset (POR) purpose. Decoupling capacitor (4.7µF) be connected to GND for noise decoupling. Output Voltage Feedback pin. This pin is connected to the resistive divider that set the desired output voltage. The POK, UVP, and OVP circuits detect this signal to report output voltage status. The VOUT pin makes a direct measurement of the converter output voltage. The VOUT pin should be connected to the top feedback resistor at the converter output. POK is an open drain output used to indicate the status of the output voltage. Connect the POK pin to +5V through a pull-high resistor. Enable/Shutdown Pin or External Reference Selection of The PWM Controller. Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 11 www.anpec.com.tw APW7199 Block Diagram POK VOUT VOUT VREF x 125% GND Sense Low-Side VROCSET Debounce Time VREF x 95% /70% 125% VREF OCP OV Fault Latch Logic 70% VREF BOOT UGATE Thermal Shutdown FB On-Time Generator Digital Soft-Start VCC VCC VREF POR EN/ EXTREF ZC Error Comparator VOUT Sample and Hold VROCSET Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 PWM Signal Controller UV PHASE VCC LGATE/ OCSET PHASE 10µA To LGATE/OCSET 12 www.anpec.com.tw APW7199 Typical Application Circuit APW7199 VPOK Schottky Diode POK Q1 APM4826 UGATE RPOK CIN 10µF x 2 VIN 3V ~ 25V 100K BOOT CBOOT 0.1µF LOUT 1.5µF VOUT=1.05V PHASE 5V COUT 150µF x 2 RVCC 2.2 Q2 APM4828 LGATE/OCSET ROCSET VCC 3.24K, 1% CVCC RTOP 4.7µF 11K, 1% GND CFB-VOUT 10nF VOUT FB EN/EXTREF RGND 10K, 1% Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 13 www.anpec.com.tw APW7199 Function Description Constant-On-Time PWM Controller with Input Feed-Forward Where FSW is the nominal switching frequency of the converter in PWM mode. The constant-on-time control architecture is a pseudofixed frequency with input voltage feed-forward. This ar- The load current at handoff from PFM to PWM mode is given by: chitecture relies on the output filter capacitor’s effective series resistance (ESR) to act as a current-sense resis- 1 VIN − VOUT × × TON−PFM 2 L V − VOUT V 1 = IN × × OUT L FSW VIN ILOAD(PFMtoPWM) = tor so the output ripple voltage provides the PWM ramp signal. In PFM operation, the high-side switch on-time is In this case, APW7199 operates in ultrasonic mode with controlled by the on-time generator is determined solely by a one-shot whose pulse width is inversely propor- PFM when the load is zero. The ultrasonic mode is illustrated as below description. tional to the input voltage and directly proportional to the output voltage. In PWM operation, the high-side switch Ultrasonic Mode on-time is determined by a switching frequency control circuit in the on-time generator block. The ultrasonic mode activates an unique PFM mode with a minimum switching frequency of 20kHz. The minimum The switching frequency control circuit senses the switching frequency of the high-side switch and keeps regulat- frequency 20kHz of ultrasonic mode eliminates audiofrequency interference in light load condition. It will transit ing it at a constant frequency in PWM mode. The design improves the frequency variation and is more outstand- to unique PFM mode when output loading makes the frequency bigger than ultrasonic frequency. ing than a conventional constant-on-time controller, which has large switching frequency variation over input voltage, In ultrasonic mode, the controller automatically transits to fixed-frequency PWM operation when the load reaches output current, and temperature. Both in PFM and PWM, the same critical conduction point (ILOAD(PFM to PWM)). the on-time generator, which senses input voltage on PHASE pin, provides very fast on-time response to input When the controller detects that no switching has occurred within about 40µs (Typical), an ultrasonic pulse line transients. Another one-shot sets a minimum off-time (typical: will be occurred. The ultrasonic controller turns on the low-side MOSFET firstly to reduce the output voltage. Af- 300ns). The on-time one-shot is triggered if the error comparator is high, the low-side switch current is below the ter feedback voltage drops below the internal reference voltage, the controller turns off the low-side MOSFET and current-limit threshold, and the minimum off-time oneshot has timed out. triggers a constant-on-time. When the constant-on-time has expired, the controller turns on the low-side MOSFET Pulse-Frequency Modulation (PFM) again until the inductor current is below the zero-crossing threshold. The behavior is the same as PFM mode. In PFM mode, an automatic switchover to pulse-frequency modulation (PFM) takes place at light loads. This switchover is affected by a comparator that truncates the Power-On-Reset (POR) low-side switch on-time at the inductor current zero crossing. This mechanism causes the threshold between A Power-On-Reset (POR) function is designed to prevent wrong logic controls when the VCC voltage is low. The PFM and PWM operation to coincide with the boundary between continuous and discontinuous inductor-current POR function continually monitors the bias supply voltage on the VCC pin if at least one of the enable pins is set operation (also known as the critical conduction point). high. When the rising VCC voltage reaches the rising POR voltage threshold (4.2V, typical), the POR signal goes The on-time of PFM is given by: TON −PFM = 1 FSW × high and the chip initiates soft-start operations. When this voltage drops lower than 4.0V (typical), the POR dis- VOUT VIN Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 ables the chip. 14 www.anpec.com.tw APW7199 Function Description (Cont.) EN/EXTREF Pin Control During soft-start stage before the POK pin is ready, the under-voltage protection is prohibited. The over-voltage The voltage (V EN/EXTREF) applied to EN/EXTREF pin selects either enable-shutdown or adjustable external and over-current protection functions are enabled. If the output capacitor has residue voltage before start-up, both reference. When VEN/EXTREF is above the EN high threshold (2.75V, typical), the PWM is enabled. When VEN/EXTREF low-side and high-side MOSFETs are in off-state until the internal digital soft-start voltage is equal to the VFB voltage. is from 0.5V to 2.5V, the output voltage can be programmed as same as VEN/EXTREF voltage. When VEN/EXTREF is below This will ensure that the output voltage starts from its existing voltage level. the EN low threshold (0.4V, typical), the chip is in the shutdown and only low leakage current is taken from In the event of under-voltage or shutdown, the chip enables the soft-stop function. The soft-stop function dis- VCC. The slew rate of V EN/EXTREF must be faster than 0.5V/µs to avoid wrong output voltage. charges the output voltages to the GND through an internal 20Ω switch. Cycling the EN/EXTREF enable signal or Digital Soft-Start VCC power-on-reset signal can reset the latch. The APW7199 integrates digital soft-start circuits to ramp Power OK Indicator up the output voltage of the converter to the programmed regulation setpoint at a predictable slew rate. The slew The APW7199 features an open-drain POK pin to indicate output regulation status. In normal operation, when rate of output voltage is internally controlled to limit the inrush current through the output capacitors during soft- the output voltage rises 95% of its target value, the POK goes high. When the output voltage outruns 70% or 125% start process. The figure 1 shows soft-start sequence. When the EN/EXTREF pin is pulled above the rising EN of the target voltage, POK signal will be pulled low immediately. threshold voltage, the VOCSET voltage is equal to 10µA x ROCSET. When VCC rising POR threshold is triggered, the Since the FB pin is used for both feedback and monitoring purposes, the output voltage deviation can be coupled device starts to sample and hold the current-limit setting threshold. The sample time is as below: directly to the FB pin by the capacitor in parallel with the voltage divider as shown in the typical applications. In [IOCSET(µA) x ROCSET(kΩ) x 4.0 + 70] µs. When current-limit setting action has finished, the device order to prevent false POK from dropping, capacitors need to parallel at the output to confine the voltage deviation initiates a soft-start process to ramp up the output voltage. The soft-start interval, TSS, is about 1.5ms (typical value). with severe load step transient and the POK comparator has a built-in 3µs noise filter. Under-Voltage Protection (UVP) V In the operational process, if a short-circuit occurs, the output voltage will drop quickly. When load current is big- T SS = t2 -t1 = 1.5ms 95% x V REF VCC V POK ger than current-limit threshold value, the output voltage will fall out of the required regulation range. The under- V OUT voltage protection circuit continually monitors the VFB after soft-start is completed. If a load step is strong enough EN to pull the output voltage lower than the under-voltage threshold, the device starts to soft-stop process to shut from down the output gradually. The under-voltage threshold is 70% of the normal output voltage. The under-voltage t0 t1 t2 comparator has a built-in 2µs noise filter to prevent the chip from wrong UVP shutdown caused by noise. Cy- t cling the EN/EXTREF enable signal or VCC power-onreset signal can reset the latch. Figure 1. Soft-Start Sequence Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 15 www.anpec.com.tw APW7199 Function Description (Cont.) Over-Voltage Protection (OVP) A resistor (ROCSET), connected from the LGATE/OCSET to GND, programs the current-limit threshold. Before the IC The over-voltage function monitors the output voltage by the FB pin. When the FB voltage increases over 125% of initiates a soft-start process, an internal current source, IOCSET (10µA typical), flowing through the ROCSET develops the reference voltage due to the high-side MOSFET failure or for other reasons, the over-voltage protection com- a voltage (VOCSET) across the ROCSET. The device holds VOCSET and stops the current source, IOCSET, during normal parator designed with a 2µs noise filter will force the lowside MOSFET gate driver fully turn on. This action actively operation. The relationship between the sampled voltage VOCSET and the current-limit threshold ILIMIT is given by: pulls down the output voltage. When the FB voltage falls below 105%, the OVP comparator is disengaged and 10µA x ROCSET = ILIMIT x RDS(ON) both high-side and low-side drivers turn off. This OVP scheme only clamps the voltage overshoot, ILIMIT can be expressed as IOUT minus half of peak-to-peak inductor current. and does not invert the output voltage when otherwise activated with a continuously high output from low-side The APW7199 has an internal current-limit voltage (VOCSET_MAX), and the value is 0.25V typically. When the MOSFET driver. It’s a common problem for OVP schemes with a latch. Once an over-voltage fault condition is set, it ROCSET x IOCSET exceeds 0.25V or the ROCSET is floating or not connected, the over current threshold will be the inter- can only be reset by toggling EN/EXTREF or VCC poweron-reset signal. nal default value 0.25V. The PCB layout guidelines should ensure that noise and Current-Limit DC errors do not corrupt the current-sense signals at PHASE. Place the hottest power MOSEFTs as close to The current-limit circuit employs a “valley” current-sensing algorithm (See Figure 2). The APW7199 uses the the IC as possible for best thermal coupling. When combined with the under-voltage protection circuit, this cur- low-side MOSFET RDS(ON) of the synchronous rectifier as a rent-limit method is effective in almost every circumstance. current-sensing element. If the magnitude of the currentsense signal at PHASE pin is above the current-limit Over-Temperature Protection (OTP) threshold, the PWM is not allowed to initiate a new cycle. The actual peak current is greater than the current-limit When the junction temperature increases over the rising threshold temperature TOTR, the IC will enter the over- threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maxi- temperature protection state that suspends the PWM, which forces the UGATE and LGATE gate drivers output mum load capability are the functions of the sense resistance, inductor value, and input voltage. low. The thermal sensor allows the converters to start a start-up process and regulate the output voltage again after the junction temperature cools by 20oC. The OTP is designed with a 20oC hysteresis to lower the average TJ INDUCTOR CURRENT IPEAK IOUT during continuous thermal overload conditions, which increases lifetime of the APW7199. ΔI ILIMIT 0 Time Figure 2. Current-Limit Algorithm Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 16 www.anpec.com.tw APW7199 Application Information Output Voltage Setting choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has The output voltage is adjustable from 0.5V to 3.3V with a resistor-divider connected with FB, GND, and converter’s been chosen, selecting an inductor which is capable of carrying the required peak current without going into output. The voltage (VEN/EXTREF) applied to EN/EXTREF pin selects adjustable external reference from 0.5V to 2.5V. saturation. In some types of inductors, especially core that is made of ferrite, the ripple current will increase Using 1% or better resistors for the resistor-divider is recommended. The output voltage is determined by: R VOUT = 0.5 × 1 + TOP R GND abruptly when it saturates. This results in a larger output ripple voltage. Besides, the inductor needs to have low DCR to reduce the loss of efficiency. Output Capacitor Selection Where 0.5 is the reference voltage, RTOP is the resistor connected from converter’s output to FB, and RGND is the Output voltage ripple, the transient voltage deviation and resistor connected from FB to GND. Suggested RGND is in the range from 1K to 20kΩ. To prevent stray pickup, lo- the stability issue are factors which have to be taken into consideration when selecting an output capacitor. Higher cate resistors RTOP and RGND close to APW7199. Similarly, when VEN/EXTREF is from 0.5V to 2.5V, the output voltage capacitor value and lower ESR reduce the output ripple and the load transient drop. Generally, selecting high per- can be programmed as same as VEN/EXTREF voltage. formance low ESR capacitors is recommended for switching regulator applications. In addition to high fre- Output Inductor Selection quency noise related to MOSFET turn-on and turn-off, the output voltage ripple includes the capacitance voltage The duty cycle (D) of a buck converter is the function of the input voltage and output voltage. Once an output voltage drop ∆VCOUT and ESR voltage drop ∆VESR caused by the AC peak-to-peak inductor’s current. These two voltages can is fixed, it can be written as: D= be represented by: VOUT VIN IRIPPLE 8COUTFSW = IRIPPLE × RESR ∆VCOUT = The inductor value (L) determines the inductor ripple ∆VESR current, IRIPPLE, and affects the load transient response. Higher inductor value reduces the inductor’s ripple cur- These two components constitute a large portion of the rent and induces lower output ripple voltage. The ripple current and ripple voltage can be approximated by: total output voltage ripple. In some applications, multiple capacitors have to be paralleled to achieve the desired IRIPPLE = ESR value. If the output of the converter has to support another load with high pulsating current, more capaci- VIN - VOUT VOUT × FSW × L VIN tors are needed in order to reduce the equivalent ESR and suppress the voltage ripple to a tolerable level. Where FSW is the switching frequency of the regulator. Although the inductor value and frequency are increased and the ripple current and voltage are reduced, a tradeoff Nevertheless, the constant-on-time (COT) control architecture relies on the output capacitor’s ESR to act as a exists between the inductor’s ripple current and the regulator load transient response time. current-sense resistor, so the output ripple voltage provides the PWM ramp signal. For stability issue, the output A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. ripple also need to be considered. By stability experiment result, we suggest the feedback ripple is above Increasing the switching frequency (F SW ) also reduces the ripple current and voltage, but it will increase the 25mV when operated in the internal mode and above 40mV when operated in the external mode. switching loss of the MOSFETs and the power dissipation of the converter. The maximum ripple current occurs To support a load transient that is faster than the switching frequency, more capacitors are needed for reducing at the maximum input voltage. A good starting point is to Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 17 www.anpec.com.tw APW7199 Application Information (Cont.) Output Capacitor Selection (Cont.) Layout Consideration the voltage excursion during load step change. Another aspect of the capacitor selection is that the total AC cur- In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. With power devices switching at higher rent going through the capacitors has to be less than the rated RMS current specified on the capacitors in order to prevent the capacitor from over-heating. frequency, the resulting current transient will cause voltage spike across the interconnecting impedance and Input Capacitor Selection parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, selecting the capacitor voltage rating to be at least 1.3 times is freewheeling by the low side MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2, large voltage spike during the switching interval. In general, using short and wide printed circuit traces should where IOUT is the load current. During power-up, the input capacitors have to handle great amount of surge current. minimize interconnecting impedances and the magnitude of voltage spike. Besides, signal and power grounds For low-duty notebook appliactions, ceramic capacitor is recommended. The capacitors must be connected be- are to be kept separating and finally combined using ground plane construction or single point grounding. Fig- tween the drain of high-side MOSFET and the source of low-side MOSFET with very low-impeadance PCB layout. ure 3 illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. Com- MOSFET Selection ponents along the bold lines should be placed lose together. Below is a checklist for your layout: The selection of the N-channel power MOSFETs are determined by the R DS(ON), reversing transfer capaci- = Keep the switching nodes (UGATE, LGATE/OCSET, BOOT, and PHASE) away from sensitive small signal tance (CRSS) and maximum output current requirement. The losses in the MOSFETs have two components: nodes since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as pos- conduction loss and transition loss. For the high-side and low-side MOSFETs, the losses are approximately given by the following equations: sible and there should be no other weak signal traces in parallel with theses traces on any layer. Phigh-side = IOUT 2(1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW Plow-side = IOUT 2(1+ TC)(RDS(ON))(1-D) = The signals going through theses traces have both high dv/dt and high di/dt with high peak charging and dis- Where charging current. The traces from the gate drivers to the MOSFETs (UGATE and LGATE/OCSET) should short and IOUT is the load current TC is the temperature dependency of RDS(ON) wide. = Place the source of the high-side MOSFET and the FSW is the switching frequency tSW is the switching interval drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between D is the duty cycle Note that both MOSFETs have conduction losses while the two pads reduces the voltage bounce of the node. In addition, the large layout plane between the drain of the the high-side MOSFET includes an additional transition loss. The switching interval, tSW , is the function of the re- MOSFETs (VIN and PHASE nodes) can get better heat sinking. verse transfer capacitance CRSS. The (1+TC) term is a factor in the temperature dependency of the RDS(ON) and = Decoupling capacitors, the resistor-divider, and boot capacitor should be close to their pins. (For example, place can be extracted from the “RDS(ON) vs. Temperature” curve of the power MOSFET. the decoupling ceramic capacitor close to the drain of the high-side MOSFET as close as possible.) Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 18 www.anpec.com.tw APW7199 Application Information (Cont.) Layout Consideration (Cont.) = The input bulk capacitors should be close to the drain of the high-side MOSFET, and the output bulk capacitors should be close to the loads. The input capacitor’s ground should be close to the grounds of the output capacitors and low-side MOSFET. = Locate the resistor-divider close to the FB pin to minimize the high impedance trace. In addition, FB pin traces can’t be close to the switching signal traces (UGATE, LGATE/OCSET, BOOT, and PHASE). = The ROCSET resistance should be placed near the IC as close as possible. APW7199 VIN VCC BOOT L O A D UGATE PHASE LGATE/OCSET VOUT ROCSET Close to IC Figure 3. Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 19 www.anpec.com.tw APW7199 Package Information TDFN3x3-10 D E A b Pin 1 A1 D2 A3 NX aaa C L K E2 Pin 1 Corner e S Y M B O L A A1 A3 TDFN3x3-10 MILLIMETERS INCHES MIN. MAX. MIN. MAX. 0.70 0.80 0.028 0.031 0.05 0.000 0.002 0.00 b 0.18 0.30 0.008 REF 0.007 0.012 D 2.90 3.10 0.114 0.122 D2 E 2.20 2.70 0.087 0.106 3.10 0.114 0.122 E2 2.90 1.40 1.75 0.055 0.069 e L 0.30 0.50 0.016 BSC 0.012 0.020 K 0.20 aaa 0.20 REF 0.50 BSC 0.008 0.08 0.003 Note : 1. Followed from JEDEC MO-229 VEED-5. Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 20 www.anpec.com.tw APW7199 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TDFN3x3-10 A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.20 1.75±0.10 3.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.35±0.20 3.35±0.20 1.30±0.20 4.0±0.10 4.0±0.10 (mm) Devices Per Unit Package Type TDFN3x3-10 Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 Quantity 3000 21 www.anpec.com.tw APW7199 Taping Direction Information TDFN3x3-10 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 22 www.anpec.com.tw APW7199 Classification Reflow Profiles (Cont.) Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) 3 Package Thickness <2.5 mm Volume mm <350 235 °C Volume mm ≥350 220 °C ≥2.5 mm 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 23 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW7199 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 24 www.anpec.com.tw