SN74AUC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES509 – NOVEMBER 2003 – REVISED DECEMBER 2005 FEATURES • VCC 1 14 2 13 4OE 3 12 4A 4 11 4Y 5 6 10 3OE 9 3A 7 8 3Y • • • • • 1A 1Y 2OE 2A 2Y 1OE • RGY PACKAGE (TOP VIEW) Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub 1-V Operable Max tpd of 2.1 ns at 1.8 V Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1500-V Charged-Device Model (C101) GND • DESCRIPTION/ORDERING INFORMATION This quadruple bus buffer gate is designed for 0.8-V to 2.7-V VCC operation, but is designed specifically for 1.6-V to 1.95-V VCC operation. The SN74AUC126 contains four independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) QFN – RGY ORDERABLE PART NUMBER Tape and reel SN74AUC126RGYR TOP-SIDE MARKING MS126 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS OE A OUTPUT Y H H H H L L L X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2005, Texas Instruments Incorporated SN74AUC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES509 – NOVEMBER 2003 – REVISED DECEMBER 2005 LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1A 2OE 2A 1 3OE 2 3 1Y 3A 4 4OE 5 6 2Y 4A 10 9 8 3Y 13 12 11 4Y Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range –0.5 3.6 UNIT V range (2) VI Input voltage –0.5 3.6 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 3.6 V VO Output voltage range (2) –0.5 VCC + 0.5 IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±20 mA ±100 mA Continuous current through VCC or GND θJA Package thermal Tstg Storage temperature range (1) (2) (3) 2 impedance (3) –65 V 47 °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-5. SN74AUC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES509 – NOVEMBER 2003 – REVISED DECEMBER 2005 Recommended Operating Conditions VCC (1) Supply voltage VCC = 0.8 V VIH High-level input voltage VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V MIN MAX 0.8 2.7 Low-level input voltage VI Input voltage 0.65 × VCC Output voltage IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature (1) V 1.7 0 0.35 × VCC VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V VO V VCC VCC = 0.8 V VIL UNIT V 0.7 0 3.6 Active state 0 VCC 3-state 0 3.6 VCC = 0.8 V –0.7 VCC = 1.1 V –3 VCC = 1.4 V –5 VCC = 1.65 V –8 VCC = 2.3 V –9 VCC = 0.8 V 0.7 VCC = 1.1 V 3 VCC = 1.4 V 5 VCC = 1.65 V 8 VCC = 2.3 V 9 –40 V V mA mA 20 ns/V 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 SN74AUC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES509 – NOVEMBER 2003 – REVISED DECEMBER 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VOH VOL (1) MIN TYP (1) MAX VCC IOH = –100 µA 0.8 V to 2.7 V IOH = –0.7 mA 0.8 V IOH = –3 mA 1.1 V 0.8 IOH = –5 mA 1.4 V 1 IOH = –8 mA 1.65 V 1.2 IOH = –9 mA 2.3 V 1.8 IOL = 100 µA 0.8 V to 2.7 V IOL = 0.7 mA 0.8 V IOL = 3 mA 1.1 V 0.3 IOL = 5 mA 1.4 V 0.4 IOL = 8 mA 1.65 V 0.45 IOL = 9 mA 2.3 V 0.6 UNIT VCC – 0.1 0.55 V 0.2 0.25 V II VI = VCC or GND 0 to 2.7 V ±5 µA Ioff VI or VO = 2.7 V 0 ±10 µA IOZ VO = VCC or GND 2.7 V ±10 µA ICC VI = VCC or GND, 10 µA Ci VI = VCC or GND 2.5 V 2.5 pF Co VO = VCC or GND 2.5 V 5 pF IO = 0 0.8 V to 2.7 V All typical values are at TA = 25°C. Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) VCC = 1.2 V ± 0.1 V FROM (INPUT) TO (OUTPUT) VCC = 0.8 V tpd A Y 5.8 0.7 ten OE Y 6.2 tdis OE Y 4.3 PARAMETER TYP VCC = 1.5 V ± 0.1 V MIN MAX VCC = 1.8 V ± 0.15 V MIN MAX MIN 3.7 0.6 2.6 0.5 0.9 3.8 0.7 2.5 1.6 4.7 1.5 3.5 VCC = 2.5 V ± 0.2 V TYP MAX MIN MAX UNIT 1 2.1 0.5 1.3 ns 0.6 1 2.2 0.6 1.3 ns 1.4 2.4 3.4 1 2.5 ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1) 4 VCC = 1.8 V ± 0.15 V FROM (INPUT) TO (OUTPUT) tpd A Y 0.5 1.8 ten OE Y 0.6 1.6 tdis OE Y 1.2 2.4 PARAMETER MIN VCC = 2.5 V ± 0.2 V TYP MAX UNIT MIN MAX 2.6 0.5 2.1 ns 2.7 0.6 2.2 ns 3.3 0.8 2.2 ns SN74AUC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES509 – NOVEMBER 2003 – REVISED DECEMBER 2005 Operating Characteristics TA = 25°C TEST CONDITIONS PARAMETER Cpd Power dissipation capacitance Outputs enabled Outputs disabled VCC = 0.8 V VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V TYP TYP TYP TYP TYP 15 15 15 16 17 2 2 2 3 4 f = 10 MHz UNIT pF 5 SN74AUC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES509 – NOVEMBER 2003 – REVISED DECEMBER 2005 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND RL LOAD CIRCUIT VCC CL RL V∆ 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 15 pF 15 pF 15 pF 15 pF 15 pF 30 pF 30 pF 2 kΩ 2 kΩ 2 kΩ 2 kΩ 2 kΩ 1 kΩ 500 Ω 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V 0.15 V 0.15 V VCC Timing Input VCC/2 0V tw tsu th VCC VCC/2 Input VCC/2 VCC VCC/2 Data Input VCC/2 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 Input VCC/2 0V tPHL tPLH VOH VCC/2 Output VCC/2 VOL tPHL VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VCC/2 VCC/2 0V tPZL tPLZ VCC VCC/2 tPZH VOH Output Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH VCC/2 VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VCC/2 VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. 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