TI TPS74301KTWTG3

TPS74301
TP
S
743
01
TP
S7
43
01
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SBVS065E – DECEMBER 2005 – REVISED MAY 2007
1.5A Ultra-LDO with Programmable Sequencing
FEATURES
•
•
•
•
•
•
•
•
•
•
Track Pin Allows for Flexible Power-Up
Sequencing
1% Accuracy Over Line, Load, and
Temperature
Supports Input Voltages as Low as 0.9V with
External Bias Supply
Adjustable Output (0.8V to 3.6V)
Ultra-Low Dropout: 55mV at 1.5A (typ)
Stable with Any or No Output Capacitor
Excellent Transient Response
Available in 5mm × 5mm × 1mm QFN and
DDPAK-7 Packages
Open-Drain Power-Good (5 × 5 QFN)
Active High Enable
APPLICATIONS
•
•
•
•
FPGA Applications
DSP Core and I/O Voltages
Post-Regulation Applications
Applications with Special Start-Up Time or
Sequencing Requirements
DESCRIPTION
The TPS74301 low-dropout (LDO) linear regulator
provides an easy-to-use robust power management
solution for a wide variety of applications. The
TRACK pin allows the output to track an external
supply. This feature is useful in minimizing the stress
on ESD structures that are present between the
CORE and I/O power pins of many processors. The
enable input and power-good output allow easy
sequencing with external regulators. This complete
flexibility allows the user to configure a solution that
meets the sequencing requirements of FPGAs,
DSPs, and other applications with special start-up
requirements.
A precision reference and error amplifier deliver 1%
accuracy over load, line, temperature, and process.
Each LDO is stable with low-cost ceramic output
capacitors and the device is fully specified from
–40°C to +125°C. The TPS74301 is offered in a
small (5mm × 5mm) QFN package, yielding a highly
compact total solution size. For applications that
require additional power dissipation, the DDPAK
(KTW) package is also available.
IOUT = 500mA
VIN
IN
R5
EN
VBIAS
VPG
PG
TPS74301
CBIAS
BIAS
R1
VTRACK
R3
FB
TRACK
GND
VTRACK
VPG
VOUT
OUT
COUT
500mV/div
CIN
R2
R4
Optional
Figure 1. Typical Application Circuit
VOUT
Time (20ms/div)
Figure 2. Tracking Response
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2007, Texas Instruments Incorporated
TPS74301
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SBVS065E – DECEMBER 2005 – REVISED MAY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION (1)
VOUT (2)
PRODUCT
TPS743xxyyyz
(1)
(2)
(3)
XX is nominal output voltage (for example, 12 = 1.2V, 15 = 1.5V, 01 = Adjustable). (3)
YYY is package designator.
Z is package quantity.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Output voltages from 0.9V to 1.5V in 50mV increments and 1.5V to 3.3V in 100mV increments are available through the use of
innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability.
For fixed 0.8V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS (1)
At TJ = –40°C to +125°C, unless otherwise noted. All voltages are with respect to GND.
TPS74301
UNIT
–0.3 to +6
V
VEN Enable voltage range
–0.3 to +6
V
VPG Power-good voltage range
–0.3 to +6
V
0 to +1.5
mA
–0.3 to +6
V
–0.3 to +6
V
–0.3 to VIN + 0.3
V
VIN, VBIAS Input voltage range
IPG PG sink current
VTRACK Track pin voltage range
VFB Feedback pin voltage range
VOUT Output voltage range
IOUT Maximum output current
Internally limited
Output short circuit duration
Indefinite
PDISS Continuous total power dissipation
See Dissipation Ratings Table
TJ Operating junction temperature range
TSTG Storage junction temperature range
(1)
–40 to +125
°C
–55 to +150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
DISSIPATION RATINGS
PACKAGE
θJA
θJC
TA < +25°C
POWER RATING
DERATING FACTOR
ABOVE TA = +25°C
RGW (QFN) (1)
36.5°C/W
4.05°C/W
2.74W
27.4mW/°C
18.8°C/W
2.32°C/W
5.32W
53.2mW/°C
KTW
(1)
(2)
2
(DDPAK) (2)
See Figure 31 for PCB layout description.
See Figure 34 for PCB layout description.
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SBVS065E – DECEMBER 2005 – REVISED MAY 2007
ELECTRICAL CHARACTERISTICS
At VEN = 1.1V, VIN = VOUT + 0.3V, CIN = CBIAS = 0.1µF, COUT = 10µF, IOUT = 50mA, VBIAS = 5.0V, and TJ = –40°C to +125°C,
unless otherwise noted. Typical values are at TJ = +25°C.
TPS74301
PARAMETER
MAX
UNIT
VIN Input voltage range
VOUT + VDO
5.5
V
VBIAS Bias pin voltage range
2.375
5.25
V
0.804
V
VREF Internal reference (Adj.)
VOUT
TJ = +25°C
0.796
VIN = 5V, IOUT = 1.5A, VBIAS = 5V
VREF
Accuracy (1)
2.375V ≤ VBIAS ≤ 5.25V, 50mA ≤ IOUT ≤ 1.5A
VOUT/IOUT Load regulation
VIN dropout voltage (2)
VBIAS dropout voltage (2)
ICL Current limit
IBIAS Bias pin current
ISHDN
Shutdown supply current
(VIN)
IFB Feedback pin current (3)
PSRR
V
±0.2
1
%
VOUT
(NOM)
+ 0.3 ≤ VIN ≤ 5.5V, QFN
0.0005
0.05
VOUT
(NOM)
+ 0.3 ≤ VIN ≤ 5.5V, DDPAK
0.0005
0.06
0mA ≤ IOUT ≤ 50mA
0.013
50mA ≤ IOUT ≤ 1.5A
0.04
100
IOUT = 1.5A, VBIAS – VOUT (NOM) ≥ 1.62V, DDPAK
60
120
VOUT = 80% × VOUT (NOM)
1.4
V
4
A
2
4
mA
VEN ≤ 0.4V
1
100
µA
68
250
nA
IOUT = 50mA to 1.5A
1.8
mV
IOUT = 0mA to 1.5A
–250
42
Power-supply rejection
(VBIAS to VOUT)
1kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V
67
800kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V
50
%VOUT droop during load
transient
%/A
55
IOUT = 1.5A, VIN = VBIAS
%/V
%/mA
IOUT = 1.5A, VBIAS – VOUT (NOM) ≥ 1.62V, QFN
800kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V
ITR Track pin current
dB
dB
25 × VOUT
µVRMS
IOUT = 50mA to 1.5A at 1A/µs, COUT = none
3.5
%VOUT
VTRACK > 0.8V
40
µs
100Hz to 100kHz, IOUT = 1.5A
0.2V ≤ VTRACK≤ 0.7V, VOUT = 0.8V
–60
VTRACK = 0.4V
0.1
60
mV
1
µA
HI
Enable input high level
1.1
5.5
V
LO
Enable input low level
0
0.4
V
HYS
Enable pin hysteresis
50
Enable pin deglitch time
20
VEN,
VEN,
DG
IEN Enable pin current
VEN = 5V
VIT PG trip threshold
VOUT decreasing
86.5
VHYS PG trip hysteresis
(1)
(2)
(3)
3.6
Power-supply rejection
(VIN to VOUT)
TACC Track pin accuracy
VEN,
0.8
73
tSTR Minimum startup time
VEN,
–1
TYP
1kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V
Noise Output noise voltage
VTRAN
MIN
Output voltage range
VOUT/VIN Line regulation
VDO
TEST CONDITIONS
IPG = 1mA (sinking), VOUT < VIT
IPG, LKG PG leakage current
VPG = 5.25V, VOUT > VIT
TJ
TSD
Thermal shutdown
temperature
µs
0.1
1
µA
90
93.5
%VOUT
3
VPG, LO PG output low voltage
Operating junction
temperature
mV
0.3
–40
Shutdown, temperature increasing
+155
Reset, temperature decreasing
+140
%VOUT
0.3
V
1
µA
+125
°C
°C
Adjustable devices tested at 0.8V; external resistor tolerance is not taken into account.
Dropout is defined as the voltage from the input to VOUT when VOUT is 2% below nominal.
IFB current flow is out of the device.
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SBVS065E – DECEMBER 2005 – REVISED MAY 2007
BLOCK DIAGRAM
Current
Limit
IN
BIAS
VOUT
UVLO
Thermal
Limit
VTRACK < VREF = 1, VTRACK > VREF = 0
R1
1
TRACK
0
VOUT = 0.8 x (1 +
0.8V
Reference
FB
PG
EN
Hysteresis
and De-Glitch
R2
0.9 ´ VREF
GND
Table 1. Standard 1% Resistor Values for Programming the Output Voltage (1)
(1)
4
R1 (kΩ)
R2 (kΩ)
VOUT (V)
Short
Open
0.8
0.619
4.99
0.9
1.13
4.53
1.0
1.37
4.42
1.05
1.87
4.99
1.1
2.49
4.99
1.2
4.12
4.75
1.5
3.57
2.87
1.8
3.57
1.69
2.5
3.57
1.15
3.3
VOUT = 0.8 × (1 + R1/R2)
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R1
)
R2
TPS74301
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SBVS065E – DECEMBER 2005 – REVISED MAY 2007
IN
NC
NC
NC
OUT
5
4
3
2
1
5 ´ 5 QFN (RGW)
Package ¾ Top View
7-Lead
DDPAK (KTW)
Surface-Mount
IN
6
20
OUT
IN
7
19
OUT
IN
8
18
OUT
PG
9
17
NC
BIAS
10
16
FB
11
12
13
14
15
EN
GND
NC
NC
TRACK
TPS74301
1 2 3 4 5 6 7
TRACK OUT IN EN
FB GND BIAS
PIN DESCRIPTIONS
NAME
KTW (DDPAK)
RGW (QFN)
DESCRIPTION
IN
5
5–8
Unregulated input to the device.
EN
7
11
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts
the regulator into shutdown mode. This pin must not be left floating.
TRACK
1
15
Tracking pin. Connect this pin to the center tap of a resistor divider off of an
external supply to program the device to track an external supply.
BIAS
6
10
Bias input voltage for error amplifier, reference, and internal control circuits.
PG
N/A
9
Power-Good (PG) is an open-drain, active-high output that indicates the status
of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a
high-impedance state. When VOUT is below this threshold the pin is driven to a
low-impedance state. A pull-up resistor from 10kΩ to 1MΩ should be
connected from this pin to a supply up to 5.5V. The supply can be higher than
the input voltage. Alternatively, the PG pin can be left floating if output
monitoring is not necessary.
FB
2
16
This pin is the feedback connection to the center tap of an external resistor
divider network that sets the output voltage. This pin must not be left floating.
OUT
3
1, 18–20
NC
N/A
2–4, 13, 14, 17
GND
4
12
PAD/TAB
Regulated output voltage. No capacitor is required on this pin for stability.
No connection. This pin can be left floating or connected to GND to allow better
thermal contact to the top-side plane.
Ground
Should be soldered to the ground plane for increased thermal performance.
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TYPICAL CHARACTERISTICS
At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1µF, CBIAS = 4.7µF, and COUT = 10µF,
unless otherwise noted.
LOAD REGULATION
1.0
LOAD REGULATION
0.050
Referred to IOUT = 50mA
0.9
Referred to IOUT = 50mA
0.025
0.7
0.6
-40°C
0.5
0.4
+25°C
0.3
0.2
0.1
0
Change in VOUT (%)
Change in VOUT (%)
0.8
-0.050
-40°C
-0.075
+125°C
-0.100
+125°C
0
+25°C
-0.025
-0.125
-0.1
-0.150
0
10
20
30
40
50
50
500
1000
1500
IOUT (mA)
IOUT (mA)
Figure 3.
Figure 4.
LINE REGULATION
VIN DROPOUT VOLTAGE vs
IOUT AND TEMPERATURE (TJ)
0.05
100
0.04
0.02
Dropout Voltage (mV)
Change in VOUT (%)
0.03
TJ = -40°C
0.01
0
-0.01
TJ = +25°C
TJ = +125°C
-0.02
-0.03
75
+125°C
50
+25°C
25
-40°C
-0.04
0
-0.05
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
0.5
VIN - VOUT (V)
Figure 6.
VIN DROPOUT VOLTAGE vs
VBIAS – VOUT AND TEMPERATURE (TJ)
VIN DROPOUT VOLTAGE vs
VBIAS – VOUT AND TEMPERATURE (TJ)
60
IOUT = 1.5A
180
IOUT = 500mA
50
Dropout Voltage (mV)
160
Dropout Voltage (mV)
1.5
Figure 5.
200
140
120
+125°C
100
+25°C
80
60
40
40
+125°C
30
+25°C
20
10
-40°C
20
-40°C
0
0
0.9
1.4
1.9
2.4
2.9
3.4
3.9
0.9
VBIAS - VOUT (V)
1.4
1.9
2.4
2.9
VBIAS - VOUT (V)
Figure 7.
6
1.0
IOUT (A)
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1µF, CBIAS = 4.7µF, and COUT = 10µF,
unless otherwise noted.
VBIAS PSRR vs FREQUENCY
1400
90
1300
80
1200
+25°C
+125°C
1100
Power-Supply Rejection (dB)
Dropout Voltage (mV)
VBIAS DROPOUT VOLTAGE vs
IOUT AND TEMPERATURE
1000
-40°C
900
800
700
IOUT = 1.5A
70
60
50
40
30
20
10
600
0
500
50
500
1000
1500
10
100
Figure 10.
60
50
40
30
20
COUT = 0mF
10
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
COUT = 100mF C
OUT = 10mF
70
100
1k
10k
100k
80
70
COUT = 100mF
60
COUT = 10mF
50
40
30
20
10
COUT = 0mF
1M
10
10M
100
Figure 11.
Figure 12.
700kHz
60
50
300kHz
100kHz
20
10
IOUT = 1.5A
0
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
Output Spectral Noise Density (mV/ÖHz)
1kHz
40
100k
1M
10M
NOISE SPECTRAL DENSITY
80
0
10k
Frequency (Hz)
VIN PSRR vs VIN – VOUT
30
1k
Frequency (Hz)
90
70
10M
VIN = 1.8, VOUT = 1.5V, IOUT = 1.5A
90
0
0
10
1M
VIN PSRR vs FREQUENCY
VIN = 1.8, VOUT = 1.5V, IOUT = 100mA
80
100k
Figure 9.
100
90
10k
Frequency (Hz)
VIN PSRR vs FREQUENCY
100
Power-Supply Rejection Ratio (dB)
1k
IOUT (mA)
1
IOUT = 1.5A
VOUT = 1.1V
0.1
0.01
100
VIN - VOUT (V)
1k
10k
100k
Frequency (Hz)
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1µF, CBIAS = 4.7µF, and COUT = 10µF,
unless otherwise noted.
VBIAS LINE TRANSIENT
VIN LINE TRANSIENT (1.5A)
20mV/div
COUT = 2 x 470mF (OSCON)
20mV/div
COUT = 100mF (Cer.)
10mV/div
COUT = 2 x 470mF (OSCON)
VOUT = 1.2V
COUT = 100mF (Cer.)
10mV/div
10mV/div
COUT = 10mF (Cer.)
COUT = 10mF (Cer.)
20mV/div
COUT = 0mF
10mV/div
COUT = 0mF
20mV/div
2.5V
4.3V
4.3V
1V/div
1V/ms
500mV/div
1V/ms
3.3V
1.5V
Time (50ms/div)
Time (50ms/div)
Figure 15.
Figure 16.
OUTPUT LOAD TRANSIENT RESPONSE
TRACKING RESPONSE
COUT = 2 x 470mF (OSCON)
IOUT = 500mA
50mV/div
COUT = 100mF (Cer.)
50mV/div
VTRACK
50mV/div
500mV/div
VPG
COUT = 10mF (Cer.)
COUT = 0mF
50mV/div
VOUT
1.5A
1A/ms
1A/div
50mA
Time (50ms/div)
Time (20ms/div)
Figure 17.
Figure 18.
POWER-UP/POWER-DOWN
IBIAS vs IOUT AND TEMPERATURE
2.85
VIN = VBIAS = VEN
VPG (500mV/div)
VOUT
Bias Current (mA)
1V/div
2.65
+125°C
2.45
2.25
2.05
+25°C
1.85
1.65
-40°C
1.45
1.25
Time (20ms/div)
0
0.5
1.0
IOUT (A)
Figure 19.
8
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1µF, CBIAS = 4.7µF, and COUT = 10µF,
unless otherwise noted.
IBIAS vs VBIAS AND VOUT
IBIAS SHUTDOWN vs TEMPERATURE
3.0
0.45
2.8
2.4
2.2
+25°C
2.0
1.8
1.6
-40°C
1.4
VBIAS = 2.375V
0.35
Bias Current (mA)
Bias Current (mA)
0.40
+125°C
2.6
0.30
VBIAS = 5.5V
0.25
0.20
0.15
0.10
0.05
1.2
1.0
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-40
0
-20
VBIAS (V)
20
40
60
80
100
120
Junction Temperature (°C)
Figure 21.
Figure 22.
TURN-ON RESPONSE–QFN PACKAGE
LOW-LEVEL PG VOLTAGE vs PG CURRENT
VTRACK = VIN
IOUT = 1.5A
VOUT
1V/div
1.1V
1V/div
0V
VEN
VOL Low-Level PG Voltage (V)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Time (50ms/div)
0
2
6
4
8
10
12
PG Current (mA)
Figure 23.
Figure 24.
OUTPUT SHORT-CIRCUIT RECOVERY
IOUT
500mA/div
VOUT
50mV/div
Output Shorted
Output Open
Time (20ms/div)
Figure 25.
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APPLICATION INFORMATION
The TPS74301 belongs to a family of new
generation ultra-low dropout regulators that feature
soft-start and tracking capabilities. These regulators
use a low current bias input to power all internal
control circuitry, allowing the NMOS pass transistor
to regulate very low input and output voltages.
Figure 26 is a typical application circuit for the
TPS74301 adjustable device.
R1 and R2 can be calculated for any output voltage
using the formula shown in Figure 26. Refer to
Table 1 for sample resistor values of common output
voltages. In order to achieve the maximum accuracy
specifications, R2 should be ≤ 4.99kΩ.
The use of an NMOS-pass FET offers several critical
advantages for many applications. Unlike a PMOS
topology device, the output capacitor has little effect
on loop stability. This architecture allows the
TPS74301 to be stable with any or even no output
capacitor. Transient response is also superior to
PMOS topologies, particularly for low VIN
applications.
INPUT, OUTPUT, AND BIAS CAPACITOR
REQUIREMENTS
The device does not require any output capacitor for
stability. If an output capacitor is needed, the device
is designed to be stable for all available types and
values of output capacitance. The device is also
stable with multiple capacitors in parallel, of any type
or value.
The TPS74301 features a TRACK pin that allows the
output to track an external supply. This feature is
useful in minimizing the stress on ESD structures
that are present between the CORE and I/O power
pins of many processors. A power-good (PG) output
is also available to allow supply monitoring and
sequencing of follow-on supplies. To control the
output turn-on, an enable (EN) pin with hysteresis
and deglitch is provided to allow slow-ramping
signals to be utilized for sequencing the device. The
low VIN and VOUT capability allows for inexpensive,
easy-to-design, and efficient linear regulation
between the multiple supply voltages often present in
processor intensive systems.
The capacitance required on the IN and BIAS pins is
strongly dependent on the input supply source
impedance. To counteract any inductance in the
input, the minimum recommended capacitor for VIN
and VBIAS is 1µF. If VIN and VBIAS are connected to
the same supply, the recommended minimum
capacitor for VBIAS is 4.7µF. Good quality, low ESR
capacitors should be used on the input; ceramic X5R
and X7R capacitors are preferred. These capacitors
should be placed as close the pins as possible for
optimum performance.
VIN
CIN
IN
PG
TPS74301
R5
EN
VBIAS
VPG
VOUT
OUT
CBIAS
BIAS
R1
VTRACK
R3
FB
TRACK
COUT
Optional
GND
R2
R4
VOUT = 0.8 ´
(
1+
R1
R2
)
Figure 26. Typical Application Circuit for the TPS74301 (Adjustable)
10
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TRANSIENT RESPONSE
IN
BIAS
The TPS74301 was designed to have transient
response within 5% for most applications without any
output capacitor. In some cases, the transient
response may be limited by the transient response of
the input supply. This limitation is especially true in
applications where the difference between the input
and output is less than 300mV. In this case, adding
additional input capacitance improves the transient
response much more than just adding additional
output capacitance would do. With a solid input
supply, adding additional output capacitance reduces
undershoot and overshoot during a transient at the
expense of a slightly longer VOUT recovery time.
Refer to Figure 17 in the Typical Characteristics
section. Since the TPS74301 is stable without an
output capacitor, many applications may allow for
little or no capacitance at the LDO output. For these
applications, local bypass capacitance for the device
under power may be sufficient to meet the transient
requirements of the application. This design reduces
the total solution cost by avoiding the need to use
expensive high-value capacitors at the LDO output.
DROPOUT VOLTAGE
The TPS74301 offers industry-leading dropout
performance, making it well-suited for high-current
low VIN/low VOUT applications. The extremely low
dropout of the TPS74301 allows the device to be
used instead of a DC/DC converter and still achieve
good efficiencies. This efficiency allows users to
rethink the power architecture for their applications to
find the smallest, simplest, and lowest cost solution.
Reference
VBIAS = 5V ± 5%
VIN = 1.8V
VOUT = 1.5V
IOUT = 1.5A
Efficiency = 83%
OUT
FB
Simplified Block Diagram
Figure 27. Typical Application of the TPS74301
Using an Auxiliary Bias Rail
The second specification (see Figure 28), referred to
as VBIAS Dropout, is for users who wish to tie IN and
BIAS together. This option allows the device to be
used in applications where an auxiliary bias voltage
is unavailable or low dropout is not required. Dropout
is limited by BIAS in these applications because
VBIAS provides the gate drive to the pass FET, and
therefore must be 1.4V above VOUT.
VIN
BIAS
Reference
IN
VBIAS = 3.3V ± 5%
VIN = 3.3V ± 5%
VOUT = 1.5V
IOUT = 1.5A
Efficiency = 45%
OUT
There are two different specifications for dropout
voltage with the TPS74301. The first specification (as
shown in Figure 27) is referred to as VIN Dropout and
is for users wishing to apply an external bias voltage
to achieve low dropout. This specification assumes
that VBIAS is at least 1.62V above VOUT, which is the
case for VBIAS when powered by a 3.3V rail with 5%
tolerance and with VOUT = 1.5V. If VBIAS is higher
than 3.3V × 0.95 or VOUT is less than 1.5V, VIN
dropout is less than specified.
VOUT
VOUT
FB
Simplified Block Diagram
Figure 28. Typical Application of the TPS74301
Without an Auxiliary Bias
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PROGRAMMABLE SEQUENCING WITH
TRACK
The TPS74301 features a track pin that allows the
output to track an external supply at start-up. While
the TRACK input is below 0.8V, the error amplifier
regulates the FB pin to the TRACK input. Properly
choosing the resistor divider network (R1 and R2) as
shown in Figure 29 enables the regulator output to
track the external supply to obtain a simultaneous or
ratiometric start-up. Once the TRACK input reaches
0.8V, the error amplifier regulates the FB pin to the
0.8V internal reference. Further increases to the
TRACK input have no effect.
TPS74201 LDO1
IN
5V
R3
32.4kW
(1)
OUT
BIAS
PG
EN
SS
DSP
3.3V
I/O
R1
R4
10kW
R2
TPS74301 LDO2
OUT
IN
BIAS
EN
(1)
1.2V
CORE
The device can have VIN, VBIAS, VEN, and VTRACK
sequenced in any order without causing damage to
the device. However, for the track function to work as
intended, certain sequencing rules must be applied.
VBIAS must be present and the device enabled before
the track signal starts to ramp. VIN should ramp up
faster than the external supply being tracked so that
the tracking signal will not drive the device into VIN
dropout as VOUT ramps up. The preferred method to
sequence the tracking device is to have VIN, VBIAS,
and VEN above the minimum required voltages
before enabling the master supply to initiate the
startup sequence. This method is illustrated in
Figure 29. Resistors R3 and R4 disable the master
supply until the input voltage is above 3.52V
(typical).
If the TRACK pin is not needed it should be
connected to VIN. Configured in this way, the device
starts up typically within 40µs, which may result in
large inrush current that could cause the input supply
to droop. If soft-start is needed, consider the
TPS74201 or TPS74401 devices.
PG
OUTPUT NOISE
TRACK
SIMULTANEOUS SEQUENCING
I/O
CORE
R1 =
VCCCORE - 0.8
0.8
RATIOMETRIC SEQUENCING
VOUT
SEQUENCING REQUIREMENTS
x R2
(2)
I/O
CORE
R1 =
VCCIO - 0.808
0.808
x R2
The TPS74301 provides low output noise when a
soft-start capacitor is used. When the device reaches
the end of the soft-start cycle, the soft-start capacitor
serves as a filter for the internal reference. By using
a 0.001µF soft-start capacitor, the output noise is
reduced by half and is typically 30µVRMS for a 1.2V
output (10Hz to 100kHz). Because most of the
output noise is generated by the internal reference,
the noise is a function of the set output voltage. The
RMS noise with a 0.001µF soft-start capacitor is
given in Equation 1.
ǒmVV Ǔ
V NǒmVRMSǓ + 25
Time
NOTES: (1) Capacitors on IN, BIAS, and OUT along with the resistors
necessary to set the output voltage have been omitted for simplification.
(2) Lowest value for VCORE and highest value for R2 should be used
in this calculation. R1 must be the closest standard value below the
calculated value for proper ratiometric sequencing.
Figure 29. Various Sequencing Methods Using
the TRACK Pin
The maximum recommended value for R2 is 100kΩ.
Once R2 is selected, R1 is calculated using one of
the equations given in Figure 29.
12
RMS
V OUT(V)
(1)
The low output noise of the TPS74301 makes it a
good choice for powering transceivers, PLLs, or
other noise-sensitive circuitry.
ENABLE/SHUTDOWN
The enable (EN) pin is active high and is compatible
with standard digital signaling levels. VEN below 0.4V
turns the regulator off, while VEN above 1.1V turns
the regulator on. Unlike many regulators, the enable
circuitry has hysteresis and deglitching for use with
relatively slow-ramping analog signals. This
configuration allows the TPS74301 to be enabled by
connecting the output of another supply to the EN
pin. The enable circuitry typically has 50mV of
hysteresis and a deglitch circuit to help avoid on-off
cycling because of small glitches in the VEN signal.
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The enable threshold is typically 0.8V and varies with
temperature and process variations. Temperature
variation is approximately –1mV/°C; therefore,
process variation accounts for most of the variation
in the enable threshold. If precise turn-on timing is
required, a fast rise-time signal should be used to
enable the TPS74301.
If not used, EN can be connected to either IN or
BIAS. If EN is connected to IN, it should be
connected as close as possible to the largest
capacitance on the input to prevent voltage droops
on that line from triggering the enable circuit.
POWER-GOOD (QFN Package Only)
The power-good (PG) pin is an open-drain output
and can be connected to any 5.5V or lower rail
through an external pull-up resistor. This pin requires
at least 1.1V on VBIAS in order to have a valid output.
The PG output is high-impedance when VOUT is
greater than VIT + VHYS. If VOUT drops below VIT or if
VBIAS drops below 1.9V, the open-drain output turns
on and pulls the PG output low. The PG pin also
asserts when the device is disabled. The
recommended operating condition of PG pin sink
current is up to 1mA, so the pull-up resistor for PG
should be in the range of 10kΩ to 1MΩ. PG is only
provided on the QFN package. If output voltage
monitoring is not needed, the PG pin can be left
floating.
INTERNAL CURRENT LIMIT
The TPS74301 features a factory-trimmed, accurate
current limit that is flat over temperature and supply
voltage. The current limit allows the device to supply
surges of up to 1.8A and maintain regulation. The
current limit responds in about 10µs to reduce the
current during a short-circuit fault. Recovery from a
short-circuit condition is well-controlled and results in
very little output overshoot when the load is
removed. See Figure 25 in the Typical
Characteristics section for output short-circuit
recovery performance.
The internal current limit protection circuitry of the
TPS74301 is designed to protect against overload
conditions. It is not intended to allow operation above
the rated current of the device. Continuously running
the TPS74301 above the rated current degrades
device reliability.
THERMAL PROTECTION
dissipation, thermal resistance, and ambient
temperature the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage as a result of
overheating.
Activation of the thermal protection circuit indicates
excessive
power
dissipation
or
inadequate
heatsinking. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete
design (including heatsink), increase the ambient
temperature until thermal protection is triggered; use
worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+30°C above the maximum expected ambient
condition of the application. This condition produces
a worst-case junction temperature of +125°C at the
highest expected ambient temperature and
worst-case load.
The internal protection circuitry of the TPS74301 is
designed to protect against overload conditions. It is
not intended to replace proper heatsinking.
Continuously running the TPS74301 into thermal
shutdown degrades device reliability.
LAYOUT RECOMMENDATIONS AND POWER
DISSIPATION
An optimal layout can greatly improve transient
performance, PSRR, and noise. To minimize the
voltage droop on the input of the device during load
transients, the capacitance on IN and BIAS should
be connected as close as possible to the device.
This capacitance also minimizes the effects of
parasitic inductance and resistance of the input
source and can therefore improve stability. To
achieve optimal transient performance and accuracy,
the top side of R1 in Figure 26 should be connected
as close as possible to the load. If BIAS is connected
to IN, it is recommended to connect BIAS as close to
the sense point of the input supply as possible. This
connection minimizes the voltage droop on BIAS
during transient conditions and can improve the
turn-on response.
Knowing the device power dissipation and proper
sizing of the thermal plane that is connected to the
tab or pad is critical to avoiding thermal shutdown
and ensuring reliable operation. Power dissipation of
the device depends on input voltage and load
conditions, and can be calculated using Equation 2:
P D + ǒVIN * VOUTǓ I OUT
(2)
Thermal protection disables the output when the
junction temperature rises to approximately +155°C,
allowing the device to cool. When the junction
temperature cools to approximately +140°C, the
output circuitry is enabled. Depending on power
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SBVS065E – DECEMBER 2005 – REVISED MAY 2007
Power dissipation can be minimized and greater
efficiency can be achieved by using the lowest
possible input voltage necessary to achieve the
required output voltage regulation.
On both the QFN (RGW) and DDPAK (KTW)
packages, the primary conduction path for heat is
through the exposed pad or tab to the printed circuit
board (PCB). The pad or tab can be connected to
ground or be left floating; however, it should be
attached to an appropriate amount of copper PCB
area to ensure the device does not overheat. The
maximum junction-to-ambient thermal resistance
depends on the maximum ambient temperature,
maximum device junction temperature, and power
dissipation of the device, and can be calculated
using Equation 3:
()125OC * T A)
R qJA +
PD
(3)
Knowing the maximum RθJA and system air flow, the
minimum amount of PCB copper area needed for
appropriate heatsinking can be calculated using
Figure 30 through Figure 34.
PCB Top View
PCB Cross Section
TJ
RqJC
TC
RqCS
0.062in.
TS
RqSA
4-layer. 0.062” FR4
Vias are 0.012” diameter, plated
Top/Bottom layers are 2 oz. copper
Inner layers are 1 oz. copper
0.5in
TA
1.0in
RqJA = RqJC + RqCS + RqSA
2.0in
2
2
2
55
50
0 LFM
qJA (°C/W)
45
40
150 LFM
35
250 LFM
30
25
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
2
Area (in )
Figure 30. PCB Layout and Corresponding RθJA Data, Buried Thermal Plane, No Vias Under Thermal Pad
14
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SBVS065E – DECEMBER 2005 – REVISED MAY 2007
PCB Top View
PCB Cross Section
TJ
RqJC
TC
RqCS
0.062in.
TS
0.5in
RqSA
4-layer. 0.062” FR4
Vias are 0.012” diameter, plated
Top/Bottom layers are 2 oz. copper
Inner layers are 1 oz. copper
1.0in
TA
2.0in
2
2
2
RqJA = RqJC + RqCS + RqSA
50
45
0 LFM
qJA (°C/W)
40
150 LFM
35
30
250 LFM
25
20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2
Area (in )
Figure 31. PCB Layout and Corresponding RθJA Data, Buried Thermal Plane, Vias Under Thermal Pad
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TPS74301
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SBVS065E – DECEMBER 2005 – REVISED MAY 2007
PCB Top View
PCB Cross Section
TJ
RqJC
TC
RqCS
0.062in.
TS
4-layer. 0.062” FR4
Vias are 0.012” diameter, plated
Top/Bottom layers are 2 oz. copper
Inner layers are 1 oz. copper
0.5in
RqSA
1.0in
TA
2.0in
2
2
RqJA = RqJC + RqCS + RqSA
90
80
qJA (°C/W)
70
0 LFM
60
150 LFM
50
40
250 LFM
30
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2
Area (in )
Figure 32. PCB Layout and Corresponding RθJA Data, Top Layer Thermal Plane
16
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TPS74301
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SBVS065E – DECEMBER 2005 – REVISED MAY 2007
PCB Top View
PCB Cross Section
2.0in
2
TJ
RqJC
1.0in
2
TC
0.5in
RqCS
0.062in.
2
TS
RqSA
4-layer. 0.062” FR4
Vias are 0.012” diameter, plated
Top/Bottom layers are 2 oz. copper
Inner layers are 1 oz. copper
TA
RqJA = RqJC + RqCS + RqSA
35
0 LFM
qJA (°C/W)
30
25
20
15
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2
Area (in )
Figure 33. PCB Layout and Corresponding RθJA, Buried Thermal Plane
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TPS74301
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SBVS065E – DECEMBER 2005 – REVISED MAY 2007
PCB Top View
PCB Cross Section
2.0in
2
TJ
1.0in
RqJC
TC
2
0.5in
2
RqCS
0.062in.
TS
RqSA
4-layer. 0.062” FR4
Vias are 0.012” diameter, plated
Top/Bottom layers are 2 oz. copper
Inner layers are 1 oz. copper
TA
RqJA = RqJC + RqCS + RqSA
55
50
45
qJA (°C/W)
40
35
30
0 LFM
25
20
15
10
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
2
Area (in )
Figure 34. PCB Layout and Corresponding RθJA, Top Layer Thermal Plane
18
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS74301KTWR
ACTIVE
DDPAK
KTW
7
500
Green (RoHS &
no Sb/Br)
CU SN
Level-3-245C-168 HR
TPS74301KTWRG3
ACTIVE
DDPAK
KTW
7
500
Green (RoHS &
no Sb/Br)
CU SN
Level-3-245C-168 HR
TPS74301KTWT
ACTIVE
DDPAK
KTW
7
50
Green (RoHS &
no Sb/Br)
CU SN
Level-3-245C-168 HR
TPS74301KTWTG3
ACTIVE
DDPAK
KTW
7
50
Green (RoHS &
no Sb/Br)
CU SN
Level-3-245C-168 HR
TPS74301RGWR
ACTIVE
QFN
RGW
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS74301RGWRG4
ACTIVE
QFN
RGW
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS74301RGWT
ACTIVE
QFN
RGW
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS74301RGWTG4
ACTIVE
QFN
RGW
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
17-May-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS74301RGWR
RGW
20
MLA
330
12
5.3
5.3
1.5
8
12
PKGORN
T2TR-MS
P
TPS74301RGWT
RGW
20
MLA
180
12
5.3
5.3
1.5
8
12
PKGORN
T2TR-MS
P
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
TPS74301RGWR
RGW
20
MLA
346.0
346.0
29.0
TPS74301RGWT
RGW
20
MLA
190.0
212.7
31.75
Pack Materials-Page 2
Height (mm)
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Pack Materials-Page 3
MECHANICAL DATA
MPSF015 – AUGUST 2001
KTW (R-PSFM-G7)
PLASTIC FLANGE-MOUNT
0.410 (10,41)
0.385 (9,78)
0.304 (7,72)
–A–
0.006
–B–
0.303 (7,70)
0.297 (7,54)
0.0625 (1,587) H
0.055 (1,40)
0.0585 (1,485)
0.300 (7,62)
0.064 (1,63)
0.045 (1,14)
0.252 (6,40)
0.056 (1,42)
0.187 (4,75)
0.370 (9,40)
0.179 (4,55)
0.330 (8,38)
H
0.296 (7,52)
A
0.605 (15,37)
0.595 (15,11)
0.012 (0,305)
C
0.000 (0,00)
0.019 (0,48)
0.104 (2,64)
0.096 (2,44)
H
0.017 (0,43)
0.050 (1,27)
C
C
F
0.034 (0,86)
0.022 (0,57)
0.010 (0,25) M
B
0.026 (0,66)
0.014 (0,36)
0°~3°
AM C M
0.183 (4,65)
0.170 (4,32)
4201284/A 08/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Lead width and height dimensions apply to the
plated lead.
D. Leads are not allowed above the Datum B.
E. Stand–off height is measured from lead tip
with reference to Datum B.
F. Lead width dimension does not include dambar
protrusion. Allowable dambar protrusion shall not
cause the lead width to exceed the maximum
dimension by more than 0.003”.
G. Cross–hatch indicates exposed metal surface.
H. Falls within JEDEC MO–169 with the exception
of the dimensions indicated.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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representatives against any damages arising out of the use of TI products in such safety-critical applications.
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Telephony
www.ti.com/telephony
Low Power
Wireless
www.ti.com/lpw
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
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