OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com UNITY-GAIN STABLE, LOW-NOISE, VOLTAGE-FEEDBACK OPERATIONAL AMPLIFIER Check for Samples: OPA820-HT FEATURES 1 • • • • SUPPORTS EXTREME TEMPERATURE APPLICATIONS • • • • • • • • APPLICATIONS • • Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Extreme (–55°C/210°C) Temperature Range (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability Texas Instruments high temperature products utilize highly optimized silicon (die) solutions with design and process enhancements to maximize performance over extended temperatures. All devices are characterized and qualified for 1000 hour continuous operating life at maximum rated temperature. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 • High Bandwidth (240 MHz at 25°C and 100 MHz at 210°C, G = 2) High Output Current (±110 mA at 25°C and 50 mA at 210°C) Low Input Noise (2.5 nV/√Hz at 25°C and 4.5 nV/√Hzat 210°C) Low Supply Current (5.6 mA at 25°C and 6.8 mA at 210°C) Flexible Supply Voltage: – Dual ±2.5 V to ±5 V – Single +5 V Downhole Drilling Extreme Temperature Application (1) Custom temperature ranges available DESCRIPTION The OPA820 provides a wideband, unity-gain stable, voltage-feedback amplifier with a very low input noise voltage and high output current using a low 6.8-mA supply current. The OPA820 complements this high-speed operation with excellent DC precision in a low-power device. A worst-case input offset voltage of ±3.5 mV and an offset current of ±700 nA give excellent absolute DC precision for pulse amplifier applications. Minimal input and output voltage swing headroom allow the OPA820 to operate on a single 5-V supply with > 2VPP output swing. While not a rail-to-rail (RR) output, this swing will support most emerging analog-to-digital converter (ADC) input ranges with lower power and noise than typical RR output op amps. The OPA820 is characterized for operation from –55°C to 210°C. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. BARE DIE INFORMATION DIE THICKNESS BACKSIDE FINISH BACKSIDE POTENTIAL BOND PAD METALLIZATION COMPOSITION BOND PAD THICKNESS 15 mils. Silicon with backgrind Floating TiW/AlCu (0.5%) 1100 nm 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 1094µm CIC60311 69µm 0 654µm 45µm 0 Table 1. Bond Pad Coordinates in Microns DISCRIPTION PAD NUMBER X MIN Y MIN X MAX Y MAX Inverting Input 1 27 439 125 537 NonInverting Input 2 27 125 125 125 Output 3 831 27 929 125 -VS 4 831 233 929 331 +VS 5 831 439 929 537 ORDERING INFORMATION (1) TA –55°C to 210°C (1) (2) 2 PACKAGE (2) KGD (bare die) ORDERABLE PART NUMBER TOP-SIDE MARKING OPA820SKD3 NA For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). UNIT Supply voltage, VS– to VS+ ±6.5 V Differential input voltage, VID ±1.2 V Input common-mode voltage range ±VS V Maximum continuous operating current at 210°C 50 mA Internal power dissipation See Thermal Characteristic specifications 210 °C Operating Free-air Temperature Range, TA –55 to 210 °C Storage Temperature Range, TSTG –65 to 210 °C Lead temperature (soldering, 10 s) 300 °C Junction temperature, TJ 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. xxxx Estimated Life (Hrs) 100000 10000 1000 100 160 170 180 190 200 210 220 Continuous TJ (°C) A. See datasheet for absolute maximum and minimum recommended operating conditions. B. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life). C. The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the dominant failure mechanism affecting device wear out for the specific device process and design characteristics. Figure 1. OPA820-HT Operating Life Derating Chart Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT 3 OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: VS = ±5 V RF = 402 Ω, RL = 100 Ω, and G = 2, unless otherwise noted. -55°C to 125°C PARAMETER CONDITIONS MIN TYP 210°C MAX MIN TYP MAX UNIT TEST LEVEL (1) AC PERFORMANCE Small-Signal Bandwidth Gain Bandwidth Product Bandwidth for 0.1dB Gain Flatness G = 1, VO = 0.1VPP, RF = 0 Ω 800 G = 2, VO = 0.1VPP 240 G = 10, VO = 0.1VPP 30 G ≥ 20 150 100 270 202 MHz C MHz C MHz C MHz C MHz C 38 Peaking at a Gain of +1 VO = 0.1VPP, RF = 0 Ω 0.5 dB C Large-Signal Bandwidth G = 2, VO = 2VPP 85 MHz C G = 2, 2-V Step 240 185 V/µs C G = 2, VO = 0.2-V Step 10.5 11.5 ns C 22 28 18 25 ns C Slew Rate 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 G = 2, VO = 0.1VPP Rise and Fall Time Settling Time to 0.02% 0.1% G = 2, VO = 2-V Step Harmonic Distortion G = 2, f = 1 MHz, VO = 2VPP 2nd harmonic RL = 200 Ω -85 -79 -77 dBc C RL = 500 Ω -90 -81 -90 dBc C RL = 200 Ω -95 -88 -78 dBc C RL = 500 Ω -110 -100 -98 dBc C Input Voltage Noise f > 100 kHz 2.5 2.9 4.5 nV/√Hz C Input Current Noise f > 100 kHz 1.7 3 G = 2, PAL, VO = 1.4VPP, RL = 150 Ω G = 2, PAL, VO = 1.4VPP, RL = 150 Ω 3rd harmonic Differential Gain Differential Phase pA/√Hz C 0.01 % C 0.03 ° C dB A mV A DC PERFORMANCE (2) Open-Loop Voltage Gain (AOL) VO = 0 V, Input-Referred 59 62 52 VCM = 0 V ±1.8 VCM = 0 V 7 7 μV/°C C VCM = 0 V 39 39 μA C VCM = 0 V 50 50 nA/°C C Input Offset Current VCM = 0 V ±700 ±700 nA C Inverting Input Bias Current Drift VCM = 0 V 50 50 nA/°C C Input Offset Voltage Average input offset voltage drift Input Bias Current Average input bias current drift (1) (2) 4 ±3.5 57 ±1.8 ±3.5 Test levels: (A) 100% tested. (B) Limits set by characterization and simulation. (C) Typical value only for information. Current is considered positive out-of-node. VCM is the input common-mode voltage. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: VS = ±5 V (continued) RF = 402 Ω, RL = 100 Ω, and G = 2, unless otherwise noted. -55°C to 125°C PARAMETER CONDITIONS MIN TYP 210°C MAX MIN TYP MAX UNIT TEST LEVEL (1) INPUT Common-Mode Input Range (CMIR) (3) Common-Mode Rejection Ratio VCM = 0 V, Input-Referred ±3.9 ±3.2 V A 73 71 dB A Input Impedance VCM = 0 V 18 || 0.8 kΩ || pf Common mode VCM = 0 V 6 || 1 MΩ || pf OUTPUT 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Differential mode Output Voltage Swing Short-Circuit Output Current Closed-Loop Output Impedance No Load ±3.5 ±3.7 ±3.4 RL = 100 Ω ±3.5 ±3.6 ±3.4 Output Shorted to Ground ±90 G = 2, f ≤ 100 kHz 0.04 ±50 C V A mA C Ω C POWER SUPPLY Maximum Operating Voltage Maximum Quiescent Current VS = ±5 V Minimum Quiescent Current VS = ±5 V 5 Input Referred 62 Power-Supply Rejection Ratio (±PSRR) (3) ±5 ±5 6.6 6.8 V A mA A 5 mA A 61 dB A Tested < 3 dB below minimum specified CMRR at ±CMIR limits. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT 5 OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: VS = 5 V RF = 402 Ω, RL = 100 Ω, and G = 2, unless otherwise noted. -55°C to 125°C PARAMETER CONDITIONS MIN TYP 210°C MAX MIN TYP MAX UNIT TEST LEVEL (1) MHz C MHz C MHz C MHz C MHz C AC PERFORMANCE Small-Signal Bandwidth Gain Bandwidth Product Bandwidth for 0.1dB Gain Flatness G = 1, VO = 0.1VPP, RF = 0 Ω 800 G = 2, VO = 0.1VPP 240 G = 10, VO = 0.1VPP 30 G ≥ 20 150 100 270 202 38 Peaking at a Gain of +1 VO = 0.1VPP, RF = 0 Ω 0.5 dB C Large-Signal Bandwidth G = 2, VO = 2VPP 85 MHz C G = 2, 2-V Step 240 185 V/µs C G = 2, VO = 0.2-V Step 10.5 11.5 ns C 22 28 18 24 ns C Slew Rate 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 G = 2, VO = 0.1VPP Rise and Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion G = 2, f = 1 MHz, VO = 2VPP 2nd harmonic 3rd harmonic Input Voltage Noise Input Current Noise Differential Gain Differential Phase DC PERFORMANCE G = 2, VO = 2-V Step RL = 200 Ω -85 -76 dBc C RL = 500 Ω -90 -75 dBc C RL = 200 Ω -95 -92 dBc C RL = 500 Ω -110 -91 dBc C f > 100 kHz 2.5 4.5 nV/√Hz C f > 100 kHz 1.7 pA/√Hz C G = 2, PAL, VO = 1.4VPP, RL = 150 Ω 0.01 % C G = 2, PAL, VO = 1.4VPP, RL = 150 Ω 0.03 ° C dB A mV A (2) Open-Loop Voltage Gain (AOL) Input Offset Voltage VO = 0 V, Input-Referred 60 65 58 VCM = 0 V 1.8 VCM = 0 V 7 7 μV/°C C VCM = 0 V 39 39 μA C VCM = 0 V 50 50 nA/°C C Input Offset Current VCM = 0 V ±700 ±700 nA C Inverting Input Bias Current Drift VCM = 0 V 50 50 nA/°C C Average input offset voltage drift Input Bias Current Average input bias current drift (1) (2) 6 3.5 64 1.8 3.5 Test levels: (A) 100% tested. (B) Limits set by characterization and simulation. (C) Typical value only for information. Current is considered positive out-of-node. VCM is the input common-mode voltage. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: VS = 5 V (continued) RF = 402 Ω, RL = 100 Ω, and G = 2, unless otherwise noted. -55°C to 125°C PARAMETER CONDITIONS MIN TYP 210°C MAX MIN TYP MAX UNIT TEST LEVEL (1) INPUT Common-Mode Input Range (CMIR) (3) Common-Mode Rejection VCM = 0 V, Input-Referred 3.9 3.2 V A 72 70 dB A Input Impedance Differential mode OUTPUT VCM = 0 V 18 || 0.8 kΩ || pf 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Common mode Output Voltage Swing Short-Circuit Output Current Closed-Loop Output Impedance VCM = 0 V 6 || 1.0 MΩ || pf No Load 3.4 3.7 3.4 RL = 100 Ω 3.4 3.6 3.4 Output Shorted to Ground ±60 G = 2, f ≤ 100 kHz 0.04 ±37 C V A mA C Ω C POWER SUPPLY Maximum Operating Voltage Maximum Quiescent Current VS = ±5 V Minimum Quiescent Current VS = ±5 V 3.8 Input Referred 62 Power-Supply Rejection Ratio (±PSRR) (3) 5 5 V A 5.8 6.5 mA A 4 mA A 61 dB C Tested < 3 dB below minimum specified CMRR at ±CMIR limits. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT 7 OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS: VS = ±5 V RF = 402 Ω, RL = 100 Ω, G = 2 and TA = 25°C unless otherwise noted. NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE 3 0 G = −1 0 Normalized Gain (dB) G = +5 −3 G = +2 −6 G = +10 −9 −12 VO = 0.1VPP RL = 100 W See Figure 1 −15 −18 G = −2 −3 G = −5 −6 −9 G = −10 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 −12 VO = 0.1VPP RL = 100 W See Figure 2 −15 −18 1M 10M 100M 1G 1 10 Frequency (Hz) −3 0 Gain (dB) VO = 1VPP VO = 2VPP −3 VO = 4VPP VO = 1VPP −6 VO = 2VPP −9 VO = 4VPP −12 −6 G = +2 RL = 100 Ω See Figure 1 −9 G = −1 RL = 100 W See Figure 2 −15 −18 −12 1 10 100 500 1 10 0.1 0 −0.1 −0.2 −0.3 1.5 1.0 0.5 Small Signal ± 100 mV Left Scale 0 −0.5 −1.0 G = +2 See Figure 1 −1.5 −2.0 −0.4 Small−Signal Output Voltage (100mV/div) 0.2 Large Signal ± 1V Right Scale 0.4 0.3 G = −1 See Figure 2 2.0 1.5 0.2 1.0 0.1 0.5 0 Small Signal ± 100 mV Left Scale −0.1 −0.2 −0.3 Large Signal ± 1V Right Scale 0 −0.5 −1.0 −1.5 −2.0 −0.4 Time (10 ns/div) 8 500 INVERTING PULSE RESPONSE 2.0 Large−Signal Output Voltage (500mV/div) Small−Signal Output Voltage (100mV/div) NONINVERTING PULSE RESPONSE 0.3 100 Frequency (MHz) Frequency (MHz) 0.4 VO = 0.5VPP 0 3 Gain (dB) 3 VO = 0.5VPP 6 500 INVERTING LARGE−SIGNAL FREQUENCY RESPONSE NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE 9 100 Frequency (MHz) Large−Signal Output Voltage (500mV/div) Normalized Gain (dB) INVERTING SMALL−SIGNAL FREQUENCY RESPONSE 3 G = +1 RF = 0 W Time (10ns/div) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS: VS = ±5 V (continued) RF = 402 Ω, RL = 100 Ω, G = 2 and TA = 25°C unless otherwise noted. 1MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE HARMONIC DISTORTION vs LOAD RESISTANCE −75 −75 Harmonic Distortion (dBc) f = 1MHz VO = 2VPP G = +2V/V −80 2nd−Harmonic −85 −90 3rd−Harmonic −95 See Figure 1 −100 100 −80 2nd−Harmonic −85 −90 3rd−Harmonic −95 −100 2.5 1k 3.0 3.5 −80 −85 −90 6.0 −85 −90 2nd−Harmonic −95 −100 3rd−Harmonic −105 −100 See Figure 1 See Figure 1 −105 0.1 1 −110 0.1 10 1 HARMONIC DISTORTION vs INVERTING GAIN HARMONIC DISTORTION vs NONINVERTING GAIN −70 f = 1MHz RL = 200 W VO = 2VPP −75 −80 −85 −90 2nd−Harmonic Harmonic Distortion (dBc) −70 10 Output Voltage (VPP) Frequency (MHz) Harmonic Distortion (dBc) 5.5 f = 1MHz RL = 200 W G = +2V/V −80 2nd−Harmonic 3rd−Harmonic −95 5.0 HARMONIC DISTORTION vs OUTPUT VOLTAGE Harmonic Distortion (dBc) Harmonic Distortion (dBc) −75 4.5 −75 VO = 2VPP RL = 100 W G = +2V/V −70 4.0 Supply Voltage (±VS) HARMONIC DISTORTION vs FREQUENCY −65 See Figure 1 −105 Resistance (Ω) −60 VO = 2VPP RL = 200 W G = +2V/V 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Harmonic Distortion (dBc) −70 3rd−Harmonic −95 −100 −105 f = 1MHz RL = 200 W VO = 2VPP −75 2nd−Harmonic −80 −85 3rd−Harmonic −90 −95 See Figure 2 See Figure 1 −100 −110 1 10 1 10 Gain ( |V/V| ) Gain (V/V) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT 9 OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS: VS = ±5 V (continued) RF = 402 Ω, RL = 100 Ω, G = 2 and TA = 25°C unless otherwise noted. TWO−TONE, 3RD−ORDER INTERMODULATION INTERCEPT INPUT VOLTAGE AND CURRENT NOISE 50 100 PI 2 00 W Intercept Point (+dBm) 10 Voltage Noise (2.5nV/√Hz) PO O P A 82 0 50 W 40 40 2 W 35 40 2 W 30 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Voltage Noise (nV/√Hz) Current Noise (pA/√Hz) 45 25 20 Current Noise (1.7pA/√Hz) 10 100 1k 10k 100k 1M 15 10M 0 5 10 Frequency (Hz) Normalized Gain to Capacitive Load (dB) RS (Ω) 0dB Peaking Targeted 10 1 1 10 100 8 5 CL = 47pF 4 CL = 100pF 3 2 RS VI 1 50Ω CL 0 1kΩ(1) 4 02Ω NOTE: (1) 1kΩ is o ptional. 402Ω −2 −3 1 10 100 400 Frequency (MHz) OPEN−LOOP GAIN AND PHASE 80 0 70 70 60 Open−Loop Gain (dB) Common−Mode Rejection Ratio (dB) Power−Supply Rejection Ratio (dB) VO OPA 820 −1 1000 CMRR +PSRR 50 40 −20 20 log (AOL) 60 −40 50 −60 40 30 −80 ∠A OL −100 20 −120 10 −140 10 0 −160 0 −10 100 30 −PSRR 20 1k 10k 100k 1M 10M 100M −180 1k Frequency (Hz) 10 30 CL = 22pF 6 CMRR AND PSRR vs FREQUENCY 80 25 CL = 10pF 7 Capacitive Load (pF) 90 20 FREQUENCY RESPONSE vs CAPACITIVE LOAD RECOMMENDED RS vs CAPACITIVE LOAD 100 15 Frequency (MHz) Open−Loop Phase (°) 1 Submit Documentation Feedback 10k 100k 1M Frequency (Hz) 10M 100M 1G Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS: VS = ±5 V (continued) RF = 402 Ω, RL = 100 Ω, G = 2 and TA = 25°C unless otherwise noted. OUTPUT VOLTAGE AND CURRENT LIMITATIONS 4 Output Current Power Limit Limit 3 10 1 Output Impedance (Ω) RL = 100Ω 2 VO (V) CLOSED−LOOP OUTPUT IMPEDANCE vs FREQUENCY 1W Internal RL = 25Ω 0 RL = 50Ω −1 −3 Output Current −4 Limit −5 −150 0.1 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 −2 1 1W Internal Power Limit 0.01 −100 −50 0 50 100 150 1k 10k 100k IO (mA) 4 Input Right Scale 4 2 2 1 Output Left Scale 0 0 −2 −1 −4 −2 RL = 100Ω G = +2V/V See Figure 1 −6 −8 −3 Output Voltage (1V/div) 3 Input Voltage (1V/div) Output Voltage (2V/div) 6 10M 100M INVERTING OVERDRIVE RECOVERY NONINVERTING OVERDRIVE RECOVERY 8 1M Frequency (Hz) 5 5 4 4 3 2 1 1 0 0 Output Left Scale −1 −2 −1 −2 RL = 100Ω G = −1V/V See Figure 2 −3 −4 −4 3 Input Right Scale 2 −3 −4 −5 Time (40ns/div) Input Voltage (1V/div) 5 −5 Time (40ns/div) COMMON−MODE INPUT RANGE AND OUTPUT SWING vs SUPPLY VOLTAGE 6 COMPOSITE VIDEO dG/dP G = +2V/V 0.18 dG Negative Video 0.36 5 0.32 0.14 0.28 0.12 0.24 0.10 0.20 0.08 0.06 0.04 0.16 dP Negative Video dP Positive Video 0.12 0.08 0.02 Differential Phase ( °) Differential Gain (%) 0.16 0.40 Voltage Range (V) 0.20 +VIN 4 −VIN 3 +VOUT 2 −VOUT 1 0.04 dG Positive Video 0 1 2 3 0 4 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Supply Voltage (±VS ) Video Loads Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT 11 OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS: VS = ±5 V (continued) RF = 402 Ω, RL = 100 Ω, G = 2 and TA = 25°C unless otherwise noted. TYPICAL INPUT OFFSET VOLTAGE DISTRIBUTION COMMON−MODE AND DIFFERENTIAL INPUT IMPEDANCE 10M 2500 Mean = −30µV Standard Deviation = 80µV Total Count = 6115 Common−Mode Input Impedance Count 1M 100k 1500 1000 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Input Impedance (Ω) 2000 Differential Input Impedance 500 10k 100 1k 10k 100k 1M 10M −730 −660 −580 −510 −440 −370 −290 −220 −150 −70 0 70 150 220 290 370 440 510 580 660 730 0 1k 100M Frequency (Hz) Input Offset Voltage (µV) TYPICAL INPUT OFFSET CURRENT DISTRIBUTION 2000 1800 1600 Mean = 26nA Standard Deviation = 57nA Total Count = 6115 Count 1400 1200 1000 800 600 400 200 −380 −342 −304 −266 −228 −190 −152 −114 −76 −38 0 38 76 114 152 190 228 266 304 342 380 0 Input Offset Current (nA) 12 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS: VS = 5 V RF = 402 Ω, RL = 100 Ω, G = 2 and TA = 25°C unless otherwise noted. NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE 3 INVERTING SMALL−SIGNAL FREQUENCY RESPONSE 3 G = +1 G = −1 0 Normalized Gain (dB) G = +2 −3 G = +5 −6 G = +10 −9 −12 VO = 0.1VPP RL = 100Ω See Figure 3 −15 −18 G = −2 −3 G = −5 −6 G = −10 −9 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 −12 VO = 0.1VPP RL = 100Ω See Figure 4 −15 −18 1M 10M 100M 1G 1 10 Frequency (Hz) VO = 1VPP 3 −3 VO = 2VPP 0 VO = 4VPP −3 VO = 1VPP −6 VO = 2VPP −9 VO = 4VPP −12 −6 G = +2V/V RL = 100Ω See Figure 3 −9 G = −1 RL = 100Ω See Figure 4 −15 −18 −12 1 10 100 600 1 10 2.6 2.5 2.4 2.3 2.2 4.0 3.5 3.0 Small Signal ± 100mV Left Scale 2.5 2.0 1.5 G = +2 See Figure 3 1.0 2.1 0.5 Small−Signal Output Voltage (100mV/div) 2.7 Large Signal ± 1V Right Scale 500 INVERTING PULSE RESPONSE 4.5 Large−Signal Output Voltage (500mV/div) Small−Signal Output Voltage (100mV/div) NONINVERTING PULSE RESPONSE 2.8 100 Frequency (MHz) Frequency (MHz) 2.9 VO = 0.5VPP 0 Gain (dB) Normalized Gain (dB) 3 VO = 0.5VPP 6 500 INVERTING LARGE−SIGNAL FREQUENCY RESPONSE NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE 9 100 Frequency (MHz) 2.9 2.8 G = −1 See Figure 4 4.5 4.0 2.7 3.5 2.6 3.0 2.5 Small Signal± 100mV Left Scale 2.4 2.3 2.2 Large Signal ± 1V Right Scale 2.1 Time (10ns/div) 2.5 2.0 1.5 1.0 0.5 Large−Signal Output Voltage (500mV/div) Normalized Gain (dB) 0 Time (10ns/div) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT 13 OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS: VS = 5 V (continued) RF = 402 Ω, RL = 100 Ω, G = 2 and TA = 25°C unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs LOAD RESISTANCE −75 −60 −85 −90 −95 3rd−Harmonic −100 G = +2V/V RL = 200Ω VO = 2VPP −70 −80 −90 See Figure 3 −110 1k 0.1 1 HARMONIC DISTORTION vs OUTPUT VOLTAGE −80 −90 HARMONIC DISTORTION vs NONINVERTING GAIN −60 2nd−Harmonic Harmonic Distortion (dBc) Harmonic Distortion (dBc) VO = 2VPP f = 1MHz G = +2V/V RL = 200Ω 3rd−Harmonic −100 10 Frequency (MHz) Resistance (Ω) −70 3rd−Harmonic −100 See Figure 3 −105 100 2nd−Harmonic 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Harmonic Distortion (dBc) Harmonic Distortion (dBc) f = 1MHz VO = 2VPP G = +2V/V 2nd−Harmonic −80 f = 1MHz RL = 200Ω VO = 2VPP −70 2nd−Harmonic −80 −90 3rd−Harmonic −100 See Figure 3 −110 0.1 1 10 1 Output Voltage Swing (VPP) −70 TWO−TONE, 3RD−ORDER INTERMODULATION INTERCEPT 40 f = 1MHz RL = 200Ω VO = 2VPP −75 +5V 0.01µF −85 Intercept Point (+dBm) 2nd−Harmonic −80 3rd−Harmonic −90 −95 10 Gain (V/V) HARMONIC DISTORTION vs INVERTING GAIN Harmonic Distortion (dBc) See Figure 3 −110 806Ω PI 35 57.6Ω 806Ω 30 PO OPA820 200Ω 402Ω 402Ω 0.01µF 25 20 See Figure 4 −100 1 10 Gain (| V/V| ) 14 15 0 5 10 15 20 25 30 Frequency (MHz) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS: VS = 5 V (continued) RF = 402 Ω, RL = 100 Ω, G = 2 and TA = 25°C unless otherwise noted. FREQUENCY RESPONSE vs CAPACITIVE LOAD RS (Ω) 0dB Peaking Targeted 10 1 8 CL = 10pF 7 6 5 CL = 22pF 4 CL = 47pF 3 CL = 100pF 2 +5V 1 0.01µF 10 100 RS VI 57.6Ω 0 0.01µF −3 1 10 1000 500 0 100 300 Frequency (MHz) TYPICAL INPUT OFFSET CURRENT DISTRIBUTION 2000 Mean = −490µV Standard Deviation = 90µV Total Count = 6115 1800 1600 Mean = 43nA Standard Deviation = 50nA Total Count = 6115 1400 1200 1000 800 600 400 200 0 −380 −342 −304 −266 −228 −190 −152 −114 −76 −38 0 38 76 114 152 190 228 266 304 342 380 1500 NOTE: (1) 1kΩis optional. 402Ω −2 1000 Count 2000 1kΩ(1) −1.08 −0.97 −0.86 −0.76 −0.65 −0.54 −0.43 −0.32 −0.22 −0.11 0 0.11 0.22 0.32 0.43 0.54 0.65 0.76 0.86 0.97 1.08 Count 2500 VO OPA820 CL −1 TYPICAL INPUT OFFSET VOLTAGE DISTRIBUTION 3000 806Ω 402Ω Capacitive Load (pF) 3500 806Ω 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 1 Normalized Gain to Capacitive Load (dB) RECOMMENDED RS vs CAPACITIVE LOAD 100 Input Offset Voltage (mV) Input Offset Current (nA) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT 15 OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com APPLICATION INFORMATION Wideband Voltage-Feedback Operation The combination of speed and dynamic range offered by the OPA820 is easily achieved in a wide variety of application circuits, providing that simple principles of good design practice are observed. For example, good power-supply decoupling, as shown in Figure 2, is essential to achieve the lowest possible harmonic distortion and smooth frequency response. Proper PC board layout and careful component selection will maximize the performance of the OPA820 in all applications, as discussed in the following sections of this data sheet. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Figure 2 shows the gain of +2 configuration used as the basis for most of the typical characteristics. Most of the curves were characterized using signal sources with 50-Ω driving impedance and with measurement equipment presenting 50-Ω load impedance. In Figure 2, the 50-Ω shunt resistor at the VI terminal matches the source impedance of the test generator while the 50-Ω series resistor at the VO terminal provides a matching resistor for the measurement equipment load. Generally, data sheet specifications refer to the voltage swings at the output pin (VO in Figure 2). The 100-Ω load, combined with the 804-Ω total feedback network load, presents the OPA820 with an effective load of approximately 90 Ω in Figure 2. +5V +VS + 0.1µF 2.2µF 50Ω Source VIN RS 50Ω Load 50Ω VO 50Ω OPA820 RF 402Ω RG 402Ω 0.1µF 2.2µF + −VS −5V Figure 2. Gain of +2, High-Frequency Application and Characterization Circuit 16 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com Wideband Inverting Operation Operating the OPA820 as an inverting amplifier has several benefits and is particularly useful when a matched 50-Ω source and input impedance is required. Figure 3 shows the inverting gain of −1 circuit used as the basis of the inverting mode typical characteristics. +5V + 0.1µF 2.2µF 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 RT 205Ω 0.01µF 50Ω Source 50Ω VO 50Ω Load OPA820 RF 402Ω RG 402Ω VI RM 57.6Ω + 0.1µF 2.2µF −5V Figure 3. Inverting G = −1 Specifications and Test Circuit In the inverting case, just the feedback resistor appears as part of the total output load in parallel with the actual load. For the 100-Ω load used in the typical characteristics, this gives a total load of 80 Ω in this inverting configuration. The gain resistor is set to get the desired gain (in this case 402 Ω for a gain of −1) while an additional input matching resistor (RM) can be used to set the total input impedance equal to the source if desired. In this case, RM = 57.6 Ω in parallel with the 402-Ω gain setting resistor gives a matched input impedance of 50 Ω. This matching is only needed when the input needs to be matched to a source impedance, as in the characterization testing done using the circuit of Figure 3. The OPA820 offers extremely good DC accuracy as well as low noise and distortion. To take full advantage of that DC precision, the total DC impedance looking out of each of the input nodes must be matched to get bias current cancellation. For the circuit of Figure 32, this requires the 205-Ω resistor shown to ground on the noninverting input. The calculation for this resistor includes a DC-coupled 50-Ω source impedance along with RG and RM. Although this resistor will provide cancellation for the bias current, it must be well decoupled (0.01 μF in Figure 3) to filter the noise contribution of the resistor and the input current noise. As the required RG resistor approaches 50 Ω at higher gains, the bandwidth for the circuit in Figure 3 will far exceed the bandwidth at that same gain magnitude for the noninverting circuit of Figure 2. This occurs due to the lower noise gain for the circuit of Figure 3 when the 50-Ω source impedance is included in the analysis. For instance, at a signal gain of −10 (RG = 50 Ω, RM = open, RF = 499 Ω) the noise gain for the circuit of Figure 3 will be 1 + 499 Ω/(50 Ω + 50 Ω) = 6 as a result of adding the 50-Ω source in the noise gain equation. This gives considerable higher bandwidth than the noninverting gain of +10. Using the 240-MHz gain bandwidth product for the OPA820, an inverting gain of −10 from a 50-Ω source to a 50-Ω RG gives 55-MHz bandwidth, whereas the noninverting gain of +10 gives 30 MHz. Wideband Single-Supply Operation Figure 4 shows the AC-coupled, single 5-V supply, gain of +2 V/V circuit configuration used as a basis for the 5 V only Electrical and Typical Characteristics. The key requirement for single-supply operation is to maintain input and output signal swings within the useable voltage ranges at both the input and the output. The circuit of Figure 4 establishes an input midpoint bias using a simple resistive divider from the 5-V supply (two 806-Ω resistors) to the noninverting input. The input signal is then AC-coupled into this midpoint voltage bias. The input voltage can swing to within 0.9 V of the negative supply and 0.5 V of the positive supply, giving a 3.6VPP input Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT 17 OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com signal range. The input impedance matching resistor (57.6 Ω) used in Figure 4 is adjusted to give a 50-Ω input match when the parallel combination of the biasing divider network is included. The gain resistor (RG) is AC-coupled, giving the circuit a DC gain of +1. This puts the input DC bias voltage (2.5 V) on the output as well. On a single 5-V supply, the output voltage can swing to within 1.3 V of either supply pin while delivering more than 80-mA output current giving 2.4-V output swing into 100 Ω (5.6-dBm maximum at the matched load). Figure 5 shows the AC-coupled, single 5-V supply, gain of −1 V/V circuit configuration used as a basis for the 5 V only Typical Characteristic curves. In this case, the midpoint DC bias on the noninverting input is also decoupled with an additional 0.01-μF decoupling capacitor. This reduces the source impedance at higher frequencies for the noninverting input bias current noise. This 2.5-V bias on the noninverting input pin appears on the inverting input pin and, since RG is DC blocked by the input capacitor, will also appear at the output pin. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 The single-supply test circuits of Figure 4 and Figure 4 show 5-V operation. These same circuits can be used over a singlesupply range of 5 V to 12 V. Operating on a single 12-V supply, with the Absolute Maximum Supply voltage specification of 13 V, gives adequate design margin for the typical ±5% supply tolerance. +5V +VS + 0.1µF 50Ω Source 0.01µF 6.8µF 806Ω DIS VI 57.6Ω VO OPA820 806Ω 100Ω VS/2 RF 402Ω RG 402Ω 0.01µF Figure 4. AC-Coupled, G = +2 V/V, Single-Supply Specifications and Test Circuit +5V +VS + 0.1µF 6.8µF 806Ω DIS 0.01µF 806Ω RG 0.01µF 402Ω OPA820 VO 100Ω VS/2 RF 402Ω VI Figure 5. AC-Coupled, G = −1 V/V, Single-Supply Specifications and Test Circuit Buffering High-Performance ADCs To achieve full performance from a high dynamic range ADC, considerable care must be exercised in the design of the input amplifier interface circuit. The example circuit on the front page shows a typical AC-coupled interface to a very high dynamic range converter. This AC-coupled example allows the OPA820 to be operated using a signal range that swings symmetrically around ground (0 V). The 2VPP swing is then level-shifted through the blocking capacitor to a midscale reference level, which is created by a well-decoupled resistive divider off the converter’s internal reference voltages. To have a negligible effect (1 dB) on the rated spurious-free dynamic range (SFDR) of the converter, the amplifier’s SFDR should be at least 18 dB greater than the converter. The OPA820 has minimal effect on the rated distortion of the ADS850, given its 79-dB SFDR at 2VPP, 1 MHz. The 18 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com > 90-dB (< 1MHz) SFDR for the OPA820 in this configuration implies a < 3-dB degradation (for the system) from the converter’s specification. For further SFDR improvement with the OPA820, a differential configuration is suggested. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Successful application of the OPA820 for ADC driving requires careful selection of the series resistor at the amplifier output, along with the additional shunt capacitor at the ADC input. To some extent, selection of this RC network will be determined empirically for each converter. Many high performance CMOS ADCs, such as the ADS850, perform better with the shunt capacitor at the input pin. This capacitor provides low source impedance for the transient currents produced by the sampling process. Improved SFDR is often obtained by adding this external capacitor, whose value is often recommended in this converter data sheet. The external capacitor, in combination with the built-in capacitance of the ADC input, presents a significant capacitive load to the OPA820. Without a series isolation resistor, an undesirable peaking or loss of stability in the amplifier may result. Since the DC bias current of the CMOS ADC input is negligible, the resistor has no effect on overall gain or offset accuracy. Refer to the typical characteristic RS vs Capacitive Load to obtain a good starting value for the series resistor. This will ensure flat frequency response to the ADC input. Increasing the external capacitor value will allow the series resistor to be reduced. Intentionally bandlimiting using this RC network can also be used to limit noise at the converter input. Video Line Driving Most video distribution systems are designed with 75-Ω series resistors to drive a matched 75-Ω cable. In order to deliver a net gain of 1 to the 75-Ω matched load, the amplifier is typically set up for a voltage gain of +2, compensating for the 6-dB attenuation of the voltage divider formed by the series and shunt 75-Ω resistors at either end of the cable. The circuit of Figure 2 applies to this requirement if all references to 50-Ω resistors are replaced by 75-Ω values. Often, the amplifier gain is further increased to 2.2, which recovers the additional DC loss of a typical long cable run. This change would require the gain resistor (RG) in Figure 2 to be reduced from 402 Ω to 335 Ω. In either case, both the gain flatness and the differential gain/phase performance of the OPA820 will provide exceptional results in video distribution applications. Differential gain and phase measure the change in overall small-signal gain and phase for the color sub-carrier frequency (3.58 MHz in NTSC systems) versus changes in the large-signal output level (which represents luminance information in a composite video signal). The OPA820, with the typical 150-Ω load of a single matched video cable, shows less than 0.01%/0.01° differential gain/phase errors over the standard luminance range for a positive video (negative sync) signal. Similar performance would be observed for multiple video signals, as shown in Figure 6. 335Ω 402Ω 75Ω Transmission Line 75Ω OPA820 Video Input VOUT 75Ω 75Ω 75Ω VOUT 75Ω 75Ω VOUT High output current drive capability allows three back−terminated 75Ωtransmission lines to be simultaneously driven. 75Ω Figure 6. Video Distribution Amplifier Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT 19 OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com Single Operational Amplifier Differential Amplifier The voltage-feedback architecture of the OPA820, with its high common-mode rejection ratio (CMRR), will provide exceptional performance in differential amplifier configurations. Figure 7 shows a typical configuration. The starting point for this design is the selection of the RF value in the range of 200 Ω to 2 kΩ. Lower values reduce the required RG, increasing the load on the V2 source and on the OPA820 output. Higher values increase output noise as well as the effects of parasitic board and device capacitances. Following the selection of RF, RG must be set to achieve the desired inverting gain for V2. Remember that the bandwidth will be set approximately by the gain bandwidth product (GBP) divided by the noise gain (1 + RF/RG). For accurate differential operation (that is, good CMRR), the ratio R2/R1 must be set equal to RF/RG. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 +5V Power−supply decoupling not shown. R1 V1 50Ω R2 OPA820 RG RF VO = RF (V − RG 1 V2) when R2 RF = R1 RG V2 −5V Figure 7. High-Speed, Single Differential Amplifier Usually, it is best to set the absolute values of R2 and R1 equal to RF and RG, respectively; this equalizes the divider resistances and cancels the effect of input bias currents. However, it is sometimes useful to scale the values of R2 and R1 in order to adjust the loading on the driving source, V1. In most cases, the achievable low-frequency CMRR will be limited by the accuracy of the resistor values. The 85-dB CMRR of the OPA820 itself will not determine the overall circuit CMRR unless the resistor ratios are matched to better than 0.003%. If it is necessary to trim the CMRR, then R2 is the suggested adjustment point. 20 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com DAC Transimpedance Amplifier High-frequency digital-to-analog converters (DACs) require a low-distortion output amplifier to retain their SFDR performance into real-world loads. See Figure 8 for a single-ended output drive implementation. In this circuit, only one side of the complementary output drive signal is used. The diagram shows the signal output current connected into the virtual ground-summing junction of the OPA820, which is set up as a transimpedance stage or I-V converter. The unused current output of the DAC is connected to ground. If the DAC requires its outputs to be terminated to a compliance voltage other than ground for operation, then the appropriate voltage level may be applied to the non-inverting input of the OPA820. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 OPA820 High−Speed DAC VO = ID RF RF CF ID CD GBP → Gain Bandwidth Product (Hz) for the OPA820. ID Figure 8. Wideband, Low-Distortion DAC Transimpedance Amplifier The DC gain for this circuit is equal to RF. At high frequencies, the DAC output capacitance (CD) will produce a zero in the noise gain for the OPA820 that may cause peaking in the closed-loop frequency response. CF is added across RF to compensate for this noise-gain peaking. To achieve a flat transimpedance frequency response, this pole in the feedback network should be set to: 1 = 2pRFCF GBP 4pRFCD (1) which will give a corner frequency f−3dB of approximately: f - 3dB = GBP 4pRFCD Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT (2) 21 OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com Active Filters Most active filter topologies will have exceptional performance using the broad bandwidth and unity-gain stability of the OPA820. Topologies employing capacitive feedback require a unity-gain stable, voltage-feedback op amp. Sallen-Key filters simply use the operational amplifier as a noninverting gain stage inside an RC network. Either current- or voltage-feedback op amps may be used in Sallen-Key implementations. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Figure 9 shows an example Sallen-Key low-pass filter, in which the OPA820 is set up to deliver a low-frequency gain of +2. The filter component values have been selected to achieve a maximally-flat Butterworth response with a 5-MHz, −3-dB bandwidth. The resistor values have been slightly adjusted to compensate for the effects of the 240-MHz bandwidth provided by the OPA820 in this configuration. This filter may be combined with the ADC driver suggestions to provide moderate (2-pole) Nyquist filtering, limiting noise, and out-of-band harmonics into the input of an ADC. This filter will deliver the exceptionally low harmonic distortion required by high SFDR ADCs such as the ADS850 (14-bit, 10 MSPS, 82-dB SFDR). C1 150pF +5V R1 124Ω R2 505Ω V1 C2 100pF OPA820 VO RF 402Ω Power−supply decoupling not shown. −5V RG 402Ω Figure 9. 5-MHz Butterworth Low-Pass Active Filter Another type of filter, a high-Q bandpass filter, is shown in Figure 10. The transfer function for this filter is: R3 + R 4 S VOUT R1R 4C1 = 1 R3 VIN 2 + S +S R1C1 R2R 4R5C1C2 with wO 2 = R3 R2R 4R5C1C2 and 1 wO = Q R1C1 For the values chosen in Figure 10: wO ≃ fO = ; 1MHz 2p (3) (4) (5) (6) and Q = 100. See Figure 11 for the frequency response of the filter shown in Figure 10. 22 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com R3 500Ω OPA820 R4 500Ω C2 1000pF R5 158Ω 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 R1 15.8kΩ R2 158Ω OPA820 VOUT VIN C1 1000pF Gain (dB) Figure 10. High-Q 1-MHz Bandpass Filter 6 0 −6 −12 −18 −24 −30 −36 −42 −48 −54 −60 −66 −72 100k 1M 10M 100M Frequency (Hz) Figure 11. High-Q 1-MHz Bandpass Filter Frequency Response DESIGN-IN TOOLS Macromodels and Applications Support Computer simulation of circuit performance using SPICE is often a quick way to analyze the performance of the OPA820 and its circuit designs. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can play a major role on circuit performance. A SPICE model for the OPA820 is available through the TI web page (www.ti.com). The applications department is also available for design assistance. These models predict typical small-signal AC, transient steps, DC performance, and noise under a wide variety of operating conditions. The models include the noise terms found in the electrical specifications of the data sheet. These models do not attempt to distinguish between the package types in their small-signal AC performance. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT 23 OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com OPERATING SUGGESTIONS Optimizing Resistor Values Since the OPA820 is a unity-gain stable, voltage-feedback operational amplifier, a wide range of resistor values may be used for the feedback and gain-setting resistors. The primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. Usually, the feedback resistor value should be between 200 Ω and 1 kΩ. Below 200 Ω, the feedback network will present additional output loading which can degrade the harmonic distortion performance of the OPA820. Above 1 kΩ, the typical parasitic capacitance (approximately 0.2 pF) across the feedback resistor may cause unintentional band limiting in the amplifier response. A direct short is suggested as a feedback for AV = +1 V/V. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 A good rule of thumb is to target the parallel combination of RF and RG (see Figure 2) to be less than about 200 Ω. The combined impedance RF||RG interacts with the inverting input capacitance, placing an additional pole in the feedback network, and thus a zero in the forward response. Assuming a 2-pF total parasitic on the inverting node, holding RF||RG < 200 Ω will keep this pole above 400 MHz. By itself, this constraint implies that the feedback resistor RF can increase to several kΩ at high gains. This is acceptable as long as the pole formed by RF and any parasitic capacitance appearing in parallel is kept out of the frequency range of interest. In the inverting configuration, an additional design consideration must be noted. RG becomes the input resistor and therefore the load impedance to the driving source. If impedance matching is desired, RG may be set equal to the required termination value. However, at low inverting gains, the resulting feedback resistor value can present a significant load to the amplifier output. For example, an inverting gain of 2 with a 50-Ω input matching resistor (= RG) would require a 100-Ω feedback resistor, which would contribute to output loading in parallel with the external load. In such a case, it would be preferable to increase both the RF and RG values, and then achieve the input matching impedance with a third resistor to ground (see Figure 3). The total input impedance becomes the parallel combination of RG and the additional shunt resistor. Bandwidth vs Gain Voltage-feedback operational amplifiers exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory, this relationship is described by the GBP shown in the specifications. Ideally, dividing GBP by the noninverting signal gain (also called the noise gain, or NG) will predict the closed-loop bandwidth. In practice, this only holds true when the phase margin approaches 90°, as it does in high-gain configurations. At low signal gains, most amplifiers will exhibit a more complex response with lower phase margin. The OPA820 is optimized to give a maximally-flat, 2nd-order Butterworth response in a gain of 2. In this configuration, the OPA820 has approximately 64° of phase margin and will show a typical −3-dB bandwidth of 240 MHz. When the phase margin is 64°, the closed-loop bandwidth is approximately √2 greater than the value predicted by dividing GBP by the noise gain. Increasing the gain will cause the phase margin to approach 90° and the bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of +10, the 30-MHz bandwidth shown in the Electrical Characteristics agrees with that predicted using the simple formula and the typical GBP of 280 MHz. Output Drive Capability The OPA820 has been optimized to drive the demanding load of a doubly-terminated transmission line. When a 50-Ω line is driven, a series 50 Ω into the cable and a terminating 50-Ω load at the end of the cable are used. Under these conditions, the cable impedance will appear resistive over a wide frequency range, and the total effective load on the OPA820 is 100 Ω in parallel with the resistance of the feedback network. The electrical characteristics show a ±3.6-V swing into this load—which will then be reduced to a ±1.8-V swing at the termination resistor. The ±75-mA output drive over temperature provides adequate current drive margin for this load. Higher voltage swings (and lower distortion) are achievable when driving higher impedance loads. A single video load typically appears as a 150-Ω load (using standard 75-Ω cables) to the driving amplifier. The OPA820 provides adequate voltage and current drive to support up to three parallel video loads (50-Ω total load) for an NTSC signal. With only one load, the OPA820 achieves an exceptionally low 0.01%/0.03° dG/dP error. 24 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com Driving Capacitive Loads 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 One of the most demanding, and yet very common, load conditions for an operational amplifier is capacitive loading. A high-speed, high open-loop gain amplifier like the OPA820 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. In simple terms, the capacitive load reacts with the open-loop output resistance of the amplifier to introduce an additional pole into the loop and thereby decrease the phase margin. This issue has become a popular topic of application notes and articles, and several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended RS vs Capacitive Load and the resulting frequency response at the load. The criterion for setting the recommended resistor is maximum bandwidth, flat frequency response at the load. Since there is now a passive low-pass filter between the output pin and the load capacitance, the response at the output pin itself is typically somewhat peaked, and becomes flat after the roll-off action of the RC network. This is not a concern in most applications, but can cause clipping if the desired signal swing at the load is very close to the amplifier’s swing limit. Such clipping would be most likely to occur in pulse response applications where the frequency peaking is manifested as an overshoot in the step response. Parasitic capacitive loads greater than 2 pF can begin to degrade the performance of the OPA820. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA820 output pin (see the Board Layout section). Distortion Performance The OPA820 is capable of delivering an exceptionally low distortion signal at high frequencies and low gains. The distortion plots in the Typical Characteristics show the typical distortion under a wide variety of conditions. Most of these plots are limited to 100-dB dynamic range. The OPA820 distortion does not rise above −90 dBc until either the signal level exceeds 0.9 V and/or the fundamental frequency exceeds 500 kHz. Distortion in the audio band is ≤ −100 dBc. Generally, until the fundamental signal reaches very high frequencies or powers, the 2nd-harmonic will dominate the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network—in the noninverting configuration this is the sum of RF + RG, whereas in the inverting configuration this is just RF (see Figure 2). Increasing the output voltage swing increases harmonic distortion directly. Increasing the signal gain will also increase the 2nd-harmonic distortion. Again, a 6-dB increase in gain will increase the 2nd- and 3rd-harmonic by 6 dB even with a constant output power and frequency. Finally, the distortion increases as the fundamental frequency increases because of the roll-off in the loop gain with frequency. Conversely, the distortion will improve going to lower frequencies down to the dominant open-loop pole at approximately 100 kHz. Starting from the −85-dBc 2nd-harmonic for 2VPP into 200 Ω, G = +2 distortion at 1 MHz (from the Typical Characteristics), the 2nd-harmonic distortion will not show any improvement below 100 kHz and will then be: −100 dB − 20 log (1 MHz/100 kHz) = −105 dBc Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT 25 OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com Noise Performance The OPA820 complements its low harmonic distortion with low input noise terms. Both the input-referred voltage noise and the two input-referred current noise terms combine to give a low output noise under a wide variety of operating conditions. Figure 12 shows the operational amplifier noise analysis model with all the noise terms included. In this model, all the noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. ENI EO 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 OPA820 RS IBN ERS RF √4kTRS RG 4kT RG I BI √4kTRF 4kT = 1.6E − 20J at 290 K Figure 12. Operational Amplifier Noise Analysis Model The total output spot noise voltage is computed as the square root of the squared contributing terms to the output noise voltage. This computation is adding all the contributing noise powers at the output by superposition, then taking the square root to get back to a spot noise voltage. Equation 7 shows the general form for this output noise voltage using the terms presented in Figure 12. EO = [E2NI + (IBNRS )2 + 4kTRS]NG2 + (IBIRF )2 + 4kTRFNG (7) Dividing this expression by the noise gain (NG = 1 + RF/RG) will give the equivalent input referred spot noise voltage at the noninverting input, as shown in Equation 8. 2 EN 4kTRF æ IBIRF ö = E2NI + (IBNRS )2 + 4kTRS + ç + ÷ NG è NG ø (8) Evaluating these two equations for the OPA820 circuit presented in Figure 2 will give a total output spot noise voltage of 6.44 nV/√Hz and an equivalent input spot noise voltage of 3.22 nV/√Hz. DC Offset Control The OPA820 can provide excellent DC signal accuracy because of its high open-loop gain, high common-mode rejection, high power-supply rejection, and low input offset voltage and bias current offset errors. To take full advantage of this low input offset voltage, careful attention to input bias current cancellation is also required. The high-speed input stage for the OPA820 has a moderately high input bias current (9 μA typ into the pins) but with a very close match between the two input currents—typically 100-nA input offset current. The total output offset voltage may be considerably reduced by matching the source impedances looking out of the two inputs. For example, one way to add bias current cancellation to the circuit of Figure 2 would be to insert a 175-Ω series resistor into the noninverting input from the 50-Ω terminating resistor. When the 50-Ω source resistor is DC-coupled, this will increase the source impedance for the noninverting input bias current to 200 Ω. Since this is now equal to the impedance looking out of the inverting input (RF||RG), the circuit will cancel the gains for the bias currents to the output leaving only the offset current times the feedback resistor as a residual DC error term at the output. Using a 402-Ω feedback resistor, this output error will now be less than ±0.4 μA × 402 Ω = ±160 μV at 25°C. 26 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com Thermal Analysis The OPA820 will not require heatsinking or airflow in most applications. Maximum desired junction temperature would set the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 210°C. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). Under this worst-case condition, PDL = VS2/(4 × RL), where RL includes feedback network loading. Note that it is the power in the output stage and not in the load that determines internal power dissipation. Board Layout Achieving optimum performance with a high-frequency amplifier such as the OPA820 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a. Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b. Minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1-μF decoupling capacitors. At the device pins, the ground and power-plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. Larger (2.2-μF to 6.8-μF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c. Careful selection and placement of external components will preserve the high-frequency performance of the OPA820. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially leaded resistors can also provide good high-frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wire-wound type resistors in a high-frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values > 1.5 kΩ, this parasitic capacitance can add a pole and/or a zero below 500 MHz that can effect circuit operation. Keep resistor values as low as possible consistent with load-driving considerations. It has been suggested here that a good starting point for design would be to set RG||RF = 200 Ω. Using this setting will automatically keep the resistor noise terms low, and minimize the effect of their parasitic capacitance. d. Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of Recommended RS vs Capacitive Load. Low parasitic capacitive loads (< 5 pF) may not need an RS since the OPA820 is nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is normally not necessary onboard, and in fact, a higher impedance environment will improve distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined based on Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT 27 OPA820-HT SBOS587 – DECEMBER 2011 www.ti.com 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 board material and trace dimensions, a matching series resistor into the trace from the output of the OPA820 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and input impedance of the destination device; this total effective impedance should be set to match the trace impedance. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of RS vs Capacitive Load. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e. Socketing a high-speed part like the OPA820 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA820 onto the board. Input and ESD Protection The OPA820 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 13. +VCC External Pin −VCC Figure 13. Internal ESD Protection These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30-mA continuous current. Where higher currents are possible (for example, in systems with ±15-V supply parts driving into the OPA820), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. Figure 14 shows an example protection circuit for I/O voltages that may exceed the supplies. +5V 50Ω Source Power−supply decoupling not shown. 174Ω V1 50Ω 50Ω D1 D2 OPA820 RF 301Ω 50Ω RG 301Ω VO −5V D1 = D2 IN5911 (or equivalent) Figure 14. Gain of +2 With Input Protection 28 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA820-HT PACKAGE OPTION ADDENDUM www.ti.com 9-May-2012 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 PACKAGING INFORMATION Orderable Device OPA820SKGD3 Status (1) Package Type Package Drawing ACTIVE (1) XCEPT KGD Pins Package Qty 0 400 Eco Plan TBD (2) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) N / A for Pkg Type The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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