ETC HMS87C5216

HMS87C5216
HMS87C5216
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
FOR UR(Universal Remocon) & WIRELESS KEYBOARD
1. OVERVIEW
1.1 Description
The HMS87C5216 is an advanced CMOS 8-bit microcontroller with 16K bytes of ROM. The device is one of GMS800 family. The HYNIX Semicon HMS87C5216 is a powerful microcontroller which provides a highly flexible and cost effective
solution to many UR & Keyboard applications. The HMS87C5216 provides the following standard features: 16K bytes of
ROM, 320 bytes of RAM, 8-bit timer/counter, on-chip oscillator,clock circuitry and RC wake up function. 4 chanel ADC, In
addition, the HMS87C5216 Series supports power saving modes to reduce power consumption
Device name
ROM Size
HMS87C5216
EPROM Size
-
16K byte
RAM Size
320bytes
Operatind
Voltage
Package
2.0 ~ 5.5V
28 SOP
40 PDIP
44 PLCC
44 QFP
1.2 Features
• Instruction Cycle Time:
- 1us at 4MHz
• Programmable I/O pins
28 PIN
40 PIN
44 PIN
INPUT
2
2
2
OUTPUT
2
2
2
I/O
22
34
38
• Operating Voltage
- 2.0 ~ 5.5 V @ 4MHz
• Timer
- Timer / Counter
......... 16Bit * 1ch
........ 16Bit * 2ch
- Basic Interval Timer ...... 8Bit * 1ch
- Watch Dog Timer ............ 6Bit * 1ch
Sep. 2001 Ver 1.0
• 8 Interrupt sources
* Nested Interrupt control is available.
- External input: 2
- Keyscan input
- Basic Interval Timer
- Watchdog timer
- Timer : 3
• Power On Reset
• Power saving Operation Modes
- STOP
- SLEEP
• Low Voltage Detection Circuit
• Watch Dog Timer Auto Start (During 1second
after Power on Reset)
• 4 CHANEL ADC
• RC TIMER WAKE UP
1
HMS87C5216
1.3 Development Tools
The HMS87C5216 and HMS87C5216 are supported by a
full-featured macro assembler, an in-circuit emulator
CHOICE-DrTM.
In Circuit Emulators
Assembler
OTP Writer
CHOICE-Dr.
HME Macro Assembler
Single Writer : Sigma
4-Gang Writer : Dr.Gang
OTP Devices
2
HMS87C5216
Sep. 2001 Ver 1.0
HMS87C5216
2. BLOCK DIAGRAM
PSW
Accumulator
ALU
PC
Stack Pointer
Data
Memory
RESET
Program
Memory
System controller
System
Clock Controller
Timing generator
8-bit Basic
Interval
Timer
Data Table
Inte rrupt C ontroller
Xin
Xout
Clock Generator
Instruction
Decoder
Watch-dog
Key Wake up
8-bit
A/D
Converter
8-bit
Timer/
Counter
Carrier
Generator
RC Watch
Timer
LVD/POR
VDD
R0
VSS
R1
R2
R3
R4
R30
R31
R32
R33
R34
R35
R36
R37
R40
R41
R42
R43
R44
Power
Supply
R00 / KS0
R01 / KS1
R02 / KS2
R03 / KS3
R04 / KS4
R05 / KS5
R06 / KS6
R07 / KS7
Sep. 2001 Ver 1.0
R10 / INT1
R11 / INT2
R12 / T0
R13 / T1
R14 / AN0
R15 / AN1
R16 / AN2
R17 / AN3
R20
R21
R22
R23
R24 /T2
R25 / EC0
R26
R27
REMOUT
3
HMS87C5216
17
R15
R12
13
16
R14
R13
14
15
RESETB
1
40
R01
2
39
R27
R02
3
38
R26
R03
4
37
R25
R04
5
36
R24
R05
6
35
R23
R06
7
34
R22
R07
8
33
R21
R34
9
32
R20
VDD
11
40PDIP
31
30
R33
R32
R32
R42
VSS
R31
R30
R17
43
42
41
40
R33
2
44
R20
3
1
R22
R21
4
R23
5
R12
R03
16
30
R11
R04
17
29
R10
REMOUT
R00
10
R13
31
XIN 28
12
32
15
R17
R16
14
R02
23
18
11
R17
R01
XOUT 27
19
10
R11
R35
R24
34
22 R16
R25
35
21 R40
R26
36
20 R15
R27
37
19 R14
R43
38
18
REMOUT
39
44QFP
RESETB
17
R45
40
16
R41
R12
18
23 R15
R13
19
22
R41 20
R16
R14
21 RESETB
XIN 11
24 R40
XOUT 10
25
17
9
16
R11
8
R10
R37
R17
R36
R10
26
7
R04
12
15
VDD
R11
44
XIN
6
R03
13
R44
R12
43
5
14
27
R35
R13
R30
14
4
15
42
R34
41
R02
3
R01
R07
R31
2
28
1
29 VSS
13
R06
12
R37
R05
R36
R00
XOUT
4
VSS
R41
R30
R10
R20
20
R45
33
24
XIN
21
44PLCC
13
R37 26
9
R00
R36 25
8
R21
34
R31
VDD
XOUT
22
28PIN
12
25
7
RESETB
11
33 R23
R07
35
R43
REMOUT
26 VSS
R22
VDD 24
6
R06
R14
27 R42
R23
23
36
R44 23
24
10
28 R32
5
R15
R27
R34 21
R05
R24
R35 22
25
37
R33
4
9
29
R04
R40
R26
R20
R25
R16
38
30
26
39
8
R07 20
3
7
R25
R21
R03
R24
31
REMOUT
R05 18
R00
27
R06 19
28
2
R22
1
R02
32
R01
6
3. PIN ASSIGNMENT
Sep. 2001 Ver 1.0
HMS87C5216
4. PIN DIAGRAM
Sep. 2001 Ver 1.0
5
HMS87C5216
0.200 max.
6
0.022
0.015
0.065
0.045
0.100 BSC
0.600 BSC
0.550
0.530
0.140
0.120
MIN 0.015
2.075
2.045
0.012
0.008
Sep. 2001 Ver 1.0
HMS87C5216
Sep. 2001 Ver 1.0
7
HMS87C5216
5. PIN FUNCTION
R20~R22, R30~R37 : R2 & R3 is a 8-bit CMOS bidirectional I/O port. Each pins 1 or 0 written to the their Port Direction Register can be used as outputs or inputs.
VDD: Supply voltage.
VSS: Circuit ground.
RESET: Reset the MCU.
XIN: Input to the inverting oscillator amplifier and input to
the internal main clock operating circuit.
XOUT: Output from the inverting oscillator amplifier.
R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.
R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.
In addition, R2 serves the functions of the various following special features.
Port pin
R24
R25
Alternate function
T2 (Timer / Counter inpit 2)
/EC (Event Counter input )
R40~R43 : R4 is 1-bit CMOS bidirectional I/O port. This
pin 1 or 0 written to the its Port Direction Register can be
used as outputs or inputs.
In addition, R1 serves the functions of the various following special features.
Port pin
R10
R11
R12
R13
R14
R15
R16
R17
8
Alternate function
INT1 (External Interrupt input 1)
INT2 (External Interrupt input 2)
T0 (Timer / Counter inpit 0)
T1 (Timer / Counter inpit 1)
AN0 (ADC input 0)
AN1 (ADC input 1)
AN2 (ADC input 2)
AN3 (ADC input 3)
Sep. 2001 Ver 1.0
HMS87C5216
6.
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
Sep. 2001 Ver 1.0
9
HMS87C5216
7. PORT STRUCTURES
• RESET
10
Sep. 2001 Ver 1.0
HMS87C5216
• Xin, Xout
ÚÞ ’
Sep. 2001 Ver 1.0
11
HMS87C5216
• RA0/EC0
ÚÞ ’
12
Sep. 2001 Ver 1.0
HMS87C5216
• RA1/AN1 ~ RA7/AN7
XIN
XOUT
Sep. 2001 Ver 1.0
13
HMS87C5216
8. ELECTRICAL CHARACTERISTICS (HMS87C5216/GMS81C1408)
8.1 Absolute Maximum Ratings
Supply voltage ........................................... -0.3 to +7.0 V
Storage Temperature ................................-40 to +125 °C
aximum current out of VSS pin..........................TBD mA
Maximum current into VDD pin ........................TBD mA
Maximum current sunk by (IOL per I/O Pin) ....TBD mA
Maximum output current sourced by (IOH per I/O Pin)
...........................................................................TBD mA
Maximum current (ΣIOL) ...................................TBDmA
Maximum current (ΣIOH) ...................................TBDmA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods
may affect device reliability.
8.2 Recommended Operating Conditions
Specifications
Parameter
Symbol
Condition
Unit
Min.
Max.
Supply Voltage
VDD
fXIN=4MHz
2.0
5.5
V
Operating Frequency
fXIN
VDD=2.0~5.5V
1
4
MHz
TOPR
VDD=2.0~5.5V
-20
85
°C
Operating Temperature
8.3 A/D Converter Characteristics
(TA=25°C, VSS=0V, VDD=3.072V @fXIN =4MHz)
Specifications
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
VAIN
-
VSS-0.3
-
VDD+0.3
V
Current Following Between AVdd and AVss
IAVdd
-
-
-
200
uA
Overall Accuracy
NACC
-
-
±1.0
±2.0
LSB
Non-Linearity Error
NNLE
-
-
±1.0
±2.0
LSB
Differential Non-Linearity Error
NDNLE
-
-
±1.0
±2.0
LSB
Zero Offset Error
NZOE
-
±0.5
±1.5
LSB
Full Scale Error
NFSE
-
±0.25
±0.5
LSB
Gain Error
NNLE
-
±1.0
±1.5
LSB
-
-
30
uS
Analog Input Voltage Range
TCONV
Conversion Time
fXIN=4MHz
8.4 DC Electrical Characteristics
(TA=-20~85°C for HMS87C5216/1408 or TA=-40~85°C for HMS87C5216E/1408E, VDD=2.2~5.5V, VSS=0V),
Specifications
Parameter
Input High Voltage
14
Symbol
VIH1
Pin
XIN, RESET
Condition
Unit
Min.
Typ.
Max.
0.8 VDD
-
VDD
V
Sep. 2001 Ver 1.0
HMS87C5216
Specifications
Parameter
Symbol
Pin
Condition
Unit
Min.
Typ.
Max.
VIH1
RESET,XIN,INT1,IN
T2,EC0,R1<7:4>
0.8VDD
-
VDD
V
VIH2
R0,R1,R2,R3,R4
0.7VDD
-
VDD
V
VIL1
RESET,XIN,INT1,IN
T2,EC0,R1<7:4>
0
-
0.2VDD
V
VIL2
R0,R1,R2,R3,R4
0
-
0.3VDD
V
Input High
Leakage Current
IIH
R0,R1,R2,R3,R4
RESETB
VIH=VDD
-
-
1.0
µA
Input Low
Leakage Current
IIL
R0,R1,R2,R3,R4
VIL=0V
-
-
-1.0
µA
VOH1
R0,R1<3:0>,R2,R3,
R4
Ioh1=-0.8mA,VDD=3V
VDD-0.4
-
-
V
VOH2
R1<7:0>,
Ioh2=-2.0mA,VDD=3V
VDD-0.4
-
-
V
VOH3
XOUT
Ioh3=-50uA,VDD=3V
VDD-0.5
-
-
V
VOL1
R0,R1<3:0>,R2,R3,
R4
IOL=5mA,VDD=3V
-
-
0.8
V
VOL2
XOUT
IOL=50uA,VDD=3V
-
-
0.5
V
Output High
Leakage Current
IIOHL
R0,R1,R2,R3,R4
VOH=VDD
-
-
1.0
µA
Output Low
Leakage Current
IIOLL
R0,R1,R2,R3,R4
VOL=0V
-
-
-1.0
µA
Output High Current
IOH
REMOUT
VDD=3V,VOH=2.0V
-20
-
-5
mA
Output Low Current
IOL
REMOUT
VDD=3V,VOL=1.0V
-0.5
-
3
mA
Input Pull-up
IP
R0,R1,R2,R3,R4
RESETB
VDD=3V
50
100
200
κ
| VT |
Hysteresis Input1
VDD=5V
0.5
-
-
V
RF!
M ain O S C Feedback
R esistor
VDD=3.0V, fXIN=4MHz
0.2
-
1.0
IDD
Active Mode
VDD=4.0V
-
4.0
10
mA
VDD=2.0V
-
2.4
6
mA
Isleep
VDD=4.0V
-
2.0
3.0
mA
Sleep Mode
VDD=2.0V
-
1.0
2.0
mA
Istop
Stop Mode,Osc Stop
VDD=4.0V
-
5.0
30
µA
VDD=2.0V
-
3.0
25
µA
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Hysteresis
Feed Back Resistor
Supply Currnet
Sep. 2001 Ver 1.0
15
HMS87C5216
8.5 AC Characteristics
(TA=-20~85°C for HMS87C5216/1408 or TA=-40~85°C for HMS87C5216E/1408E, VDD=5V±10%, VSS=0V)
Specifications
Parameter
Symbol
Pins
Unit
Min.
Typ.
Max.
Operating Frequency
fMCP
XIN
1
-
4
MHz
Systemp Clock Cycle Time
tSYS
-
0.5
-
2.0
uS
Oscillation Stabilizing
Time(4MHz)
tMST!
XIN, XOUT
-
-
20
mS
External Clock “H” or “L” Pulse
Width
tCPW
XIN
80
External Clock Transition Time
tRCP,tFCP
XIN
-
-
tlW
INT1,INT2
2
-
RESETB Input Pulse “L” Width
tRST
RESETB
8
-
-
tSYS
Event Couter Input “H” or “L”
Pulse Width
tTCW
ECo
2
-
-
tSYS
Event Couter Transition Time
tREC,tFEC
ECo
0
-
20
nS
Interrupt Input Pulse Width
nS
20
nS
tSYS
Figure 8-1 Timing Chart
16
Sep. 2001 Ver 1.0
HMS87C5216
9. MEMORY ORGANIZATION
The HMS87C5216 have separate address spaces for Program memory and Data Memory. Program memory can
only be read, not written to. It can be up to 16K bytes of
Program memory. Data memory can be read and written to
up to 320 bytes including the stack area.
9.1 Registers
This device has six registers that are the Program Counter
(PC), a Accumulator (A), two index registers (X, Y), the
Stack Pointer (SP), and the Program Status Word (PSW).
The Program Counter consists of 16-bit register.
A
ACCUMULATOR
X
X REGISTER
Y
Y REGISTER
SP
PCH
STACK POINTER
PCL
PROGRAM COUNTER
PSW
PROGRAM STATUS
WORD
Generally, SP is automatically updated when a subroutine
call is executed or an interrupt is accepted. However, if it
is used in excess of the stack area permitted by the data
memory allocating configuration, the user-processed data
may be lost.
The stack can be located at any position within 100H to
17FH of the internal data memory. The SP is not initialized
by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of “17FH” is
used.
Stack Address (100H ~17FH)
15
8
1
Figure 9-1 Configuration of Registers
Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc.
The Accumulator can be used as a 16-bit register with Y
Register as shown below.
Y
Y
A
A
Two 8-bit Registers can be used as a “YA” 16-bit Register
Figure 9-2 Configuration of YA 16-bit Register
X, Y Registers: In the addressing mode which uses these
index registers, the register contents are added to the specified address, which becomes the actual address. These
modes are extremely effective for referencing subroutine
tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators.
Stack Pointer: The Stack Pointer is an 8-bit register used
for occurrence interrupts and calling out subroutines. Stack
Pointer identifies the location in the stack to be accessed
(save or restore).
Sep. 2001 Ver 1.0
7
0
SP
Hardware fixed
Note: The Stack Pointer must be initialized by software because its value is undefined after RESET.
Example: To initialize the SP
LDX
#07FH
TXSP
; SP ← 7FH
Program Counter: The Program Counter is a 16-bit wide
which consists of two 8-bit registers, PCH and PCL. This
counter indicates the address of the next instruction to be
executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH).
Program Status Word: The Program Status Word (PSW)
contains several bits that reflect the current state of the
CPU. The PSW is described in Figure 9-3 . It contains the
Negative flag, the Overflow flag, the Break flag the Half
Carry (for BCD operation), the Interrupt enable flag, the
Zero flag, and the Carry flag.
[Carry flag C]
This flag stores any carry or borrow from the ALU of CPU
after an arithmetic operation and is also changed by the
Shift Instruction or Rotate Instruction.
[Zero flag Z]
This flag is set when the result of an arithmetic operation
or data transfer is “0” and is cleared by any other result.
17
HMS87C5216
MSB
PSW
N
LSB
V
G
B
H
I
Z
C
RESET VALUE: 00H
CARRY FLAG RECEIVES
CARRY OUT
NEGATIVE FLAG
OVERFLOW FLAG
ZERO FLAG
SELECT DIRECT PAGE FLAG
INTERRUPT ENABLE FLAG
HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS
BRK FLAG
Figure 9-3 PSW (Program Status Word) Register
[Interrupt disable flag I]
This flag enables/disables all interrupts except interrupt
caused by Reset or software BRK instruction. All interrupts are disabled when cleared to “0”. This flag immediately becomes “0” when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.
[Half carry flag H]
After operation, this is set when there is a carry from bit 3
of ALU or there is no borrow from bit 4 of ALU. This bit
can not be set or cleared except CLRV instruction with
Overflow flag (V).
[Break flag B]
This flag is set by software BRK instruction to distinguish
BRK from TCALL instruction with the same vector address.
[Overflow flag V]
18
This flag is set to “1” when an overflow occurs as the result
of an arithmetic operation involving signs. An overflow
occurs when the result of an addition or subtraction exceeds +127(7FH) or -128(80H). The CLRV instruction
clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
to this flag.
[Negative flag N]
This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.
[Direct page flag G]
This flag assigns RAM page for direct addressing mode. In
the direct addressing mode, addressing area is from zero
page 00 to FF when this flag is 0. If it is set to 1, addressing
area is 1 page. It is set by instruction and cleared by
CLRG.
Sep. 2001 Ver 1.0
HMS87C5216
9.2 Program Memory
A 16-bit program counter is capable of addressing up to
64K bytes, but these devices have 16K bytes program
memory space only physically implemented. Accessing a
location above FFFFH will cause a wrap-around to 0000H.
Example: Usage of TCALL
Figure 9-4 , shows a map of Program Memory. After reset,
the CPU begins execution from reset vector which is stored
in address FFFEH and FFFFH as shown in Figure 9-5 .
;
;TABLE CALL ROUTINE
;
FUNC_A: LDA
LRG0
RET
;
FUNC_B: LDA
LRG1
2
RET
;
;TABLE CALL ADD. AREA
;
ORG
0FFC0H
DW
FUNC_A
DW
FUNC_B
As shown in Figure 9-4 , each area is assigned a fixed location in Program Memory. Program Memory area contains the user program.
C000H
LDA
#5
TCALL 0FH
:
:
;1BYTE INSTR UCTIO N
;INSTEAD OF 3 BYTES
;NOR M AL C ALL
1
;TCALL ADDRESS AREA
F000H
PROGRAM
MEMORY
FEFFH
FF00H
FFC0H
FFDFH
FFE0H
FFFFH
TCALL
AREA
PCALL
AREA
INTERRUPT
VECTOR AREA
Figure 9-4 Program Memory Map
The interrupt causes the CPU to jump to specific location,
where it commences the execution of the service routine.
The External interrupt 0, for example, is assigned to location 0FFFAH. The interrupt service locations spaces 2-byte
interval: 0FFF8H and 0FFF9H for External Interrupt 1,
0FFFAH and 0FFFBH for External Interrupt 0, etc.
As for the area from 0FF00H to 0FFFFH, if any area of
them is not going to be used, its service location is available as general purpose Program Memory.
Address
0FFE0H
Page Call (PCALL) area contains subroutine program to
reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called,
it is more useful to save program byte length.
Table Call (TCALL) causes the CPU to jump to each
TCALL address, where it commences the execution of the
service routine. The Table Call service area spaces 2-byte
for every TCALL: 0FFC0H for TCALL15, 0FFC2H for
TCALL14, etc., as shown in Figure 9-6 .
Vector Area Memory
-
E2
-
E4
ADC Interrupt Vector Area
E6
RC WT Interrupt Vector Area
E8
BIT Interrupt Vector Area
EA
WDT Interrupt Vector Area
EC
-
EE
Timer/Counter 2 Interrupt Vector Area
F0
Timer/Counter 1 Interrupt Vector Area
F2
Timer/Counter 0 Interrupt Vector Area
F4
-
F6
EXT2 Interrupt Vector Area
F8
EXT1 Interrupt Vector Area
FA
KEY SCAN Interrupt Vector Area
FC
-
FE
RESET Vector Area
NOTE:
“-” means reserved area.
Figure 9-5 Interrupt Vector Area
Sep. 2001 Ver 1.0
19
HMS87C5216
Address
Address
Program Memory
0FFC0H
C1
TCALL 15
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
PCALL Area Memory
0FF00H
PCALL Area
(256 Bytes)
0FFFFH
TCALL 14
TCALL 13
TCALL 12
TCALL 11
TCALL 10
TCALL 9
TCALL 8
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
TCALL 7
TCALL 6
TCALL 5
TCALL 4
TCALL 3
TCALL 2
TCALL 1
TCALL 0 / BRK *
NOTE:
* means that the BRK software interrupt is using
same address with TCALL0.
Figure 9-6 PCALL and TCALL Memory Area
PCALL→ rel
TCALL→ n
4F35
4A
PCALL 35H
TCALL 4
4A
4F
35
~
~
~
~
~
~
0F125H
01001010
~
~
NEXT
þ
Reverse
PC: 11111111 11010110
FH FH
DH 6H
0FF00H
0FF35H
0FFFFH
NEXT
Ã
0FF00H
0FFD6H
25
0FFD7H
F1
À
0FFFFH
20
Sep. 2001 Ver 1.0
HMS87C5216
Example: The usage software example of Vector address and the initialize part.
ORG
0FFE0H
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
NOT_USED
NOT_USED
ADC_INT
RC_WT_INT
BIT_INT
WDT_INT
NOT_USED
TMR2_INT
TMR1_INT
TMR0_INT
NOT_USED
EXT2_INT
EXT1_INT
KEY_SCAN
NOT_USED
RESET
ORG
0F000H
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
(0FFEO)
(0FFE2)
(0FFE4)
(0FFE6)
(0FFE8)
(0FFEA)
(0FFEC)
(0FFEE)
(0FFF0)
(0FFF2)
(0FFF4)
(0FFF6)
(0FFF8)
(0FFFA)
(0FFFC)
(0FFFE)
A/D Interface
RC WAKE UP Timer
BIT Timer
WDT
Timer-2
Timer-1
Timer-0
External2
External1
Key Scan
Reset
;********************************************
;
MAIN
PROGRAM
*
;*******************************************
;
RESET: DI
;Disable All Interrupts
LDX
#0
RAM_CLR: LDA
#0
;RAM Clear(!0000H->!00BFH)
STA
{X}+
CMPX
#0C0H
BNE
RAM_CLR
;
LDX
#07FH
;Stack Pointer Initialize
TXSP
;
CALL
INITIAL
;
;
LDM
R1, #0
;Normal Port A
LDM
R1DD,#1000_0010B ;Normal Port Direction
LDM
R2, #0
;Normal Port B
LDM
R2DD,#1000_0010B ;Normal Port Direction
:
:
:
:
Sep. 2001 Ver 1.0
21
HMS87C5216
9.3 Data Memory
Figure 9-7 shows the internal Data Memory space available. Data Memory is divided into two groups, a user RAM
(including Stack) and control registers.
Note: Several names are given at same address. Refer to-
Address
0000H
Symbol
R/W
RESET
Value
Addressing
m ode
Table 9-1 Control Registers
USER
MEMORY
PAGE0
00BFH
00C0H
00FFH
0100H
CONTROL
REGISTERS
USER
MEMORY
(including STACK)
PAGE2
017FH
Figure 9-7 Data Memory Map
User Memory
The HMS87C5216 has 330 × 8 bits for the user memory
(RAM).
Control Registers
The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog to
digital converters and I/O ports. The control registers are in
address range of 0C0H to 0FFH.
Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
More detailed informations of each register are explained
in each peripheral section.
Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write
instruction. Use byte manipulation instruction.
Example; To write at CKCTLR
LDM
22
CKCTLR,#09H ;Divide ratio ÷16
Sep. 2001 Ver 1.0
HMS87C5216
Address
Symbol
R/W
RESET
Value
Addressing
mode
0C0H
0C1H
0C2H
0C3H
0C4H
0C5H
0C6H
0C7H
0C7H
0C8H
0C9H
0CAH
0CBH
0CCH
0CDH
0CEH
0CFH
R0
R0DR
R1
R1DR
R2
R2DR
TMR1
CKCTLR
BITR
WDTR
PSR
RCWTR
IESR
IENL
IRQL
IENH
IRQH
R/W
W
R/W
W
R/W
W
W
W
R
W
W
W
W
R/W
R/W
R/W
R/W
Undefined
0000_0000
Undefined
0000_0000
Undefined
0000_0000
0000_0000
--11_0111
0000_0000
-000_1111
--00_0000
----_1000
--00_00--000_-0--000_-0-000-_000000-_000-
byte, bit1
byte2
byte, bit
byte
byte, bit
byte
byte
byte
byte
byte
byte
byte,bit
byte,bit
byte,bit
byte,bit
byte,bit
byte,bot
0D0H
0D1H
0D2H
0D3H
0D4H
0D5H
0D5H
0D6H
0D6H
0D7H
0D8H
0D8H
0D9H
0D9H
0DAH
0DCH
0DDH
0DEH
0DFH
TM0
TM1
TM2
T0HMD
T0HLD
T0MC
T0LMD
T0LC
T0LLD
T1HD
T1C
T1LD
T2C
T2D
TM01
KSR0
KSR1
R10D
R2OD
R/W
R/W
R/W
W
W
R
W
R
W
W
R
W
R
W
R/W
W
W
W
W
0000_0000
0000_-000
---0_0000
Undefined
Undefined
0000_0000
Undefined
0000_0000
Undefined
Undefined
0000_0000
Undefined
0000_0000
Undefined
0000_0000
00000_000
0000_0000
0000_0000
0000_0000
byte, bit
byte, bit
byte, bit
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte,bit
0E0H
0E1H
0E4H
0E5H
0E6H
0E7H
0E8H
0EEH
0EFH
R3OD
R4OD
R0OD
R3
R3DR
R4
R4DR
TMR2
LVDR
W
W
W
R/W
W
R/W
W
R
R
0000_0000
--00_0000
0000_0000
Undefined
0000_0000
Undefined
TT00_0000
0000_0000
TTT_T00T
byte
byte
byte
byteSbit
byte
byte,bit
byte
byte
byte
0F0H
0F4H
0F5H
0F6H
0F7H
0F8H
0F9H
0FAH
0FBH
0FCH
SMR
ADMR
ADDR
KRL0
KRL1
R0PU
R1PU
R2PU
R3PU
R4PU
W
R/W
R
W
W
W
W
W
W
W
----_---0
-000_0001
Undefined
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
--00_0000
byte
byte, bit
byte
byte
byte
byte
byte
byte
byte
byte
Table 9-1 Control Registers
1. “byte, bit” means that register can be addressed by not only bit
but byte manipulation instruction.
2. “byte” means that register can be addressed by only byte
manipulation instruction. On the other hand, do not use any
read-modify-write instruction such as bit manipulation for
clearing bit.
below table.
Stack Area
The stack provides the area where the return address is
saved before a jump is performed during the processing
routine at the execution of a subroutine call instruction or
the acceptance of an interrupt.
When returning from the processing routine, executing the
subroutine return instruction [RET] restores the contents of
the program counter from the stack; executing the interrupt
return instruction [RETI] restores the contents of the program counter and flags.
The save/restore locations in the stack are determined by
the stack pointed (SP). The SP is automatically decreased
after the saving, and increased before the restoring. This
means the value of the SP indicates the stack location
number for the next save.
Table 9-1 Control Registers
Sep. 2001 Ver 1.0
23
HMS87C5216
9.4 Addressing Mode
The HMS87C5216 and GMS81C1408 uses six addressing
modes;
(3) Direct Page Addressing → dp
• Register addressing
Example;
• Immediate addressing
C535
In this mode, a address is specified within direct page.
LDA
;A ←RAM[35H]
35H
• Direct page addressing
• Absolute addressing
0035H
data
À
• Indexed addressing
~
~
• Register-indirect addressing
~
~
0F550H
C5
0F551H
35
þ
data → A
(1) Register Addressing
Register addressing accesses the A, X, Y, C and PSW.
(2) Immediate Addressing → #imm
In this mode, second byte (operand) is accessed as a data
immediately.
Example:
0435
ADC
#35H
(4) Absolute Addressing → !abs
Absolute addressing sets corresponding memory data to
Data, i.e. second byte(Operand I) of command becomes
lower level address and third byte (Operand II) becomes
upper level address.
With 3 bytes command, it is possible to access to whole
memory area.
MEMORY
ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,
LDY, OR, SBC, STA, STX, STY
04
A+35H+C → A
35
Example;
0735F0
E45535
LDM
ADC
data
0F035H
35H,#55H
~
~
0F100H
~
~
24
À
~
~
þ
A+data+C → A
07
0F101H
35
0F102H
F0
address: 0F035
~
~
þ
0F100H
data ← 55H
data
0035H
;A ←ROM[0F035H]
!0F035H
À
E4
0F101H
55
0F102H
35
Sep. 2001 Ver 1.0
HMS87C5216
The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR
Example; Addressing accesses the address 0135H.
983500
INC
;A ←RAM[035H]
!0035H
X indexed direct page, auto increment→ {X}+
In this mode, a address is specified within direct page by
the X register and the content of X is increased by 1.
LDA, STA
Example; X=35H
DB
data
0035H
~
~
LDA
{X}+
Ã
À
~
~
data+1 → data
0F100H
98
þ
0F101H
35
address: 0035
0F102H
00
35H
À
data
~
~
data → A
~
~
þ
36H → X
DB
(5) Indexed Addressing
X indexed direct page (no offset) → {X}
In this mode, a address is specified by the X register.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA
Example; X=15H
D4
LDA
{X}
;ACC←RAM[X].
X indexed direct page (8 bit offset) → dp+X
This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page.
ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA
STY, XMA, ASL, DEC, INC, LSR, ROL, ROR
Example; X=015H
15H
C645
data
~
~
LDA
45H+X
À
data → A
~
~
þ
0E550H
D4
5AH
data
Ã
~
~
Sep. 2001 Ver 1.0
À
~
~
0E550H
C6
0E551H
45
data → A
þ
45H+15H=5AH
25
HMS87C5216
Y indexed direct page (8 bit offset) → dp+Y
3F35
JMP
[35H]
This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in
Direct page.
This is same with above (2). Use Y register instead of X.
35H
0A
36H
E3
Y indexed absolute →!abs+Y
~
~
Sets the value of 16-bit absolute address plus Y-register
data as Memory. This addressing mode can specify memory in whole area.
Example; Y=55H
D500FA
LDA
~
~
D5
00
0F102H
FA
~
~
~
~
þ
3F
35
!0FA00H+Y
0F100H
À jump to address 0E30AH
NEXT
0FA00H
0F101H
0FA55H
0E30AH
~
~
þ
X indexed indirect → [dp+X]
0FA00H+55H=0FA55H
~
~
À
data → A
data
Ã
Processes memory data as Data, assigned by 16-bit pair
memory which is determined by pair data
[dp+X+1][dp+X] Operand plus X-register data in Direct
page.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; X=10H
1625
ADC
[25H+X]
(6) Indirect Addressing
Direct page indirect → [dp]
Assigns data address to use for accomplishing command
which sets memory data(or pair memory) by Operand.
Also index can be used with Index register X,Y.
JMP, CALL
35H
05
36H
E0
~
~ À
~
~
0E005H
0FA00H
25 + X(10) = 35H
~
~
16
25
26
þ
data
~
~
Example;
0E005H
à A + data + C → A
Sep. 2001 Ver 1.0
HMS87C5216
Y indexed indirect → [dp]+Y
Absolute indirect → [!abs]
Processes memory data as Data, assigned by the data
[dp+1][dp] of 16-bit pair memory paired by Operand in Direct page plus Y-register data.
The program jumps to address specified by 16-bit absolute
address.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; Y=10H
1725
ADC
JMP
Example;
1F25E0
JMP
[!0C025H]
[25H]+Y
PROGRAM MEMORY
25H
05
0E025H
25
26H
E0
0E026H
E7
~
~
0E015H
~
~
0FA00H
0E005H + Y(10) = 0E015H
þ
data
~
~
À
~
~
þ
0E725H
0FA00H
17
Sep. 2001 Ver 1.0
À
jump to
address 0E30AH
NEXT
~
~
~
~
25
~
~
~
~
1F
25
à A + data + C → A
E0
27
HMS87C5216
10. I/O PORTS
The GMS87C5216 has 38 I/O ports which are PORT0(8 I/
O), PORT1 (8 I/O), PORT2 (8 I/O), PORT3 (8 I/O),
PORT4 (6 I/O). Pull-up resistor of each port can be selectable by program. Each port contains data direction register
which controls I/O and data register which stores port data
and can assign input state or output state to each bit. If
R0DD is ``1``, port R0 is in the output state, and if ``0``, it
is in the input state. R0DD is write-only register. Since
R0DD is initialized as ``00 h`` in reset state, the whole port
R0 becomes input state.
10.1 R0 Ports
(2) R0 Data Register (R0)
R0 is an 8-bit CMOS bidirectional I/O port (address
0C0H). Each I/O pin can independently used as an input or
an output through the R0DD register (address 0C1H).
R0 data register (R0) is 8-bit register to store data of port
R0. When set as the output state by R0DD, and data is written in R0, data is outputted into R0 pin. When set as the input state, input state of pin is read. The initial value of R0
is unknown in reset state.
R0 has internal pull-ups that is independently connected or
disconnected by R0PC. The control registers for R0 are
shown below.
R0 Data Register (R/W)
R0
ADDRESS : 0C0H
RESET VALUE : Undefined
R07 R06 R05 R04 R03 R02 R01 R00
R0 Direction Register (W)
ADDRESS : 0C1H
RESET VALUE : 00H
R0DD
Port Direction
0: Input
1: Output
R0 Pull-up Selection Register (W)
ADDRESS :0F8H
RESET VALUE : 00H
R0PC
Pull-up select
1: Without pull-up
0: With pull-up
R0 Open drain Assign Register (W) ADDRESS :0E4H
RESET VALUE : 00H
(3) R0 Open drain Assign Register (R0ODC)
R0 Open Drain Assign Register (R0ODC) is 8bit register,
and can assign R0 port as open drain output port each bit,
if corresponding port is selected as output. If R0ODC is
selected as ``1``, port R0 is open drain output, and if selected as ``0``, it is push-pull output. R0ODC is write-only
register and initialized as ``00 h`` in reset state.
(4) R0 Pull-up Resistor Control Register (R0PC)
R0 pull-up resistor control register (R0PC) is 8-bit register
and can control pull-up on or off each bit, if corresponding
port is selected as input. If R0PC is selected as ``1``, pullup ia disabled and if selected as ``0``, it is enabled. R0PC
is write-only register and initialized as ``00 h`` in reset
state. The pull-up is automatically disabled, if corresponding port is selected as output.
10.2 R1 Ports
R0ODC
Open drain select
0: Push-pull
1: Open drain
(1) R0 I/O Data Direction Register (R0DD)
R1 is an 8-bit CMOS bidirectional I/O port (address
0C2H). Each I/O pin can independently used as an input or
an output through the R1DD register (address 0C3H).
R1 has internal pull-ups that is independently connected or
disconnected by register R1PC. The control registers for
R1 are shown below.
R0 I/O Data Direction Register (R0DD) is 8-bit register,
28
Sep. 2001 Ver 1.0
HMS87C5216
R1 Data Register (R/W)
R1
ADDRESS : 0C2H
RESET VALUE : Undefined
R17 R16 R15 R14 R13 R12 R11 R10
R1 Direction Register (W)
ADDRESS : 0C3H
RESET VALUE : 00H
assign the selection mode for each bit. When set as ``0``,
corresponding bit of PMR1 acts as port R1 selection mode,
and when set as ``1``, it becomes function selection mode.
PMR1 is write-only register and initialized as ``00 h`` in
reset state. Therefore, becomes Port selection mode. Port
R1 can be I/O port by manipulating each R1DD bit, if corresponding PMR1 bit is selected as ``0``.
R1DD
Port Direction
0: Input
1: Output
Pin Name
R1 Pull-up Selection Register (W)
ADDRESS : 0F9H
RESET VALUE : 00H
R1PC
PMR1
Selection
Mode
Remarks
0
R25(I/O)
-
1
EC0(I)
EVENT COUNT0
0
R24(I/O)
-
1
T2(O)
TIMER2
0
R13 (I/O)
-
1
T1(O)
TIMER1
0
R12 (I/O)
-
1
T0(O)
TIMER0
0
R11 (I/O)
-
1
INT2(I)
EXT INT2
0
R10(I/O)
-
1
INT1(I)
EXT INT1
-
Pull-up select
1: Without pull-up
0: With pull-up
R1 Open drain Assign Register (W) ADDRESS : 0DEH
RESET VALUE : 00H
EC0
T2
P1ODC
Open drain select
0: Push-pull
1: Open drain
R1 Port Mode Register (W)
ADDRESS : 0C9H
RESET VALUE : 00H
T1
T0
PMR1
Mode select
0: Port R1 selection
1: Function selection
INT2
INT1
Table 10-1 Selection mode of PMR1
(1) R1 I/O Data Direction Register (R1DD)
R1 I/O Data Direction Register (R1DD) is 8-bit register,
and can assign input state or output state to each bit. If
R1DD is ``1``, port R1 is in the output state, and if ``0``, it
is in the input state. R1DD is write-only register. Since
R1DD is initialized as ``00 h`` in reset state, the whole port
R1 becomes input state.
(2) R1 Data Register (R1)
R1 data register (R1) is 8-bit register to store data of port
R1. When set as the output state by R1DD, and data is written in R1, data is outputted into R1 pin. When set as the input state, input state of pin is read. The initial value of R1
is unknown in reset state.
(3) R1 Mode Register (PMR1)
R1 Port Mode Register (PMR1) is 8-bit register, and can
Sep. 2001 Ver 1.0
(4) R1 Pull-up Resistor Control Register (R1PC)
R1 pull-up resistor control register (R1PC) is 8-bit register
and can control pull-up on or off each bit, if corresponding
port is selected as input. If R1PC is selected as ``1``, pullup ia disabled and if selected as ``0``, it is enabled. R1PC
is write-only register and initialized as ``00 h`` in reset
state. The pull-up is automatically disabled, if corresponding port is selected as output.
10.3 R2 Port
R2 is an 8-bit CMOS bidirectional I/O port (address
0C4H). Each I/O pin can independently used as an input or
an output through the R2DD register (address 0C5H).
29
HMS87C5216
R2 has internal pujll-ups that is independently connected
or disconnected by R2PC (address 0FAH). The control registers for R2 are shown as below.
R2 Data Register (R/W)
R2
ADDRESS : 0C4H
RESET VALUE : Undefined
R27 R26 R25 R24 R23 R22 R21 R20
R2 Direction Register (W)
ADDRESS : 0C5H
RESET VALUE : 00H
R2DD
Port Direction
0: Input
1: Output
R2 Pull-up Selection Register (W)
ADDRESS :0FAH
RESET VALUE : 00H
R2PC
Pull-up select
1: Without pull-up
0: With pull-up
R2 Open drain Assign Register (W) ADDRESS :0DFH
RESET VALUE : 00H
R2ODC
Open drain select
0: Push-pull
1: Open drain
and can assign input state or output state to each bit. If
R2DD is ``1``, port R2 is in the output state, and if ``0``, it
is in the input state. R2DD is write-only register. Since
R2DD is initialized as ``00 h`` in reset state, the whole port
R2 becomes input state.
(2) R2 Data Register (R2)
R2 data register (R2) is 8-bit register to store data of port
R2. When set as the output state by R2DD, and data is written in R2, data is outputted into R2 pin. When set as the input state, input state of pin is read. The initial value of R2
is unknown in reset state.
(3) R2 Open drain Assign Register (R2ODC)
R2 Open Drain Assign Register (R2ODC) is 8bit register,
and can assign R2 port as open drain output port each bit,
if corresponding port is selected as output. If R2ODC is
selected as ``1``, port R2 is open drain output, and if selected as ``0``, it is push-pull output. R2ODC is write-only
register and initialized as ``00 h`` in reset state.
(4) R2 Pull-up Resistor Control Register (R2PC)
R2 pull-up resistor control register (R2PC) is 8-bit register
and can control pull-up on or off each bit, if corresponding
port is selected as input. If R2PC is selected as ``1``, pullup ia disabled and if selected as ``0``, it is enabled. R2PC
is write-only register and initialized as ``00 h`` in reset
state. The pull-up is automatically disabled, if corresponding port is selected as output.
(1) R2 I/O Data Direction Register (R2DD)
R2 I/O Data Direction Register (R2DD) is 8-bit register,
30
Sep. 2001 Ver 1.0
HMS87C5216
R3 Port
R3 is an 8-bit CMOS bidirectional I/O port (address
0E5H). Each I/O pin can independently used as an input or
an output through the R3DD register (address 0E6H).
R3 has internal pull-ups that is independently connected or
disconnected by R3PC (address 0FBH). The control registers for R3 are shown as below.
R3 Data Register (R/W)
R3
ADDRESS : 0E5H
RESET VALUE : Undefined
R37 R36 R35 R34 R33 R32 R31 R30
R3 Direction Register (W)
ADDRESS : 0E6H
RESET VALUE : 00H
R3DD
Port Direction
0: Input
1: Output
R3 Pull-up Selection Register (W)
ADDRESS :0FBH
RESET VALUE : 00H
(1) R3 I/O Data Direction Register (R3DD)
R3 I/O Data Direction Register (R3DD) is 8-bit register,
and can assign input state or output state to each bit. If
R3DD is ``1``, port R3 is in the output state, and if ``0``, it
is in the input state. R3DD is write-only register. Since
R3DD is initialized as ``00 h`` in reset state, the whole port
R3 becomes input state.
(2) R3 Data Register (R3)
R3 data register (R3) is 8-bit register to store data of port
R3. When set as the output state by R3DD, and data is written in R3, data is outputted into R3 pin. When set as the input state, input state of pin is read. The initial value of R3
is unknown in reset state.
(3) R3 Open drain Assign Register (R3ODC)
R3 Open Drain Assign Register (R3ODC) is 8bit register,
and can assign R3 port as open drain output port each bit,
if corresponding port is selected as output. If R3ODC is
selected as ``1``, port R3 is open drain output, and if selected as ``0``, it is push-pull output. R3ODC is write-only
register and initialized as ``00 h`` in reset state.
R3PC
Pull-up select
1: Without pull-up
0: With pull-up
R3 Open drain Assign Register (W) ADDRESS :0E0H
RESET VALUE : 00H
R3ODC
Open drain select
0: Push-pull
1: Open drain
Sep. 2001 Ver 1.0
(4) R3 Pull-up Resistor Control Register (R3PC)
R3 pull-up resistor control register (R3PC) is 8-bit register
and can control pull-up on or off each bit, if corresponding
port is selected as input. If R3PC is selected as ``1``, pullup ia disabled and if selected as ``0``, it is enabled. R3PC
is write-only register and initialized as ``00 h`` in reset
state. The pull-up is automatically disabled, if corresponding port is selected as output.
31
HMS87C5216
R4 Port
R4 is an 1-bit CMOS bidirectional I/O port (address
0E7H). Each I/O pin can independently used as an input or
an output through the R4DD register (address 0E8H).
R3 has internal pull-ups that is independently connected or
disconnected by R4PC (address 0FCH). The control registers for R4 are shown as below.
ADDRESS : 0E7H
RESET VALUE : Undefined
R4 Data Register (R/W)
R4
R44 R43 R42 R41 R40
R4 Direction Register (W)
ADDRESS : 0E8H
RESET VALUE : 00H
R4DD
Port Direction
0: Input
1: Output
R4 Pull-up Selection Register (W)
ADDRESS :0FCH
RESET VALUE : 00H
(1) R4 I/O Data Direction Register (R4DD)
R4 I/O Data Direction Register (R4DD) is 1-bit register,
and can assign input state or output state to each bit. If
R4DD is ``1``, port R4 is in the output state, and if ``0``, it
is in the input state. R4DD is write-only register. Since
R4DD is initialized as ``00 h`` in reset state, the whole port
R4 becomes input state.
(2) R4 Data Register (R4)
R4 data register (R4) is 1-bit register to store data of port
R4. When set as the output state by R4DD, and data is written in R4, data is outputted into R4 pin. When set as the input state, input state of pin is read. The initial value of R4
is unknown in reset state.
(3) R4 Open drain Assign Register (R4ODC)
R4 Open Drain Assign Register (R4ODC) is 1-bit register,
and can assign R4 port as open drain output port each bit,
if corresponding port is selected as output. If R4ODC is
selected as ``1``, port R4 is open drain output, and if selected as ``0``, it is push-pull output. R4ODC is write-only
register and initialized as ``00 h`` in reset state.
R4PC
Pull-up select
1: Without pull-up
0: With pull-up
R4 Open drain Assign Register (W) ADDRESS :0E1H
RESET VALUE : 00H
R4ODC
Open drain select
0: Push-pull
1: Open drain
32
(4) R4 Pull-up Resistor Control Register (R4PC)
R4 pull-up resistor control register (R4PC) is 1-bit register
and can control pull-up on or off each bit, if corresponding
port is selected as input. If R4PC is selected as ``1``, pullup ia disabled and if selected as ``0``, it is enabled. R4PC
is write-only register and initialized as ``00 h`` in reset
state. The pull-up is automatically disabled, if corresponding port is selected as output.
Sep. 2001 Ver 1.0
HMS87C5216
11. CLOCK GENERATOR
Clock generating circuit consists of Clock Pulse Generator
(C.P.G), Prescaler, Basic Interval Timer (B.I.T) and Watch
fex
Dog Timer. The clock applied to the Xin pin divided by
two is used as the internal system clock.
fcpu
OSC
Circuit
Internal System Clock
C.P.G
PRESCALER
IFBIT
PS1
ENPCK
0
7
0
5
8
WDTCL
B.I.T (8)
MUX
WDT (6)
9
BTCL
IFWDT
COMPARATOR
3
WDTON
Peripheral
CKCTLR
0
1
2
3
4
6
WDTR
5
0
To Reset
Circuit
6
5
6
Internal Data Bus
Figure 11-1 Block Diagram of Clock Generator
Prescaler consists of 12-bit binary counter. The clock supplied from oscillation circuit is input to prescaler (fex).
PS1
fex
PS2
PS3
PS4
PS5
The divided output from each bit of prescaler is provided
to peripheral hardware.
PS6
PS7
PS8
PS9
PS10
PS11
PS12
ENPCK
B.I.T
fcpu
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10 PS11
PS12
Peripheral
Figure 11-2 Block diagram of Prescaler
Sep. 2001 Ver 1.0
33
HMS87C5216
fex (MHz)
ps 0
ps 1
ps 2
ps 3
ps 4
ps 5
ps 6
ps 7
ps 8
ps 9
ps 10
ps 11
ps 12
4 MHz
frequency
4 MHz
2 MHz
1 MHz
500 KHz
250 KHz
125 KHz
62.5 KHz
31.25 KHz
15.63 KHz
7.183 KHz
3.906 KHz
1.953 KHz
0.976 KHz
2 MHz
period
250 ns
500 ns
1 us
2 us
4 us
8 us
16 us
32 us
64 us
128 us
256 us
512 us
1024 us
frequency
2 MHz
1 MHz
500 KHz
250 KHz
125 KHz
62.5 KHz
31.25 KHz
15.63 KHz
7.183 KHz
3.906 KHz
1.953 KHz
0.976 KHz
0.488 KHz
period
500 ns
1 us
2 us
4 us
8 us
16 us
32 us
64 us
128 us
256 us
512 us
1024 us
2048 us
Table 11-1 ps output period
lock to peripheral hardware can be stopped by bit4 (ENPCK) of CKCTLR Register. ENPCK is set to ``1`` in reset
state.
34
Sep. 2001 Ver 1.0
HMS87C5216
12. Timer
12.1 Basic Interval Timer
The GMS81C5016/24/32 has one 8-bit Basic Interval Timer that is free-run and can not stop. Block diagram is shown
in Figure 12-1 .
-8bit binary counter
-Use the bit output of prescaler as input to secure the oscillation stabilization time after power-on
The Basic Interval Timer generates the time base for key
scanning, watchdog timer counting, and etc. It also provides a Basic interval timer interrupt (IFBIT). As the count
overflow from FFH to 00H, this overflow causes the interrupt to be generated.
-Secures the oscillation stabilization time in standby mode
(stop mode) release
-Contents of B.I.T can be read
-Provides the clock for watch dog timer.
DATA BUS
-
-
WDTON
ENPCK
BTCL
BTS2
BTS1
BTS0
CKCTLR
PS3
PS4
PS5
BITR
PS6
MUX
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
IFBIT
PS7
PS8
DATA BUS
PS9
PS10
Figure 12-1 Block Diagram of Basic Interval Timer
(1) Control of B.I.T
The Basic Interval Timer is controlled by the clock control
register (CKCTLR) shown in Figure 12-2 . If bit3(BTCL)
of CKCTLR is set to ``1``, B.I.T is cleared, and then, after
Sep. 2001 Ver 1.0
one machine cycle, BTCL becomes ``0``, and B.I.T starts
counting. BTCL is set to ``0`` in reset state.
35
HMS87C5216
Clock Control Register
7
CKCTLR
-
-
WDTON
ENPCK
BTCL
0
BTS2
BTS1
BTS0
BTCL
Periphral clock
0
free-run
1
W <00C7 h>
Automatically cleared, after one cycle
Figure 12-2 BTCL mode of B.I.T
(2) Input clock selection of B.I.T
The input clock of B.I.T can be selected from the prescaler
within a range of 2us to 256us by clock input selection bits
(BTS2~BTS0). (at fex = 4MHz). In reset state, or power
on reset, BTS2=``1``, BTS1=``1``, BTS0=``1`` to secure
the longest oscillation stabilization time. B.I.T can gener-
Figure 12-3 .
Clock Control Register
7
CKCTLR
ate the wide range of basic interval time interrupt request
(IFBIT) by selecting prescaler output. Interrupt interval
can be selected to kinds of interval time as shown in
ENPCK
BTCL
0
-
-
WDTON
BTS2
BTS1
BTS0
BTS2
BTS1
BTS0
B.I.T. Input clock
Standby release time
0
0
0
PS3 (2us)
512 us
0
0
1
PS4 (4us)
1,024 us
0
1
0
PS5 (8us)
2,048 us
0
1
1
PS6 (16us)
4,096 us
1
0
0
PS7 (32us)
8,192 us
1
0
1
PS8 (64us)
16,384 us
1
1
0
PS9 (128us)
32,768 us
1
1
1
PS10 (256us)
65,536 us
W <00C7 h>
Figure 12-3 Basic Interval Timer Interrupt Time
(3) Reading Basic Interval Timer
By reading of the Basic Interval Timer Register (BITR),
we can read counter value of B.I.T. Because B.I.T can be
36
cleared or read, the spending time up to maximum 65.5ms
can be available. B.I.T is read-only register. If B.I.T reg-
Sep. 2001 Ver 1.0
HMS87C5216
ister is written, then CKCTLR register with same address
Basic Interval Timer Register
7
BITR
BIT7
is written.
BIT6
BIT5
BIT4
BIT3
BIT2
0
BIT1
BIT0
R <00C7 h>
12.2 Timer0, Timer1, Timer2
(1) Timer Operation Mode
Timer consists of 16bit binary counter Timer0 (T0), 8bit
binary Timer1 (T1), Timer2 (T2), Timer Data Register,
Timer Mode Register (TM01, TM0, TM1, TM2) and control circuit. Timer Data Register Consists of Timer0 HighMSB Data Register (T0HMD), Timer0 High-LSB Data
Register (T0HLD), Timer0 Low-MSB Data Register
(T0LMD), Timer0 Low-LSB Data Register (T0LLD),
Timer0
- 16-bit Interval Timer
- 16-bit Event Counter
- 16-bit Input Capture
- 16-bit rectangular-wave output
Timer1
- 8-bit Interval Timer
- 8-bit rectangular-wave output
Timer2
- 8-bit Interval Timer
- 8-bit rectangular-wave output
- Modulo-N Mode
Sep. 2001 Ver 1.0
Timer1 High Data Register (T1HD), Timer1 Low Data
Register (T1LD), Timer2 Data Register (T2DR). Any of
the PS0 ~ PS5, PS11 and external event input EC can be
selected as clock source for T0. Any of the PS0 ~ PS3, PS7
~ PS10 can be selected as clock T1. Any of the PS5 ~ PS12
can be selected as clock source for T2.
* Relevant Port Mode Register (PMR1 : 00C9 h) value
should be assigned for event counter,
- Single/Modulo-N Mode
- Timer Output Initial Value Setting
- Timer0~Timer1 combination Logic Output
- One Interrupt Generating Every 2nd
Counter Overflow
37
HMS87C5216
EC / R14
INT2 / R12
(Capture
Signal)
Polarity
Selection
TIMER0 (16 BIT)
16
EDGE
Selection
16
8
8
T0HMD
T0HLD
T1HD
T1LD
8
8
T0LMD
T0LLD
Tout LOGIC
8
T0 OUT / R17
REMOUT
8
TIMER1 (8 BIT)
T1 OUT / R16
TIMER2 (8 BIT)
T2 OUT / R15
T2DR
Figure 12-4 Timer / Counter Block diagram
(2) Function of Timer & Counter
fex = 4MHz
16bit Timer (T0)
8bit Timer (T2)
Resolution (CK)
Max. Count
Resolution (CK)
Max. Count
PS0 ( 0.25 us)
16,384 us
PS0 ( 0.25 us)
64 us
PS5 (
8 us)
2.048 us
PS1 ( 0. 5 us)
32,768 us
PS1 (
0.5 us)
128 us
PS6 (
16 us)
4,096 us
PS2 (
1 us)
65,536 us
PS2 (
1 us)
256 us
PS7 (
32 us)
8,192 us
PS3 (
2 us)
131,072 us
PS3 (
2 us)
512us
PS8 (
64 us)
16,384 us
PS4 (
4 us)
262,144 us
PS7 (
32 us)
8,192 us
PS9 ( 128 us)
32,768 us
PS5 (
8 us)
524,288 us
PS8 (
64 us)
16,384 us
PS10 ( 256 us)
65,536 us
PS11 ( 512 us)
33,554,432 us
PS9 ( 128 us)
32,768 us
PS11 ( 512 us)
131,072 us
PS10 ( 256 us)
65,536 us
PS12 (1,024 us)
262,144 us
EC
38
8bit Timer (T1)
-
Resolution (CK)
Max. Count
Sep. 2001 Ver 1.0
HMS87C5216
Internal Data Bus
<00D5 h>
R/W
<00D0 h>
TM0
7
6
5
4
3
2
1
0
TIMER0 H
COUNT
REG
<00D6 h>
<00D3 h>
TIMER0
HM
DATA
REG
TIMER0 L
COUNT
REG
<00D4 h>
TIMER0
HL
DATA
REG
<00D5 h>
TIMER0
LM
DATA
REG
<00D6 h>
TIMER0
LL
DATA
REG
DATA READ
SINGLE/
MODULO-N
SELECTION
16
16
MUX
16
PS0
PS1
CK
PS2
PS3
Int.
Gen.
MUX
T0 COUNTER
(16 BIT)
PS4
PS5
PS11
D
EC
E
M
U
X
IFT0
Clear
L
A
INT2
EDGE
SELECTION
Y
T0INT
OUTPUT GEN.
T0 OUT
Figure 12-5 Block Diagram of Timer0
Sep. 2001 Ver 1.0
39
HMS87C5216
Internal Data Bus
<00D7 h>
<00D8 h>
<00D8 h>
<00D1h>
TM1
7
6
5
4
3
2
1
0
R/W
TIMER1
H
DATA
REG
TIMER1
COUNT REG
X
TIMER1
L
DATA
REG
SINGLE/
MODULO-N
SELECTION
OUTPUT GEN.
PS0
PS1
CK
PS2
PS3
Int.
T1 COUNTER
(8 BIT)
MUX
PS7
Gen.
PS8
PS9
IFT1
PS10
T1INT
OUTPUT GEN.
T1OUT
Figure 12-6 Block Diagram of Timer1
40
Sep. 2001 Ver 1.0
HMS87C5216
Internal Data Bus
<00D9 h>
<00D9 h>
<00D2 h>
TM2
7
6
5
4
3
2
1
0
R/W
TIMER2
COUNT REG
TIMER2
DATA REG
PS5
PS6
CK
PS7
PS8
PS9
MUX
IFT2
T2 COUNTER
(8 BIT)
PS10
PS11
PS12
OUTPUT GEN.
T2 OUT
Figure 12-7 Block Diagram of Timer2
Sep. 2001 Ver 1.0
41
HMS87C5216
Timer0 / Timer1 Mode Register
7
TM01
TOUTS
TOUTB
-
T0OUTP
T0INIT
T1INIT
0
TOUT1
TOUT0
TOUT0
TOUT1
TOUT LOGIC
0
0
AND of T0 OUTPUT and T1 OUTPUT
0
1
NAND of T0 OUTPUT and T1 OUTPUT
1
0
OR of T0 OUTPUT and T1 OUTPUT
1
1
NOR of T0 OUTPUT and T1 OUTPUT
T1INIT
Timer1 Output Initial Value
0
Timer1 output low
1
Timer1 output high
T0INIT
Timer0 Output Initial Value
0
Timer0 Output Low
1
Timer0 Output High
T0OUTP
T0OUT Polarity Selection
0
T0OUT polarity equal to TOUT logic input signal
1
T0OUT polarity reverse to TOUT logic input signal
TOUTB
REMOUT Port Bit Control
0
REMOUT output low
1
REMOUT output high
TOUTS
R / W <00DA h>
REMOUT Port Output Selection
(TOUT logic or TOUTB)
0
Bit (TOUTB) output through REMOUT
1
TOUT logic output through REMOUT
Figure 12-8 Timer0 / Timer1 Mode Register
42
Sep. 2001 Ver 1.0
HMS87C5216
Timer0 Mode Register
7
TM0
CAP0
T0ST
T0CN
T0MOD
T0IFS
0
T0SL2
T0SL1
T0SL0
R / W <00D0 h>
T0SL2
T0SL1
T0SL0
0
0
0
PS0 (250ns)
0
0
1
PS1 (500ns)
0
1
0
PS2 (
1us)
0
1
1
PS3 (
2us)
1
0
0
PS4 (
4us)
1
0
1
PS5 (
8us)
1
1
0
PS11 (512us)
Event
1
1
1
EC
Counter
T0IFS
Input clock selection
*
Timer0 Interrupt Selection
0
Interrupt every counter overflow
1
Interrupt every 2nd counter overflow
Timer0 Single/Modulo-N Selection
T0MOD
0
Modulo-N
1
Single
T0CN
Notes
Timer0 Counter Continuation/Pause Control
0
Count pause
1
Count contination
Timer0 Start/Stop Control
T0ST
0
Timer0 Stop
1
Timer Start after clear
Timer0 Interrupt Selection
CAP0
0
Timer/Counter
1
Input capture *
* PS1 : not supporting input capture.
Figure 12-9 Timer0 Mode Register
Sep. 2001 Ver 1.0
43
HMS87C5216
Timer1 Mode Register
7
TM1
T1ST
T1CN
T1MOD
0
T1IFS
-
T1SL2
T1SL1
T1SL0
0
0
0
PS0 (250ns)
0
0
1
PS1 (500ns)
0
1
0
PS2 (
1us)
0
1
1
PS3 (
2us)
1
0
0
PS7 ( 32us)
1
0
1
PS8 ( 64us)
1
1
0
PS9 (128us)
1
1
1
PS10 (256us)
T1IFS
T1SL2
T1SL1
Timer1 Interrupt Selection
Interrupt every counter overflow
1
Interrupt every 2nd counter overflow
Timer1 Single/Modulo-N Selection
0
Modulo-N
1
Single
T1CN
Timer1 Counter Continuation/Pause Control
0
Count pause
1
Count contination
T1ST
R / W <00D1 h>
Input clock selection
0
T1MOD
T1SL0
Timer1 Start/Stop Control
0
Timer1 Stop
1
Timer1 Start after clear
Figure 12-10 Timer1 Mode Register
44
Sep. 2001 Ver 1.0
HMS87C5216
Timer2 Mode Register
7
TM2
-
-
-
T2ST
T2CN
0
T2SL2
T2SL1
T2SL2
T2SL1
T2SL0
0
0
0
PS5
(
0
0
1
PS6
( 16us)
0
1
0
PS7
( 32us)
0
1
1
PS8
( 64us)
1
0
0
PS9
( 128us)
1
0
1
PS10 ( 256us)
1
1
0
PS11 ( 512us)
1
1
1
PS12 (1024us)
T2CN
T2SL0
R / W <00D2 h>
Input clock selection
8us)
Timer2 Counter Continuation/Pause Control
0
Count pause
1
Count contination
Timer2 Start/Stop Control
T2ST
0
Timer2 Stop
1
Timer2 Start after clear
Figure 12-11 Timer2 Mode Register
7
IEDS
External Interrupt Signal Edge Selection Register
-
-
IED2H
IED2L
IED1H
IED1L
-
IED*H
IED*L
INT*
0
0
-
0
1
Falling Edge Selection
1
0
Rising Edge Selection
1
1
Both Edge Selection
0
-
W <00CB h>
Figure 12-12 External Interrupt Signal Edge Selection Register
Sep. 2001 Ver 1.0
45
HMS87C5216
(3) Timer0, Timer1
TIMER0 and TIMER1 have an up-counter. When value of
the up-counter reaches the content of Timer Data Register
Concurrence
T0 Data
Registers
Value
(TDR), the up-counter is cleared to ``00 h``, and interrupt
(IFT0, IFT1) is occured at the next clock.
Concurrence
Concurrence
T0 Value
0
CLEAR
CLEAR
INTERRUPT
CLEAR
INTERRUPT
INTERRUPT
IFT0
Interval period
Figure 12-13 Operatiion of Timer0
For Timer0, the internal clock (PS) and the external clock
(EC) can be selected as counter clock. But Timer1 and
Timer2 use only internal clock. As internal clock. Timer0
can be used as internal-timer which period is determined
by Timer Data Register (TDR). Chosen as external
clock, Timer0 executes as event-counter. The counter execution of Timer0 and Timer1 is controlled by T0CN,
T0ST, CAP0, T1CN, T1ST, of Timer Mode Register TM0
and TM1. T0CN, T1CN are used to stop and start Timer0
and Timer1 without clearing the counter. T0ST, T1ST is
used to clear the counter. For clearing and starting the
counter, T0ST or T1ST should be temporarily set to ``0``
and then set to ``1``. T0CN, T1CN, T0ST and T1ST
should be set ``1``, when Timer counting-up. Controlling
of CAP0 enables Timer0 as input capture. By programming of CAP0 to ``1``, the period of signal from INT2 can
be measured and then, event counter value for INT2 can
be read. During counting-up, value of counter can be read.
Timer execution is stopped by the reset signal (RESET
46
= ``L``)
Note: In the process of reading 16-bit Timer Data, first
read the upper 8-bit data. Then read the lower 8-bit data,
and read the upper 8-bit data again. If the earlier read upper 8-bit data are matched with the later read upper 8-bit
data, read 16-bit data are correct. If not, caution should be
taken in the selection of upper 8-bit data.
(Example)
1) Upper 8-bit Read 0A 0A
2) Lower 8-bit Read FF 01
3) Upper 8-bit Read 0B 0B
=====================
-
-
0AFF 0B01
Sep. 2001 Ver 1.0
HMS87C5216
T0 Data
Register
Value
Concurrence
Concurrence
CLEAR
CLEAR
T0 Value
0
INTERRUPT
INTERRUPT
IFT0
0
T0ST
1
Clear & Start
0
T0CN
1
Counter
Stop
Count
Clear
& Count
Stop
Count Clear & Start
continue
Figure 12-14 Start/Stop operation of Timer0
T3
T2
T1
T0
INT2
Figure 12-15 Input capture operation of Timer0
Sep. 2001 Ver 1.0
47
HMS87C5216
* Single/Modulo-N Mode
Timer0 (Timer1) can select initial (T0INIT, T1INIT of
TM01) output level of Timer Output port. If initial level is
``L``, Low-Data Register value of Timer Data Register is
transferred to comparator and T0OUT (T1OUT) is to be
``Low``, if initial level is High? High -Data Register is
transferred and to be ``High``. Single Mode can be set by
Mode Select bit (T0MOD, T1MOD) of Timer Mode Register (TM0, TM1) to ``1`` When used as Single Mode,
Timer counts up and compares with value of Data Register. If the result is same, Time Out interrupt occurs and
level of Timer Output port toggle, then counter stops as reset state. When used as Modulo-N Mode, T0MOD
(T1MOD) should be set ``0``. Counter counts up until the
value of Data Register and occurs Time-out interrupt. The
level of Timer Output port toggle and repeats process of
counting the value which is selected in Data Register.
During Modulo-N Mode, If interrupt select bit (T0IFS,
T1IFS) of Mode Register is ``0``, Interrupt occurs on every Time-out. If it is ``1``, Interrupt occurs every second
time-out.
(*note. Timer Output is toggled whenever time
Note:
out happen)
[ Single Mode ]
8bit / 16bit
counting
Timer Enable initial.
value toggle.
Timer-output toggle.
interrupt occurs.
count stop.
[ Modulo-N Mode ]
8bit / 16bit
counting
Timer Enable initial.
value toggle.
Timer-Output Toggle.
Int occurs (IFS = 1) Each 2nd time out.
Int occurs (IFS = 0) When Time out.
Figure 12-16 Operation Diagram for Single/Modulo-N Mode
(4) Timer 2
Timer2 operates as a up-counter. The content of T2DR are
compared with the contents of up-counter. If a match is
found. Timer2 interrupt (IFT2) is generated and the upcounter is cleared to ``00 h``. Therefore, Timer2 executes
as a interval timer. Interrupt period is determined by the
count source clock for the Timer2 and content of T2DR.
48
When T2ST is set to ``1``, count value of Timer 2 is
cleared and starts counting-up. For clearing and starting
the Timer2. T2ST have to set to ``1`` after set to ``0``. In
order to write a value directly into the T2DR, T2ST should
be set to ``0``. Count value of Timer2 can be read at any
time.
Sep. 2001 Ver 1.0
HMS87C5216
T2 Data
Registers
Value
Concurrence
Concurrence
Concurrence
T2 Value
0
CLEAR
CLEAR
INTERRUPT
INTERRUPT
CLEAR
INTERRUPT
IFT0
Interval period
Figure 12-17 Operation of Timer2
T2 Data
Register
Value
Concurrence
Concurrence
CLEAR
CLEAR
T2 Value
0
INTERRUPT
INTERRUPT
IFT2
T2ST
count stop by 0
count start clear by 1
Counter
Count up
Count Stop
Count
continue
Count up after clear
Figure 12-18 Start/Stop of Timer2
Sep. 2001 Ver 1.0
49
HMS87C5216
13. INTERRUPTS
- 8 interrupt vector
The GMS81C5016/24/32 interrupt circuits consist of Interrupt Mode Register (MOD), Interrupt enable register
(IENH, IENL), Interrupt request flags of IRQH, IRQL,
Priority circuit and Master enable flag ("I" flag of PSW). 8
interrupt sources are provided. The configuration of interrupt circuit is shown in Figure 13-1 .
- Nested interrupt control is possible
- Programmable interrupt mode
- Hardware accept mode
- Software selection accept mode
The GMS81C5016/24/32 contains 8 interrupt sources; 3
externals and 5 internals. Nested interrupt services with
priority control is also possible. Software interrupt is nonmaskable interrupt, the others are all maskable interrupts.
- Read and write of interrupt request flag are possible.
- In interrupt accept, request flag is automatically cleared.
- 8 interrupt source (2Ext, 3Timer, BIT, WDT and Key
Scan)
Internal Data Bus
0
-
KSCN
KSCNR
INT1
INT1R
INT2
INT2R
IFT0
T0R
IFT1
T1R
IFT2
T2R
IFWDT
IFBIT
-
-
IENL
7
0
IENH
-
-
-
-
-
7
0
IMOD
7
-
-
INT.
VECTOR
ADDR.
PRIORITY
CONTROL
WDTR
BRK
BITR
IRQ
Standby Mode Release
Figure 13-1 Block Diagram of Interrupt
13.1 Interrupt priority and sources.
Each interrupt vector is independent and has its own priority. Software interrupt (BRK) is also available. Interrupt
50
source classification is shown in Table 13-1.
Sep. 2001 Ver 1.0
HMS87C5216
Hardwar
e
Interrupt
Mask
Priority
non-maskable
-
maskable
-
Interrupt Source
INT Vector High
INT Vector Low
RST (RESET pin)
FFFF
FFFE
0
KSCNR (Key Scan)
FFFB
FFFA
1
INT1R (External Interrupt1)
FFF9
FFF8
2
INT2R (External Interrupt2)
FFF7
FFF6
3
T0R (Timer0)
FFF3
FFF2
4
T1R (Timer1)
FFF1
FFF0
5
T2R (Timer2)
FFEF
FFEE
6
WDTR (Watctdog Timer)
FFE9
FFE8
7
BITR (Basic Interval Timer)
FFE7
FFE6
-
BRK instruction
FFDF
FFDE
Table 13-1 Interrupt Priority & Source
13.2 INTERRUPT CONTROL REGISTER
I flag of PSW is a interrupt mask enable flag. When I flag
= ``0``, all interrupts become disable. When I flag = ``1``,
interrupts can be selectively enabled and disabled by contents of corresponding Interrupt Enable Register. When interrupt is occured, interrupt request flag is set, and
Interrupt request is detected at the edge of interrupt signal.
The accepted interrupt request flag is automatically cleared
R/W <00CCh>
IEN L
IENH
-
WDTR
BITE
-
-
-
-
-
KSCNE
INT1E
INT2E
-
T0E
T1E
T2E
-
-
WDTR
BITE
-
-
-
-
-
KSCNE
INT1R
INT2R
-
T0R
T1R
T2R
-
IRQL
IRQH
during interrupt cycle process. The interrupt request flag
maintains ``1`` until the interrupt is accepted or is cleared
in program. In reset state, interrupt request flag register
(IRQH, IRQL) is cleared to ``0``. It is possible to read the
state of interrupt register and to mainpulate the contents of
register and to generate interrupt. (Refer to software interrupt).
R/W <00CEh>
R/W <00CDh>
R/W <00CFh>
IENL : INTERRUPT ENABLE REGISTER LOW
IENH : INTERRUPT ENABLE REGISTER HIGH
IRQL : INTERRUPT REQUEST REGISTER LOW
IRQH : INTERRUPT REQUEST REGISTER HIGH
Sep. 2001 Ver 1.0
51
HMS87C5216
13.3 INTERRUPT ACCEPT MODE
The interrupt priority order is determined by bit (IM1,
Interrupt Mode Register
7
IMOD
IM0) of IMOD register.
-
-
IM1
IM0
IP3
0
IP2
IP1
IP0
R/W <00CA h>
Assigning by interrupt accept mode bit
IM1
IM0
Priority
0
0
fixed by hardware
0
1
changeable by IP3~ IP0
1
*
Interrupt is inhibited
(1) Selection of Interrupt by IP3-IP0
The condition allow for accepting interrupt is set state of
the interrupt mask enable flag and
the interrupt enable bit must be ``1``. In Reset state, these
IP3 - IP0 registers become all ``0``.
IP3
IP2
IP1
IP0
Selection Interrupt
0
0
0
1
KSCNR (Key Scan)
0
0
1
0
INT1R (External interrupt 1)
0
0
1
1
INT2R (External interrupt 2)
0
1
0
0
Reserved
0
1
0
1
T0R (Timer 0)
0
1
1
0
T1R (Timer 1)
0
1
1
1
T2R (Timer 2)
1
0
0
0
Reserved
1
0
0
1
Reserved
1
0
1
0
WDTR (Watch Dog Timer)
1
0
1
1
BITR (Basic Interval Timer)
1
1
0
0
Reserved
Table 13-2 Interrupt Selection by IP3 - IP0
52
Sep. 2001 Ver 1.0
HMS87C5216
(2) Interrupt Timing
CLOCK
A command before interrupt
interrupt process step
SYNC
Interrupt Request Sampling
Figure 13-2 Interrupt Enable Accept Timing
*Interrupt Request sampling time
-Maximum 12 machine cycle (When execute DIV
instruction)
-Minimum 0 machine cycle
*Interrupt preprocess step is 8 machine cycle
*Interrupt overhead
-Maximum 1 + 12 + 8 = 21 machine cycle
-Minimum 1 + 0 + 8 = 9 machine cycle
(3) The valid timing after executing Interrupt control instructions
I flag is valid just after executing of EI/DI on the contrary.
Interrupt Enable register is valid one instruction after con-
trolling interrupt Enable Register.
13.4 INTERRUPT PROCESSING SEQUENCE
When an interrupt is accepted, the on-going process is
stopped and the interrupt service routine is executed. After
the interrupt service routine is completed it is necessary to
restore everything to the state before the interrupt occured.As soon as an interrupt is accepted, the content of the
program counter and PSW are savedin the stack area. At
the same time, the content of the vector address corresponding to the accepted interrupt, which is in the interrupt
vector table, enters into the program counter and interrupt
service is executed. In order to execute the interrupt service routine, it is necessary to write the jump addresses in
the vector table (FFE0 h ~ FFFF h) corresponding to each
interrupt
Sep. 2001 Ver 1.0
* Interrupt Processing Step
1) Store upper byte of Program Counter, SP <= SP
2) Store lower byte of Program Counter, SP <= SP - 1
3) Store Program Status Word, SP <= SP - 2
4) After resetting of I-flag, clear accepted Interrupt Request Flag. (Set B-flag for BRK Instruction)
5) Call Interrupt service routine
53
HMS87C5216
clock
Interrupt Process Step
ISR
*1
SYNC
R/W
internal
addr bus
PC
internal
data bus
æ
OP
CODE
SP
æ
OP
CODE
SP-1
æ
PCH
SP-2
æ
æ
PCL
*2
*3
LVA
HVA
æ
PSW
new PC
æ
``L``
vector
``H``
vector
internal
READ
*1 ISR
*2 LVA
*3 HVA
internal
WRITE
: Interrupt Service
Routine
: Low Vector Address
: High Vector Address
Figure 13-3 Interrupt Procesing Step Timing
13.5 SOFTWARE INTERRUPT (Interrupt by Break (BRK) Instruction)
S o f t w ar e in t e r r u p t i s a v ai l ab l e j u s t b y w r i t in g
``Break(BRK)`` instruction. The values of PC and PSW is
stacked by BRK instruction and then B flag of PSW is set
and I flag is reset.
Flag change by BRK execution
PSW
N
V
G
B
PSW
N
V
G
1
H
I
H
0
set
Z
C
Z
C
reset
(Right after BRK execution)
Interrupt vector of BRK instruction is shared by vector of
Table Call (TCALL0). When both instruction of BRK and
TCALL0 are used, as shown in Figure 13-4 each process-
54
ing routine is judged by contents of B flag. There is no instruction to reset directly B flag.
Sep. 2001 Ver 1.0
HMS87C5216
0
B flag
1
BRK or
TCALL0
BRK INTERRUPT ROUTINE
TCALL0 ROUTINE
RETI
RET
Figure 13-4 Execution of BRK or TCALL0
13.6 MULTIPLE INTERRUPT
If there is an interrupt, Interrupt Mask Enable Flag is automatically cleared before entering the Interrupt Service
Routine. After then, no interrupt is accepted. If EI instruction is executed, interrupt mask enable bit becomes ``1``,
and each enable bit can accept interrupt request. When two
or more interrupts are generated simultaneously, the highest priority interrupt set by Interrupt Mode Register is accepted.
13.7 Key Scan Input Processing
(1) Standby Mode Release Register (SMRR)
Key Scan Interrupt is generated by detecting low or high
Input from each Input pin (R0, R1) is one of the sources
which release standby (SLEEP, STOP) mode. Key Scan
ports are all 16bit which are controlled by Standby Mode
Release Register (SMRR0, SMRR1). Key Input is considered as Interrupt, therefore, KSCNE bit of IEHN should be
Sep. 2001 Ver 1.0
set for correct interrupt executing, SLEEP mode and STOP
mode, the rest of executing is the same as that of external
Interrupt. Each SMRR Register bit is allowed for each port
(for Bit= ``0``, no Key Input, for Bit= ``1``, Key Input
available). At reset, SMRR becomes ``00 h``. So, there is
no Key Input source.
55
HMS87C5216
7
0
W <00DC h>
SMRR0
Internal
Key Scan
Interrupt
R00
R01
.
.
.
R07
R0 port
Selection Logic
7
0
W <00DD h>
SMRR1
R10
R11
.
.
.
R17
R0 port
Selection Logic
Figure 13-5 Key Scan Block
SMRR0 Register
7
SMRR0
KR07
KR06
KR05
SMRR1
56
KR03
0
KR02
KR01
KR00
KR12
KR11
KR10
SMRR1 Register
7
KR17
KR04
KR16
KR15
KR14
KR13
W <00DC h>
0
W <00DD h>
Sep. 2001 Ver 1.0
HMS87C5216
SMRR0
SMRR1
0
KR07
Key Input Selection
0
no select
1
select
0
no select
1
select
0
no select
1
select
0
no select
1
select
0
no select
1
select
0
no select
1
select
0
no select
1
select
0
no select
1
select
KR17
1
0
KR16
KR06
1
0
KR15
KR05
1
0
KR04
KR14
1
0
KR03
KR13
1
0
KR12
KR02
1
0
KR11
KR01
1
0
KR10
KR00
1
(2) Standby Release Level Control Register (SRLC)
Standby release level control register (SRLC) can select
the key scan input level ``L`` or ``H`` for standby release
by each bit pin (R0, R1). Standby release level control reg-
SRLC0 Register
7
SRLC0
KLR07
KLR06
KLR05
Sep. 2001 Ver 1.0
KLR17
KLR04
KLR03
0
KLR02
KLR01
KLR00
KLR12
KLR11
KLR10
SRLC1 Register
7
SRLC1
ister (SRLC) is write-only register and initialized as ``00
h`` in reset state.
KLR16
KLR15
KLR14
KLR13
W <00F6 h>
0
W <00F7 h>
57
HMS87C5216
SRLC0
SRLC1
0
KLR07
0
Low
1
High
0
Low
1
High
0
Low
1
High
0
Low
1
High
0
Low
1
High
0
Low
1
High
0
Low
1
High
0
Low
1
High
KLR17
1
0
KLR16
KLR06
1
0
KLR15
KLR05
1
0
KLR04
KLR14
1
0
KLR03
KLR13
1
0
KLR12
KLR02
1
0
KLR11
KLR01
1
0
KLR10
KLR00
1
58
Key Input Level
Sep. 2001 Ver 1.0
HMS87C5216
14. WATCH DOG TIMER
Watch Dog Timer (WDT) consists of 6-bit binary counter,
6-bit comparator, and Watch Dog Timer Register
(WDTR).
0
5
CLR
IFBIT
WDT0
WDT1
WDT2
WDT3
WDT4
WDTON
WDT5
To Reset circuit
6BIT COMPARATOR
IF WDT
WDTR
WDTR0
WDTR1
WDTR2
WDTR3
WDTR4
WDTR5
0
WDTCL
W <00C8 h>
6
Internal Data Bus
Figure 14-1 Block diagram of Watch Dog Timer
14.1 Control of WDT
Watch Dog Timer can be used 6-bit general Timer or specific Watch dog timer by setting
Clock Control Register
7
CKCTLR
-
-
WDTON
ENPCK
BTCL
BTS2
0
BTS1
WDTON
Watch Dog Timer Function Control
0
6-bit Timer
1
Watch Dog Timer
By assigning bit6(WDTCL) of WDTR, 6-bit counter can
Sep. 2001 Ver 1.0
bit5 (WDTON) of Clock Control Register (CKCTLR).
BTS0
W <00C7 h>
be cleared.
59
HMS87C5216
Watch DOG Timer Register
7
WDTR
-
WDTCL
WDTR5
WDTR4
WDTR3
WDTR2
0
WDTR1
WDTR0
W <00C8 h>
Determine Interval of IFWDT
Interval of IFWDT = Value of WDTR Ý Interval of IFBIT
WDTCL
Watch Dog Timer Operation
0
free-run
1
Automatically cleared, after one machine cycle
14.2 WDT Interrupt Interval
WDT Interrupt (IFWDT) interval is determined by the interrupt IFBIT interval of Basic Interval Timer and the value of WDT Register.
-Interval of IFWDT = (IFBIT interval) * (WDTR value)
*At Hardware reset time ,WDT starts automatically.
Therefore, the user must select the CKCTLR, WDTR before WDT overflow.
-Interval of IFWDT : 512 us * 1 = 512 us (MIN>)
-Reset WDTR value = 0F h,15
-65,536us * 63 = 4,128,768 us (MAX>)
-interval of WDT = 65,536 * 15 = 983040 us
As IFBIT (Basic Interval Timer Interrupt Request) is used
for input clock of WDT, Input clock cycle is possible from
512 us to 65,536 us by BTS. (at fex = 4MHz)
60
(about 1second )
Sep. 2001 Ver 1.0
HMS87C5216
Clock Control Register
7
CKCTLR
ENPCK
BTCL
BTS2
0
-
-
WDTON
BTS1
BTS0
BTS2
BTS1
BTS0
WDT Input clock
0
0
0
512 us
32,756 us
0
0
1
1,024 us
64,512 us
0
1
0
2,048 us
129,024 us
0
1
1
4,096 us
258,048 us
1
0
0
8,192 us
516,096 us
1
0
1
16,384 us
1,032,192 us
1
1
0
32,768 us
2,064,384 us
1
1
1
65,536 us
4,128,768 us
W <00C7 h>
Max. Interval of WDT
Output (*note1)
Device come into the reset state by WDT
N o t e : W h en W D T R R eg i st e r v al u e is 6 3 ( 3F h )
(Caution) : Do not use ``0`` for WDTR Register value.
Sep. 2001 Ver 1.0
61
HMS87C5216
15. STANDBY FUNCTION
To save power consumption, there is STOP modes. In this
modes, the execution of program stops.
15.1 Sleep Mode
release SLEEP mode by BITR (basic interval timer interrupt), bit10 of prescaler should be selected as B.I.T input
clock before entering SLEEP mode. ``NOP`` instruction
should be follows setting of SLEEP mode for rising precharge time of data bus line.
SLEEP mode can be entered by setting the bit of SLEEP
mode register (SLPM). In the mode, CPU clock stops but
oscillator keeps running. B.I.T and a part of peripheral
hardware execute, but prescalerís output which provide
clock to peripherals can be stopped by program. (Except,
PS10 canít stopped.) In SLEEP mode, more consuming
power can be saved by not using other peripheral hardware
except for B.I.T. By setting ENPCK (peripheral clock control bit) of CKCTLR (clock control register) to ``0``, peripheral hardware halted, and SLEEP mode is entered. To
-
-
-
-
-
NOP
: NOP instruction
0
-
-
-
SLPM0
condition
0
sleep mode release
1
sleep mode
SLPM0
Colck Control Register
7
CKCTLR
; mode register (SLPM)
SLEEP MODE CONTROL Register
7
SLPM
(ex) setting of SLEEP mode : set the bit of SLEEP
-
WDTON
ENPCK
BTCL
W <00F0 h>
0
BTS2
BTS1
ENCPK
Peripheral Clock
0
stopped
1
provided
BTS0
W <00C8 h>
15.2 STOP MODE
STOP mode can be entered by STOP instruction during
program. In STOP mode, oscillator is stopped to make all
clocks stop, which leads to less power consumption. All
registers and RAM data are preserved. ``NOP`` instruction
should be follows STOP instruction for rising precharge
62
time of Data Bus line.
(ex)
STOP
: STOP instruction execution
NOP
: NOP instruction
Sep. 2001 Ver 1.0
HMS87C5216
OSC.
Clock Pulse GEN
Circuit
CLR
CPU Clock
MUX
Basic Interval Timer
B.I.T 7
CLR
Prescaler
CLR
STOP
S
Q
R
S
Q
R
Control
Signal
Overflow Detection
Release Signal From Interrupt Circuit
RESET
Figure 15-1 Block Diagram of Standby Circuit
Prescaler
ENPCK
PS10
Selector
Basic Interval Timer
Peripheral
Figure 15-2 ENPCK and Basic Interval Timer Clock
Sep. 2001 Ver 1.0
63
HMS87C5216
15.3 STANDBY MODE RELEASE
Release of STANDBY mode is executed by RESET input
and Interrupt signal. Register value is defined when Reset.
When there is a release signal of STOP mode (Interrupt,
RESET input), the instruction execution starts after stabilization oscillation time is set by value of BTS2 ~ BTS0
and set ENPCK to ``1``.
Release Signal
SLEEP
STOP
RESET
O
O
KSCN (key input)
O
O
INT1 , INT2
O
O
B.I.T
O
X
Table 15-1 Standby Mode Register
Release Factor
RESET
KSCN
(key input)
INT1
INT2
Basic Interval Timer
(IFBIT)
Release Method
By RESET Pin = Low level, Standby mode is release and system is initialized
Standby mode is released by low input of selected pin by key scan Input
(SMRR0, SMRR1) In case of interrupt mask enable flag = ``0``,
program executes just after standby instruction,
if flag = ``1``, enters each interrupt service routine.
When external interrupt (INT1, INT2) enable flag is ``1``, standby mode is released
at the rising edge of each terminal. When Standby mode is released at interrupt.
Mask Enable flag = ``0``, program executes from the next instruction of standby
instruction. When ``1``, enters each interrupt service routine.
When B.I.T is executed only by bit10 of prescaler (PS10), SLEEP mode can be
release. Interrupt release SLEEP mode, when BIT interrupt enable flag is ``1``.
When standby mode is released at interrupt. Mask enable flag = ``0``,
program executes from the next instruction of SLEEP instruction.
When ``1``, enters each interrupt service routine.
Table 15-2 Standby Mode Release
64
Sep. 2001 Ver 1.0
HMS87C5216
[ SLEEP MODE ]
SLEEP command
Xin
SLEEP Mode
release by interrupt
RESET
Longer than
2 machine cycle
[ STOP MODE ]
clock
Stable
OSC. time
STOP Mode
release by interrupt
Program Setting Time by
CKCTLR
RESET
Longer than
stable OSC. Time
Figure 15-3 Release Timing of Standby Mode
15.4 RELEASE OPERATION OF STANDBY MODE
After standby mode is released, the operation begins according to content of related interrupt register just before
standby mode start (Figure 15-4 )
(1) Interrupt Enable Flag(I) of PSW = ``0``
Release by only interrupt which interrupt enable flag =
``1``, and starts to execute from next to standby instruction
(SLEEP or STOP).
(2) Interrupt Enable Flag(I) of PSW = ``1``
= ``1``, and jump to the relevant interrupt service routine.
Note: When STOP instruction is used, B.I.T should guarantee the stabilization oscillation time. Thus, just before entering STOP mode, clock of bit10 (PS10) of prescaler is
selected or peripheral hardware clock control bit (ENPCK)
to ``1``, Therefore the clock necessary for stabilization oscillation time should be input into B.I.T. otherwise, standby
mode is released by reset signal. In case of interrupt request flag and interrupt enable flag are both ``1``, standby
mode is not entered.
Released by only interrupt which each interrupt enable flag
Sep. 2001 Ver 1.0
65
HMS87C5216
STOP Command
Standby Mode
Interrupt Request GEN.
0
IE Flag
1
Standby Mode Release
0
PSW
IE Flag
1
Standby Next Command
Execution
Interrupt Service Routine
Figure 15-4 Standby Mode Release Flow
Internal circuit
SLEEP mode
STOP mode
Oscillator
Active
Stop
Internal CPU clock
Stop
Stop
Register
Retained
Retained
RAM
Retained
Retained
I/O port
Retained
Retained
Prescaler
Active
Retained
Basic Interval Timer
PS10 selected : Active
Others : Stop
Stop
Watch Dog Timer
Stop
Stop
Timer
Stop
Stop
Address Bus, Data Bus
Retained
Retained
Table 15-3 Operation State in Standby Mode
66
Sep. 2001 Ver 1.0
HMS87C5216
16. OSCILLATION CIRCUIT
pulse generator, and then enters prescaler to make peripheral hardware clock. Alternately, the oscillator may be
driven from an external source as shown is Fig. 4.2.-(b). In
the Standby (STOP) mode, oscillatiion stop, Xout state
goes to ``HIigh``, Xin state goes to ``Low``, and built-in
feed back resistor is disabled.
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Fig. 4.2-(a) shows
circuit diagrams using a crystal (or ceramic) oscillator. As
shown in the diagram, oscillation circuits can be constructed by connecting a oscillator between Xout and Xin.
Clock from oscillation circuit makes CPU clock via clock
(a) External Crystal (Ceramic) oscillator circuit
Cout
Xout
Xin
Cin
(b) External clock input circuit
Xout
Xin
External clock
Figure 16-1 Oscillator configurations
* Recommendable resonator
Frequency
4.0 MHz
Resonator Maker
Part Name
Load Capacitor
Operating Voltage
CQ
ZTA4.00MG
Cin=Cout=30pF
2.2 ~ 4.0V
TDK
FCR4.0MC5
Cin=Cout=open
2.2 ~ 4.0V
TDK
FCR4.0M5
Cin=Cout=33pF
2.2 ~ 4.0V
TDK
CCR4.0MC3
2.2 ~ 4.0V
* MC type is building in load capacitior.CCR type is chip type.
Sep. 2001 Ver 1.0
67
HMS87C5216
17. RESET FUNCTION
17.1 EXTERNAL RESET
The RESET pin should be held at low for at least 2machine
cycles with the power supply voltage within the operating
voltage range and must be connected 0.1uF capacitor for
stable system initialization. The RESET pin contains a
Schmitt trigger with an internal pull-up resistor.
RESET
0.1 uF Capacitor
Figure 17-1
17.2 POWER ON RESET
detection circuit.
Power On Reset circuit automatically detects the rise of
power voltage (the rising time should be within 50ms) the
power voltage reaches a certain level, RESET terminal is
maintained at °»L°» Level until a crystal ceramic oscillator
oscillates stably. After power applies and starting of oscillation, this reset state is maintained for about oscillation
cycle of 219 (about 65.5ms : at 4MHz).The execution of
built-in Power On Reset circuit is as follows :
(2) Once B.I.T Overflow detection circuit is reset. Then,
Prescaler starts to count.
(3) Prescaler output is inputted into B.I.T and PS10 of
Prescaler output is automatically selected. If overflow of
B.I.T is detected, Overflow detection circuit is set.
(4) Reset circuit generates maximum period of reset pulse
from Prescaler and B.I.T.
(1) Latch the pulse from Power On Detection Pulse Generator circuit, and reset Prescaler, B.I.T and B.I.T Overflow
Internal IC
VDD
Internal Reset
RESET
0.1uF
Power On DET
Pulse GEN.
VSS
XTAL
OSC.
CLR
Prescaler
PS10
CLR
MSB
CLR
Basic Interval
Basic Interval
Tiemr
Tiemr
Figure 17-2 Block Diagram of Power On Reset Circuit
68
Sep. 2001 Ver 1.0
HMS87C5216
Note: Notice ; When Power On Reset, oscillator stabilization time doesn`t include OSC. Start time.
wylzjhsly jv|u{ z{hy{
}kk
vzjU z{hy{ {ptpun
Figure 17-3 Oscillator stabilization diagram
RESET
INTERNAL
RESET
ADDR. BUS
SP
INTERNAL
DATA BUS
SP-1
SP-2
FFFE FFFF
FE
NEW PC
LSB
MSB
VECTOR VECTOR
Figure 17-4 Reset Timing by Diagram
17.3 Low Voltage Detection Mode
(1) Low voltage detection condition
(2) Low Voltage Detection Mode
An on board voltage comparator checks that VDD is at the
required level to ensure correct operation of the device. If
VDD is below a certain level, Low voltage detector forces
the device into low voltage detection mode.
There is no power consumption except stop current, stop
mode release function is disabled. All I/O port is configured as input mode and Data memory is retained until voltage through external capacitor is worn out. In this mode,
all port can be selected with Pull-up resistor by Mask option. If there is no information on the Mask option sheet
,the default pull up option (all port connect to pull-up resis-
Sep. 2001 Ver 1.0
69
HMS87C5216
tor ) is selected.
the low voltage detection mode and come into normal reset
state. It depends on user whether to execute RAM clear
routine or not.
(3) Release of Low Voltage Detection Mode
Reset signal result from new battery(normally 3V) wakes
s–ž }–“›ˆŽŒ O}P
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
×
10
×
20
×
30
×
40
×
{Œ”—Œ™ˆ›œ™ŒO
×
50
×
60
×
70
×
P
Figure 17-5 Low Voltage vs Temperature
(4) SRAM BACK-UP after Low Voltage Detection.
70
Sep. 2001 Ver 1.0
HMS87C5216
3.0V
about hours depend on Vcc-Gnd Capacitor
MCU OPR.
Voltage
Low Voltage Detection
point
Power On Reset
( SRAM retention)
×
1.8V(TYP)
( 20 P
Power On Reset
( SRAM unstable )
0.7V(VRET)
0V
* SRAM Data Backup
* The operation after Low voltage detection
Interrupt
: disable
User
Stop release : disable
Removes
All I/O port : input Mode
Batteries
Remout port : Low Level
OSC
: STOP
All I/O port pull-up ON (Mask Option )
SRAM Data retention
User
Replace
Batteries
Figure 17-6 Low Voltage Detection and Protection
(5) S/W flow chart example after Reset using SRAM Back-up
RESET
Stack Pointer initialize
Check the SRAM value
(RAM Pattern, Check sum..)
SRAM DATA IS VALID?
N
Clear All Ram area
Y
Use saved SRAM
value
Figure 17-7 S/W Flow Chart Example for SRAM Back-up
Sep. 2001 Ver 1.0
71
HMS87C5216
17.4 Low Voltage Indicator Register (LVIR)
Low Voltage Indication Register (LVIR) is read only Register. It is useful to display the consumption of Batteries.
If VDD power level is below a cirtain level which is higher
than low voltage detection level ( refer to Figure 17-6 ) ,
72
The bit of LVIR register could be set according to the VDD
level sequentially. The VDD dection levels for Indication
are two , that is , Bit1 and Bit0 of LVIR Register. The detection level of Bit0 is higer than Bit1.
bit
7
6
5
4
3
2
1
0
LVIR
-
-
-
-
-
-
LVIR1
LVIR0
initial value
-
-
-
-
-
-
0
0
R/W
-
-
-
-
-
-
R
R
<00EF h>
Sep. 2001 Ver 1.0
HMS87C5216
18. CLOCK GENERATOR
Clock generating circuit consists of Clock Pulse Generator
(C.P.G), Prescaler, Basic Interval Timer (B.I.T) and Watch
fex
Dog Timer. The clock applied to the Xin pin divided by
two is used as the internal system clock.
fcpu
OSC
Circuit
Internal System Clock
C.P.G
PRESCALER
IFBIT
PS1
ENPCK
0
7
0
5
8
WDTCL
B.I.T (8)
MUX
WDT (6)
9
BTCL
IFWDT
COMPARATOR
3
WDTON
Peripheral
CKCTLR
6
0
1
2
3
4
WDTR
5
To Reset
Circuit
6
0
5
6
Internal Data Bus
Figure 18-1 Block Diagram of Clock Generator
Prescaler consists of 12-bit binary counter. The clock supplied from oscillation circuit is input to prescaler (fex).
PS1
fex
PS2
PS3
PS4
PS5
The divided output from each bit of prescaler is provided
to peripheral hardware.
PS6
PS7
PS8
PS9
PS10
PS11
PS12
ENPCK
B.I.T
fcpu
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10 PS11
PS12
Peripheral
Figure 18-2 Block diagram of Prescaler
Sep. 2001 Ver 1.0
73
HMS87C5216
4 MHz
fex (MHz)
frequency
ps 0
ps 1
ps 2
ps 3
ps 4
ps 5
ps 6
ps 7
ps 8
ps 9
ps 10
ps 11
ps 12
4 MHz
2 MHz
1 MHz
500 KHz
250 KHz
125 KHz
62.5 KHz
31.25 KHz
15.63 KHz
7.183 KHz
3.906 KHz
1.953 KHz
0.976 KHz
2 MHz
period
frequency
period
500 ns
1 us
2 us
4 us
8 us
16 us
32 us
64 us
128 us
256 us
512 us
1024 us
2048 us
2 MHz
1 MHz
500 KHz
250 KHz
125 KHz
62.5 KHz
31.25 KHz
15.63 KHz
7.183 KHz
3.906 KHz
1.953 KHz
0.976 KHz
0.488 KHz
250 ns
500 ns
1 us
2 us
4 us
8 us
16 us
32 us
64 us
128 us
256 us
512 us
1024 us
Table 18-1 ps output perio Basic Interval Timer
The HMS87C5216 and GMS81C1408 has one 8-bit Basic
Interval Timer that is free-run, can not stop. Block diagram
is shown in Figure 18-3 .The 8-bit Basic interval timer register (BITR) is increased every internal count pulse which
is divided by prescaler. Since prescaler has divided ratio by
8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator
frequency. As the count overflows from FFH to 00H, this
overflow causes to generate the Basic interval timer interrupt. The BITF is interrupt request flag of Basic interval
timer.
When write “1” to bit BTCL of CKCTLR, BITR register is
cleared to “0” and restart to count-up. The bit BTCL becomes “0” after one machine cycle by hardware.
If the STOP instruction executed after writing “1” to bit
WAKEUP of CKCTLR, it goes into the wake-up timer
mode. In this mode, all of the block is halted except the os-
cillator, prescaler (only fxin÷2048) and Timer0.
If the STOP instruction executed after writing “1” to bit
RCWDT of CKCTLR, it goes into the internal RC oscillated watchdog timer mode. In this mode, all of the block is
halted except the internal RC oscillator, Basic Interval
Timer and Watchdog Timer. More detail informations are
explained in Power Saving Function. The bit WDTON decides Watchdog Timer or the normal 7-bit timer
Note: All control bits of Basic interval timer are in CKCTLR
register which is located at same address of BITR
(address ECH). Address ECH is read as BITR, written to CKCTLR. Therefore, the CKCTLR can not be
accessed by bit manipulation instruction.
.
RCWDT
BTS[2:0]
fxin
÷8
÷ 16
÷ 32
÷ 64
÷ 128
÷ 256
÷ 512
÷ 1024
BTCL
3
To Watchdog Timer
Clear
8
MUX
0
BITR (8BIT)
BITIF
Basic Interval Timer
Interrupt
1
Internal RC OSC
Figure 18-3 Block Diagram of Basic Interval Timer
74
Sep. 2001 Ver 1.0
HMS87C5216
Clock Control Register
CKCTLR
-
WAKEUP RCWDT
WDTON
BTCL
BTS2
BTS1
BTS0
ADDRESS : ECH
RESET VALUE : -0010111
Bit Manipulation Not Available
Basic Interval Timer Clock Selection
Symbol
WAKEUP
Function Description
1 : Enables Wake-up Timer
0 : Disables Wake-up Timer
RCWDT
1 : Enables Internal RC Watchdog Timer
0 : Disables Internal RC Watchdog Time
WDTON
1 : Enables Watchdog Timer
0 : Operates as a 7-bit Timer
BTCL
1 : BITR is cleared and BTCL becomes “0” automatically
after one machine cycle, and BITR continue to count-up
000 : fxin ÷ 8
001 : fxin ÷ 16
010 : fxin ÷ 32
011 : fxin ÷ 64
100 : fxin ÷ 128
101 : fxin ÷ 256
110 : fxin ÷ 512
111 : fxin ÷ 1024
Figure 18-4 CKCTLR: Clock Control Register
Sep. 2001 Ver 1.0
75
HMS87C5216
19. ANALOG TO DIGITAL CONVERTER
The analog-to-digital converter (A/D) allows conversion
of an analog input signal to a corresponding 8-bit digital
value. The A/D module has eight analog inputs, which are
multiplexed into one sample and hold. The output of the
sample and hold is the input into the converter, which generates the result via successive approximation.
The analog reference voltage is VDD. The A/D module has
two registers which are the control register ADMR and A/
D result register ADDR. The ADMR register, shown in
Figure 19-2 , controls the operation of the A/D converter
module. The port pins can be configure as analog inputs or
digital I/O.
To use analog inputs, each port is assigned analog input
port by setting the bit ANSEL[7:0] in RAFUNC register.
And selected the corresponding channel to be converted by
setting ADS[2:0].
The processing of conversion is start when the start bit
ADST is set to “1”. After one cycle, it is cleared by hardware. The register ADCR contains the results of the A/D
conversion. When the conversion is completed, the result
is loaded into the ADCR, the A/D conversion status bit
ADSF is set to “1”, and the A/D interrupt flag ADIF is set.
The block diagram of the A/D module is shown in Figure
19-1 . The A/D status bit ADSF is set automatically when
A/D conversion is completed, cleared when A/D conversion is in process. The conversion time takes maximum 30
uS (at fxin=4 MHz).
A/D Result Register
ADAN[1:0]
ADDR(8-bit)
ADDRESS : EDH
RESET VALUE : Undefined
11
R1[7]/AN3
Sample & Hold
ADEN
10
S/H
Successive
Approximation
Circuit
R1[6]/AN2
A D IF
A/D Interrupt
ADEN
01
R1[5]/AN1
ADEN
00
R1[4]/AN0
Resistor
Ladder
Circuit
ADEN
AVDD
ADEN
Figure 19-1 A/D Converter Block Diagram
76
Sep. 2001 Ver 1.0
HMS87C5216
A/D Control Register
ADMR
-
ANEN
ADAN3
ADAN2
ADAN1
ADAN0
ADST
ADF
ADDRESS : F4H
RESET VALUE : --000001
A/D Status bit
0 : A/D Conversion is in process
1 : A/D Conversion is completed
Analog Channel Select
0000 : Channel 0 (R1[4]/AN0)
0001 : Channel 1 (R1[5]/AN1)
0010 : Channel 2 (R1[6]/AN2)
0011 : Channel 3 (R1[7]/AN3)
A/D Start bit
1 : A/D Conversion is started
After 1 cycle, cleared to “0”
0 : Bit force to zero
A/D Enable bit
1 : A/D Conversion is enable
0 : A/D Converter module shut off
and consumes no operation current
A/D Result Data Register
ADCR
ADCR7
ADCR6
ADCR5
ADCR4
ADCR3
ADCR2
ADCR1
ADCR0
ADDRESS : F5H
RESET VALUE : Undefined
Figure 19-2 A/D Converter Registers
A/D Converter Cautions
ENABLE A/D CONVERTER
(1) Input range of AN0 to AN3
The input voltage of AN0 to AN3 should be within the
specification range. In particular, if a voltage above VDD
or below Vss is input (even if within the absolute maximum rating range), the conversion value for that channel can not be indeterminate. The conversion values of the other channels may also
be affected.
A/D INPUT CHANNEL SELECT
ANALOG REFERENCE SELECT
(2) Noise countermeasures
In order to maintain 8-bit resolution, attention must be paid to
noise on pins VDD and AN0 to AN3. Since the effect increases
in proportion to the output impedance of the analog input source,
it is recommended that a capacitor be connected externally as
shown in Figure 19-4 in order to reduce noise.
A/D START (ADST = 1)
NOP
Analog
Input
ADSF = 1
NO
AN0~AN3
100~1000pF
YES
READ ADCR
Figure 19-4 Analog Input Pin Connecting Capacitor
Figure 19-3 A/D Converter Operation Flow
Sep. 2001 Ver 1.0
(3) Pins AN0/R1[4] and AN1/R1[5] to AN3/R1[7]
77
HMS87C5216
The analog input pins AN0 to AN3 also function as input/
output port (PORT R1 ) pins. When A/D conversion is performed with any of pins AN0 to AN3 selected, be sure not
to execute a PORT input instruction while conversion is in
progress, as this may reduce the conversion resolution.
78
Also, if digital pulses are applied to a pin adjacent to the
pin in the process of A/D conversion, the expected A/D
conversion value may not be obtainable due to coupling
noise. Therefore, avoid applying pulses to pins adjacent to
the pin undergoing A/D conversion.
Sep. 2001 Ver 1.0