TPS3700 www.ti.com SBVS187B – FEBRUARY 2012 – REVISED APRIL 2012 Window Comparator for Over- and Undervoltage Detection Check for Samples: TPS3700 FEATURES 1 • • • • • Wide Supply Voltage Range: 1.8 V to 18 V Adjustable Threshold: Down to 400 mV Open-Drain Outputs for Over- and Undervoltage Detection Low Quiescent Current: 5.5 µA (typ) High Threshold Accuracy: – 1.0% Over Temperature – 0.25% (typ) Internal Hysteresis: 5.5 mV (typ) Temperature Range: –40°C to +125°C Available in a ThinSOT23-6 Package APPLICATIONS • • • • • • • Industrial Control Systems Automotive Systems Embedded Computing Modules DSP, Microcontroller, or Microprocessor Applications Notebook and Desktop Computers Portable- and Battery-Powered Products FPGA and ASIC Applications VMON DESCRIPTION The TPS3700 wide-supply voltage window comparator operates over a 1.8-V to 18-V range. The device has two high-accuracy comparators with an internal 400-mV reference and two open-drain outputs rated to 18 V for over- and undervoltage detection. The TPS3700 can be used as a window comparator or as two independent voltage monitors; the monitored voltage can be set with the use of external resistors. OUTA is driven low when the voltage at INA+ drops below (VITP – VHYS), and goes high when the voltage returns above the respective threshold (VITP). OUTB is driven low when the voltage at INB– rises above VITP, and goes high when the voltage drops below the respective threshold (VITP – VHYS). Both comparators in the TPS3700 include built-in hysteresis for filtering to reject brief glitches, thereby ensuring stable output operation without false triggering. The TPS3700 is available in a ThinSOT23-6 package and is specified over the junction temperature range of –40°C to +125°C. OUTA • • • 2 1.8 V to 18 V INA+ VITP 0.1 mF VDD RP1 OUTA INA+ RP2 R2 Device To a reset or enable input of the system. OUTB R1 INB OUTB INB- R3 DDC PACKAGE ThinSOT23-6 (TOP VIEW) GND Figure 1. TPS3700 Typical Application VITP OUTA 1 6 OUTB GND 2 5 VDD INA+ 3 4 INB- 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS3700 SBVS187B – FEBRUARY 2012 – REVISED APRIL 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT DESCRIPTION yyy is package designator z is package quantity TPS3700yyyz (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. VALUE Voltage (2) Current Electrostatic discharge (ESD) rating (3) (2) (3) MAX UNIT –0.3 +20 V VOUTA, VOUTB –0.3 +20 V VINA+, VINB– –0.3 +7 V 40 mA °C Output pin current Temperature (1) MIN VDD Operating junction, TJ –40 +125 Storage, Tstg –65 +150 °C 2 kV 500 V Human body model (HBM) Charge device model (CDM) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. All voltages are with respect to network ground terminal. ESD testing is performed according to the respective JESD22 JEDEC standard. THERMAL INFORMATION TPS3700 THERMAL METRIC (1) DDC (SOT23) UNITS 6 PINS θJA Junction-to-ambient thermal resistance 204.6 θJCtop Junction-to-case (top) thermal resistance 50.5 θJB Junction-to-board thermal resistance 54.3 ψJT Junction-to-top characterization parameter 0.8 ψJB Junction-to-board characterization parameter 52.8 θJCbot Junction-to-case (bottom) thermal resistance N/A (1) 2 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS3700 TPS3700 www.ti.com SBVS187B – FEBRUARY 2012 – REVISED APRIL 2012 ELECTRICAL CHARACTERISTICS Over the operating temperature range of TJ = –40°C to +125°C, and 1.8 V < VDD < 18 V, unless otherwise noted. Typical values are at TJ = +25°C and VDD = 5 V. PARAMETER VDD TEST CONDITIONS Supply voltage range V(POR) VITP Power-on reset voltage (1) VITN Negative-going input threshold voltage VHYS Hysteresis voltage (HYS = VITP – VITN) Input current (at IN pin) VOL Low-level output voltage Ilkg(OD) TYP 1.8 Positive-going input threshold voltage IIN MIN Open-drain output leakage current MAX 18 VOL (max) = 0.2 V, I(OUT) = 15 µA UNIT V 0.8 V 400 404 mV 396 400 404 mV 387 394.5 400 mV 387 394.5 400 mV 5.5 12 mV 25 nA VDD = 1.8 V 396 VDD = 18 V VDD = 1.8 V VDD = 18 V VDD = 1.8 V and 18 V, VIN = 6.5 V –25 1 VDD = 1.8 V and 18 V, VIN = 0.1 V –15 1 15 nA VDD = 1.3 V, IOUT = 0.4 mA 250 mV VDD = 1.8 V, IOUT = 3 mA 250 mV VDD = 5 V, IOUT = 5 mA 250 mV VDD = 1.8 V and 18 V, VOUT = VDD 300 nA VDD = 1.8 V, VOUT = 18 V 300 nA tpd(HL) High-to-low propagation delay (2) VDD = 5 V, 10-mV input overdrive, RL = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV tpd(LH) Low-to-high propagation delay (2) VDD = 5 V, 10-mV input overdrive, RL = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV 29 µs tR Output rise time VDD = 5 V, 10-mV input overdrive, RL = 10 kΩ, VO = (0.1 to 0.9) × VDD 2.2 µs tF Output fall time VDD = 5 V, 10-mV input overdrive, RL = 10 kΩ, VO = (0.1 to 0.9) × VDD 0.22 µs VDD = 1.8 V, no load IDD Supply current 5.5 11 µA 6 13 µA VDD = 12 V 6 13 µA 7 13 µA VDD = 18 V (1) (2) (3) (4) Undervoltage lockout (4) µs VDD = 5 V Startup delay (3) UVLO 18 150 VDD falling 1.3 µs 1.7 V The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. Below V(POR), the output cannot be determined. High-to-low and low-to-high refers to the transition at the input pins (INA+ and INB–). During power on, VDD must exceed 1.8 V for at least 150 µs before the output is in a correct state. When VDD falls below UVLO, OUTA is driven low and OUTB goes to high impedance. The outputs cannot be determined below V(POR). Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS3700 3 TPS3700 SBVS187B – FEBRUARY 2012 – REVISED APRIL 2012 www.ti.com PARAMETRIC MEASUREMENT INFORMATION TIMING DIAGRAM VDD VITP VHYS INA+ OUTA tpd(HL) tpd(LH) tpd(LH) VITP VHYS INB- OUTB tpd(LH) tpd(HL) Figure 2. TPS3700 Timing Diagram 4 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS3700 TPS3700 www.ti.com SBVS187B – FEBRUARY 2012 – REVISED APRIL 2012 PIN CONFIGURATIONS DDC PACKAGE ThisSOT23-6 (TOP VIEW) OUTA 1 6 OUTB GND 2 5 VDD INA+ 3 4 INB- PIN ASSIGNMENTS PIN NAME PIN NO. GND 2 Ground DESCRIPTION INA+ 3 This pin is connected to the voltage to be monitored with the use of an external resistor divider. When the voltage at this terminal drops below the threshold voltage (VITP – VHYS), OUTA is driven low. INB– 4 This pin is connected to the voltage to be monitored with the use of an external resistor divider. When the voltage at this terminal exceeds the threshold voltage (VITP), OUTB is driven low. OUTA 1 INA+ comparator open-drain output. OUTA is driven low when the voltage at this comparator is below (VITP – VHYS). The output goes high when the sense voltage returns above the respective threshold (VITP). OUTB 6 INB– comparator open-drain output. OUTB is driven low when the voltage at this comparator exceeds VITP. The output goes high when the sense voltage returns below the respective threshold (VITP – VHYS). VDD 5 Supply voltage input. Connect a 1.8-V to 18-V supply to VDD to power the device. It is good analog design practice to place a 0.1-µF ceramic capacitor close to this pin. BLOCK DIAGRAM VDD INA+ OUTA OUTB INB- Reference GND Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS3700 5 TPS3700 SBVS187B – FEBRUARY 2012 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS At TJ = +25°C and VCC = 5 V, unless otherwise noted. SUPPLY CURRENT vs SUPPLY VOLTAGE RISING INPUT THRESHOLD VOLTAGE vs TEMPERATURE 401 10 VDD = 1.8 V VDD = 5 V VDD = 12 V VDD = 18 V 9 400.6 8 6 VITP (mV) IDD (µA) 7 5 4 −40°C 0°C +25°C +85°C +125°C 3 2 1 0 0 2 4 6 8 10 VDD (V) 12 14 16 400.2 399.8 399.4 399 −40 −25 −10 18 G002 30 VDD = 1.8 V VDD = 5 V VDD = 12 V VDD = 18 V High−to−Low Propagation Delay (µs) VHYS (mV) 110 125 PROPAGATION DELAY vs TEMPERATURE (High-to-Low Transition at the Inputs) 6 4 3 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 VDD = 1.8 V, INB− to OUTB VDD = 18 V, INB− to OUTB VDD = 1.8 V, INA+ to OUTA VDD = 18 V, INA+ to OUTA 28 26 24 22 20 18 16 14 12 10 8 −40 −25 −10 110 125 5 G003 20 35 50 65 Temperature (°C) 80 95 110 125 G004 Figure 5. Figure 6. PROPAGATION DELAY vs TEMPERATURE (Low-to-High Transition at the Inputs) MINIMUM PULSE WIDTH vs THRESHOLD OVERDRIVE VOLTAGE (1) 30 20 28 18 26 16 Input Pulse Duration (µs) Low−to−High Propagation Delay (µs) 95 HYSTERESIS vs TEMPERATURE 5 24 22 20 18 16 14 VDD = 1.8 V, INB− to OUTB VDD = 18 V, INB− to OUTB VDD = 1.8 V, INA+ to OUTA VDD = 18 V, INA+ to OUTA 12 10 8 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 INA+ INB− 14 12 10 8 6 4 2 110 125 0 2.5 G005 Figure 7. 6 80 Figure 4. 7 (1) 20 35 50 65 Temperature (°C) Figure 3. 9 8 5 G001 4 5.5 7 8.5 10 11.5 VITP Overdrive (%) 13 14.5 16 G006 Figure 8. INA+ = negative spike below VITN and INB– = positive spike above VITP. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS3700 TPS3700 www.ti.com SBVS187B – FEBRUARY 2012 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS (continued) At TJ = +25°C and VCC = 5 V, unless otherwise noted. OUTPUT VOLTAGE LOW vs OUTPUT SINK CURRENT (–40°C) SUPPLY CURRENT vs OUTPUT SINK CURRENT 11 2000 10 1750 9 1500 7 VOL (mV) IDD (µA) 8 6 5 −40°C 0°C +25°C +85°C +125°C 4 3 2 1 0 5 10 15 20 25 30 Output Sink Current (mA) 35 1000 750 250 0 40 0 5 10 G007 15 20 25 30 Output Sink Current (mA) 35 40 G008 Figure 9. Figure 10. OUTPUT VOLTAGE LOW vs OUTPUT SINK CURRENT (0°C) OUTPUT VOLTAGE LOW vs OUTPUT SINK CURRENT (+25°C) 2000 VDD = 1.8 V VDD = 5 V VDD = 18 V 1750 1500 1500 1250 1000 750 1250 1000 750 500 500 250 250 0 0 5 10 VDD = 1.8 V VDD = 5 V VDD = 18 V 1750 VOL (mV) VOL (mV) 1250 500 2000 15 20 25 30 Output Sink Current (mA) 35 0 40 0 5 10 G009 15 20 25 30 Output Sink Current (mA) 35 40 G010 Figure 11. Figure 12. OUTPUT VOLTAGE LOW vs OUTPUT SINK CURRENT (+85°C) OUTPUT VOLTAGE LOW vs OUTPUT SINK CURRENT (+125°C) 2000 2000 VDD = 1.8 V VDD = 5 V VDD = 18 V 1750 1500 1500 1250 1000 750 1250 1000 750 500 500 250 250 0 0 5 10 VDD = 1.8 V VDD = 5 V VDD = 18 V 1750 VOL (mV) VOL (mV) VDD = 1.8 V VDD = 5 V VDD = 18 V 15 20 25 30 Output Sink Current (mA) 35 40 0 0 G011 Figure 13. 5 10 15 20 25 30 Output Sink Current (mA) 35 40 G012 Figure 14. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS3700 7 TPS3700 SBVS187B – FEBRUARY 2012 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C and VCC = 5 V, unless otherwise noted. STARTUP DELAY (VDD = 5 V, INA+ = 390 mV, INB– = 410 mV, Outputs Pulled Up to VDD) STARTUP DELAY (VDD = 5 V, INA+ = 410 mV, INB– = 390 mV, Outputs Pulled Up to VDD) OUTB C2 (2.0 V/div) C1 (2.0 V/div) C3 (2.0 V/div) C2 (2.0 V/div) OUTB OUTA C1 (2.0 V/div) C3 (2.0 V/div) VDD Time (100 ms/div) G013 Figure 15. 8 OUTA VDD Time (100 ms/div) G014 Figure 16. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS3700 TPS3700 www.ti.com SBVS187B – FEBRUARY 2012 – REVISED APRIL 2012 GENERAL DESCRIPTION The TPS3700 combines two comparators for over- and undervoltage detection. The TPS3700 is a wide-supply voltage range (1.8 V to 18 V) device with a high-accuracy rising input threshold of 400 mV (1% over temperature) and built-in hysteresis. The outputs are also rated to 18 V and can sink up to 40 mA. The TPS3700 is designed to assert the output signals, as shown in Table 1. Each input pin can be set to monitor any voltage above 0.4 V using an external resistor divider network. With the use of two input pins of different polarities, the TPS3700 forms a window comparator. Broad voltage thresholds can be supported that allow the device to be used in a wide array of applications. Table 1. TPS3700 Truth Table CONDITION OUTPUT STATUS INA+ > VITP OUTA high Output A not asserted INA+ < VITN OUTA low Output A asserted INB– > VITP OUTB low Output B asserted INB– < VITN OUTB high Output B not asserted INPUTS (INA+, INB–) The TPS3700 combines two comparators. Each comparator has one external input (inverting and noninverting); the other input is connected to the internal reference. The comparator rising threshold is designed and trimmed to be equal to the reference voltage (400 mV). Both comparators also have a built-in falling hysteresis that makes the device immune to supply rail noise and ensures stable operation. The comparator inputs can swing from ground to 6.5 V, regardless of the device supply voltage used. Although not required in most cases, it is good analog design practice to place a 1-nF to 10-nF bypass capacitor at the comparator input for extremely noisy applications in order to reduce sensitivity to transients and layout parasitics. For comparator A, the corresponding output (OUTA) is driven to logic low when the input INA+ voltage drops below (VITP – VHYS). When the voltage exceeds VITP, the output (OUTA) goes to a high-impedance state; see Figure 2. For comparator B, the corresponding output (OUTB) is driven to logic low when the voltage at input INB– exceeds VITP. When the voltage drops below VITP – VHYS the output (OUTB) goes to a high-impedance state; see Figure 2. Together, these comparators form a window-detection function as discussed in the Window Comparator section. OUTPUTS (OUTA, OUTB) In a typical TPS3700 application, the outputs are connected to a reset or enable input of the processor [such as a digital signal processor (DSP), central processing unit (CPU), field-programmable gate array (FPGA), or application-specific integrated circuit (ASIC)] or the outputs are connected to the enable input of a voltage regulator [such as a dc-dc or low-dropout regulator (LDO)]. The TPS3700 provides two open-drain outputs (OUTA and OUTB); pull-up resistors must be used to hold these lines high when the output goes to high impedance (not asserted). By connecting pull-up resistors to the proper voltage rails, the outputs can be connected to other devices at correct interface voltage levels. The TPS3700 outputs can be pulled up to 18 V, independent of the device supply voltage. To ensure proper voltage levels, some thought should be given while choosing the pull-up resistor values. The pull-up resistor value is determined by VOL, sink current capability, and output leakage current (Ilkg(OD)). These values are specified in the Electrical Characteristics table. By using wired-AND logic, OUTA and OUTB can be merged into one logic signal. Table 1 and the Inputs section describe how the outputs are asserted or de-asserted. Refer to Figure 2 for a timing diagram that describes the relationship between threshold voltages and the respective output. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS3700 9 TPS3700 SBVS187B – FEBRUARY 2012 – REVISED APRIL 2012 www.ti.com WINDOW COMPARATOR The inverting and noninverting configuration of the comparators forms a window-comparator detection circuit using a resistor divider network, as shown in Figure 17 and Figure 18. The input pins can monitor any system voltage above 400 mV with the use of a resistor divider network. INA+ and INB– monitor for undervoltage and overvoltage conditions, respectively. VMON (13.2 V to 10.8 V) 1.8 V to 18 V VDD RP1 (50 kW) IN OUTA INA+ Voltage Regulator VOUT R2 (13.7 kW) EN Device OUTB INBR3 (69.8 kW) OUT R1 (2.21 MW) UV VMON OV OUT GND Figure 17. Window Comparator Block Diagram Overvoltage Limit VMON Undervoltage Limit OUTB OUTA Figure 18. Window Comparator Timing Diagram 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS3700 TPS3700 www.ti.com SBVS187B – FEBRUARY 2012 – REVISED APRIL 2012 The resistor divider values and target threshold voltage can be calculated by using Equation 1 through Equation 4: RTOTAL = R1 + R2 + R3 (1) Choose RTOTAL such that current through the divider is approximately 100x higher than the input current at the INA+ and INB– pins. The resistors can have high values to minimize current consumption as a result of low input bias current without adding significant error to the resistive divider. Refer to application note Optimizing Resistor Dividers at a Comparator Input (SLVA450) for details on sizing input resistors. R3 is determined by Equation 2: RTOTAL R3 = ´ VITP VMON(OV) where: VMON(OV) is the target voltage at which an overvoltage condition is detected (2) R2 is determined by either Equation 3 or Equation 4: RTOTAL R2 = ´ VITP - R3 VMON (no UV) where: VMON(no R2 = UV) RTOTAL VMON(UV) is the target voltage at which an undervoltage condition is removed as VMON rises (3) ´ (VITP - VHYS) - R3 where: VMON(UV) is the target voltage at which an undervoltage condition is detected (4) For more application information on the TPS3700, refer to Figure 19 through Figure 22. IMMUNITY TO INPUT PIN VOLTAGE TRANSIENTS The TPS3700 is relatively immune to short voltage transient spikes on the input pins. Sensitivity to transients is dependent on both transient duration and amplitude; refer to the Typical Characteristics curve, Minimum Pulse Width vs Threshold Overdrive Voltage (Figure 8). Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS3700 11 TPS3700 SBVS187B – FEBRUARY 2012 – REVISED APRIL 2012 www.ti.com VPULL-UP (Up To 18 V) 1.8 V to 18 V VDD OUTA INA+ To a reset or enable input of the system. Device OUTB INB- GND Figure 19. Interfacing to Voltages Other Than VDD 1.8 V to 18 V VDD OUTA INA+ To a reset or enable input of the system. Device OUTB INB- GND Figure 20. Monitoring the Same Voltage as VDD 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS3700 TPS3700 www.ti.com SBVS187B – FEBRUARY 2012 – REVISED APRIL 2012 VMON (26.4 V to 21.7 V) 1.8 V to 18 V R1 (2.61 MW) VDD OUTA INA+ R2 (8.06 kW) Device R3 (40.2 kW) To a reset or enable input of the system. OUTB INB- GND NOTE: The inputs can monitor a voltage higher than VDD (max) with the use of an external resistor divider network. Figure 21. Monitoring a Voltage Other Than VDD 1.8 V to 18 V OUTA INA+ To a reset or enable input of the system. Device 12 V OUTB INB- INA+ VITP INB- VITP OUTB 5V OUTA VDD GND NOTE: In this case, OUTA is driven low when an undervoltage condition is detected at the 5-V rail and OUTB is driven low when an overvoltage condition is detected at the 12-V rail. Figure 22. Monitoring Overvoltage for One Rail and Undervoltage for a Different Rail Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS3700 13 TPS3700 SBVS187B – FEBRUARY 2012 – REVISED APRIL 2012 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (February 2012) to Revision B • 14 Page Moved to Production Data .................................................................................................................................................... 1 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS3700 PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS3700DDCR ACTIVE SOT DDC 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS3700DDCT ACTIVE SOT DDC 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Apr-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS3700DDCR SOT DDC 6 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS3700DDCT SOT DDC 6 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Apr-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS3700DDCR SOT DDC 6 3000 195.0 200.0 45.0 TPS3700DDCT SOT DDC 6 250 195.0 200.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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