ICS8343I Integrated Circuit Systems, Inc. LOW SKEW 1-TO-16 FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8343I is a low skew, 1-to-16 Fanout ,&6 Buffer and a member of the HiPerClockS™ family HiPerClockS™ of High Performance Clock Solutions from ICS. The ICS8343I is at 5.0V, 3.3V, 2.5V and mixed 3.3V input and 2.5V supply modes over the commercial temperature range. Guaranteed output and part-topart skew characteristics make the ICS8343I ideal for those clock distribution applications demanding well defined performance and repeatability. • 16 LVCMOS outputs • Output frequency up to 200MHz • 250ps output skew •· 700ps part to part • CMOS compatible clock input at 5V, LVTTL and LVCMOS compatible at 3.3V and 2.5V • LVTTL output enable inputs • Dual output enable inputs facilitates 1-to-16 or 1-to-8 input to output modes • 5.0V, 3.3V, 2.5V or mixed 3.3V, 2.5V from -40°C to 85°C ambient operating temperature • 32 lead low-profile QFP(LQFP), 7mm x 7mm x 1.4mm package body, 0.8mm package lead pitch BLOCK DIAGRAM Q13 Q14 Q15 OE2 OE1 Q0 VDD2 Q1 VDD Q2 VDD1 PIN ASSIGNMENT 32 31 30 29 28 27 26 25 CLK Q15 Q0 Q14 Q1 1 24 VDD2 VDD1 2 23 VDD2 VDD1 3 22 VDD2 Q3 4 21 Q12 Q4 5 20 Q11 ICS8343I Q2 Q13 Q3 Q12 GND 6 19 GND Q4 Q11 GND 7 18 GND Q5 Q10 GND 8 17 GND Q10 Q9 Q8 OE2 VDD GND CLK Q8 Q7 Q7 Q6 Q9 9 10 11 12 13 14 15 16 Q5 Q6 OE1 8343I VDD1 32-Lead LQFP Y package Top View www.icst.com/products/hiperclocks.html 1 REV. B MARCH 8, 2001 ICS8343I Integrated Circuit Systems, Inc. LOW SKEW 1-TO-16 FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2, 3 VDD1 Power Type Description Output Q0 thru Q7 power supply. Connect to 5V, 3.3V or 2.5V. 4, 5 Q3, Q4 Output Clock outputs. 14Ω typical output impedance. 6, 7, 8 GND Power Connect to ground. 9, 10, 11 Q5, Q6, Q7 Output Clock outputs. 14Ω typical output impedance. 12 CLK Input Clock input. 13 VDD Power Input power supply. Connect to 5V, 3.3V or 2.5V 14, 15, 16 Q8, Q9, Q10 Output Clock outputs. 14Ω typical output impedance. 17, 18, 19 GND Power Connect to ground. 20, 21 Q11, Q12 Output Clock outputs. 14Ω typical output impedance. 22, 23, 24 VDD2 Power Output Q8 thru Q15 power supply. Connect to 5V, 3.3V or 2.5V. 25, 26, 27 Q13, Q14, Q15 Output Clock outputs. 14Ω typical output impedance. 28 OE2 Input Pullup Output enable. When low forces outputs Q8 thru Q15 to HiZ state. 29 OE1 Input Pullup Output enable. When low forces outputs Q0 thru Q7 to HiZ state. 30, 31, 32 Q0, Q1, Q2 Output Clock outputs. 14Ω typical output impedance. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Typical Maximum CLK Units pF OE1, OE2 pF VDD1, VDD2 = 5.25V Power Dissipation Capacitance (per output) CPD Minimum 15 pF VDD1, VDD2 = 3.47V 11 pF VDD1, VDD2 = 2.63V 9.5 pF RPULLUP Input Pullup Resistor pF RPULLDOWN Input Pulldown Resistor pF ROUT TABLE 3. FUNCTION TABLE Inputs OE1 8343I Outputs OE2 Q0 thru Q7 Q8 thru Q15 0 0 Hi Z Hi Z 1 0 Active Hi Z 0 1 Hi Z Active 1 1 Active Active www.icst.com/products/hiperclocks.html 2 REV. B MARCH 8, 2001 ICS8343I Integrated Circuit Systems, Inc. LOW SKEW 1-TO-16 FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage Inputs Outputs Ambient Operating Temperature Storage Temperature 7V -0.5V to VDD+0.5 V -0.5V to VDD+0.5V -40°C to 85°C -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDD1 = VDD2 = 5V±5%, TA = -40° TO 85°C Symbol Parameter VDD, VDD1, VDD2 Operating Supply Voltage IDD Input Operating Supply Current Test Conditions Minimum 4.75 Typical 5.0 VDD = VDDx = 5.25V Maximum 5.25 110 Units V µA TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = VDD1 = VDD2 = 5V±5%, TA = -40° TO 85°C Symbol Parameter VIH Input High Voltage CLK OEx VIL IIH IIL VOH Input Low Voltage Input High Current Input Low Current CLK Test Conditions Minimum Maximum Units VDD = 4.75V 3.32 Typical 5.05 V VDD = 5.25V 3.67 5.55 V VDD = 5.25V 2 VDD + 0.3 V VDD = 4.75V -0.3 1.42 V VDD = 5.25V -0.3 1.57 V OEx VDD = 4.75V -0.3 0.8 V CLK VDD = VIN = 5.25V 1 µA OEx VDD = VIN = 5.25 1 µA CLK VDD = 5.25V, VIN = 0V -4 0 µA OEx VDD = 5.25V, VIN = 0V -40 µA Output High Voltage VDDx = 4.75V, IOH = -25mA 4 V VOL Output Low Voltage VDDx = 4.75V, IOL = 25mA 0.8 V IOZH High Impedance Leakage Current OEx = 0V, VOUT = VDDx 1 µA IOZL High Impedance Leakage Current OEx = 0V, VOUT = 0V 8343I www.icst.com/products/hiperclocks.html 3 -1 µA REV. B MARCH 8, 2001 ICS8343I Integrated Circuit Systems, Inc. LOW SKEW 1-TO-16 FANOUT BUFFER TABLE 5A. AC CHARACTERISTICS, VDD = VDD1 = VDD2 = 5V±5%, TA = -40° TO 85°C Symbol Parameter fMAX Maximum Input Frequency Test Conditions Minimum Typical Maximum Units 66 MHz tpLH Propagation Delay, Low-to-High 0 < f ≤ 66MHz 0.9 1.4 1.8 ns tpHL Propagation Delay, High-to-Low 0.9 1.4 1.9 ns tsk(o) Output Skew; NOTE 3 350 ps tsk(pp) Par t-to-Par t Skew; NOTE 4 700 ps tR Output Rise Time 0< f ≤ 66MHz Measured on rising edge @VDDx/2 Measured on rising edge @VDDx/2 Measured from 0.8V to 2.0V 0.3 0.5 ns tF Output Fall Time Measured from 2.0V to 0.8V 0.3 0.4 tCYCLE/2 + 0.75 ns tPW tCYCLE/2 - 0.75 Output Pulse Width tCYCLE/2 ns NOTE 1: All parameters measured at fMAX unless noted otherwise. NOTE 2: Outputs terminated with 50Ω resistor connected to VDDx/2. NOTE 3: Defined as skew across outputs at the same supply voltages and with equal load conditions. NOTE 4: Defined as skew at different outputs on different devices operating at the same supply voltages and with equal load conditions. 8343I www.icst.com/products/hiperclocks.html 4 REV. B MARCH 8, 2001 ICS8343I Integrated Circuit Systems, Inc. LOW SKEW 1-TO-16 FANOUT BUFFER TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDD1 = VDD2 = 3.3V±5%, TA = -40° TO 85°C Symbol Parameter VDD, VDD1, VDD2 Operating Supply Voltage IDD Input Operating Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 100 Units V µA Maximum Units TABLE 4D. LVCMOS DC CHARACTERISTICS, VDD = VDD1 = VDD2 = 3.3V±5%, TA = -40° TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current Test Conditions Minimum Typical CLK VDD = 3.465V 2 VDD + 0.3 V OEx VDD = 3.465V 2 VDD + 0.3 V CLK VDD = 3.135V -0.3 0.8 V -0.3 OEx VDD = 3.135V 0.8 V CLK VIN =VDD 1 µA OEx VIN =VDD 1 µA CLK VIN = 0V -15 µA IIL Input Low Current VIN = 0V -15 µA VOH Output High Voltage VDD = 3.135V, IOH = -25mA 2.4 V OEx VOL Output Low Voltage VDD = 3.135V, IOL = 25mA 0.8 V IOZH High Impedance Leakage Current OEx = 0V, VOUT = VDD 1 µA IOZL High Impedance Leakage Current OEx = 0V, VOUT = 0V -1 µA TABLE 5B. AC CHARACTERISTICS, VDD = VDD1 = VDD2 = 3.3V±5%, TA = -40° TO 85°C Symbol Parameter fMAX Maximum Input Frequency tpLH Propagation Delay, Low-to-High 0 ≤ f ≤ 200MHz 1.0 tpHL Propagation Delay, High-to-Low 1.1 tsk(o) Output Skew; NOTE 3 tsk(pp) Par t-to-Par t Skew; NOTE 4 tR Output Rise Time 0 ≤ f ≤ 200MHz Measured on rising edge @VDDx/2 Measured on rising edge @VDDx/2 0 ≤ f ≤ 200MHz tF Output Fall Time 0 ≤ f ≤ 200MHz tPW Test Conditions Minimum tCYCLE/2 - 0.5 Output Pulse Width Typical Maximum Units 200 MHz 2.1 3.1 ns 2.0 2.8 ns 250 ps 700 ps 0.5 0.8 ns 0.9 1.7 tCYCLE/2 + 0.5 ns tCYCLE/2 ns NOTE 1: All parameters measured at fMAX unless noted otherwise. NOTE 2: Outputs terminated with 50Ω resistor connected to VDDx/2. NOTE 3: Defined as skew across outputs at the same supply voltages and with equal load conditions. NOTE 4: Defined as skew at different outputs on different devices operating at the same supply voltages and with equal load conditions. 8343I www.icst.com/products/hiperclocks.html 5 REV. B MARCH 8, 2001 ICS8343I Integrated Circuit Systems, Inc. LOW SKEW 1-TO-16 FANOUT BUFFER TABLE 4E. DC POWER SUPPLY CHARACTERISTICS, VDD = 3.3V±5%, VDD1 = VDD2 = 2.5V±5%, TA = -40° TO 85°C Symbol VDD VDD1, VDD2 IDD Parameter Input Operating Supply Voltage Out Operating Supply Voltage Input Operating Supply Current Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 100 Units V V µA TABLE 4F. LVCMOS DC CHARACTERISTICS, VDD = 3.3V±5%, VDD1 = VDD2 = 2.5V±5%, TA = -40° TO 85°C Symbol Parameter VIH Input High Voltage CLK Test Conditions Minimum Maximum Units VDD = 3.465V 2 Typical VDD + 0.3 V OEx VDD = 3.465V 2 VDD + 0.3 V CLK VDD = 3.135V -0.3 0.8 V -0.3 0.8 V 1 µA VIL Input Low Voltage OEx VDD = 3.135V IIH Input High Current CLK VIN =VDD OEx VIN =VDD IIL Input Low Current CLK VIN = 0V -15 µA OEx VIN = 0V -15 µA 1.5 VOH Output High Voltage VDD = 2.375V, IOH = -25mA VOL Output Low Voltage VDD = 2.375V, IOL = 25mA IOZH High Impedance Leakage Current OEx = 0V, VOUT = VDD IOZL High Impedance Leakage Current OEx = 0V, VOUT = 0V 1 µA V 0.8 V 1 µA -1 µA TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V±5%, VDD1 = VDD2 = 2.5V±5%, TA = -40° TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Maximum Input Frequency 200 MHz tpLH Propagation Delay, Low-to-High 0 ≤ f ≤ 200MHz 1.0 2.3 3.2 ns tpHL Propagation Delay, High-to-Low 1.4 2.3 3.2 ns tsk(o) Output Skew; NOTE 3 250 ps tsk(pp) Par t-to-Par t Skew; NOTE 4 700 ps tR Output Rise Time 0 ≤ f ≤ 200MHz Measured on rising edge @VDDx/2 Measured on rising edge @VDDx/2 0 ≤ f ≤ 200MHz tF Output Fall Time 0 ≤ f ≤ 200MHz tPW Output Pulse Width tCYCLE/2 - 0.5 0.5 0.8 ns 0.9 1.7 tCYCLE/2 + 0.5 ns tCYCLE/2 ns NOTE 1: All parameters measured at fMAX unless noted otherwise. NOTE 2: Outputs terminated with 50Ω resistor connected to VDDx/2. NOTE 3: Defined as skew across outputs at the same supply voltages and with equal load conditio NOTE 4: Defined as skew at different outputs on different devices operating at the same supply voltages and with equal load conditions. 8343I www.icst.com/products/hiperclocks.html 6 REV. B MARCH 8, 2001 ICS8343I Integrated Circuit Systems, Inc. LOW SKEW 1-TO-16 FANOUT BUFFER TABLE 4G. POWER SUPPLY DC CHARACTERISTICS, VDD = VDD1 = VDD2 = 2.5V±5%, TA = -40° TO 85°C Symbol Parameter VDD, VDD1, VDD2 Operating Supply Voltage IDD Input Operating Supply Current Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 100 Units V µA Maximum Units TABLE 4H. LVCMOS DC CHARACTERISTICS, VDD = VDD1 = VDD2 = 2.5V±5%, TA = -40° TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current Test Conditions Minimum Typical CLK VDD = 2.625V 2 VDD + 0.3 V OEx VDD = 2.625V 2 VDD + 0.3 V CLK VDD = 2.375V -0.3 0.8 V -0.3 OEx VDD = 2.375V 0.8 V CLK VIN =VDD 1 µA OEx VIN =VDD 1 µA CLK VIN = 0V -10 µA IIL Input Low Current VIN = 0V -10 µA VOH Output High Voltage VDD = 2.375V, IOH = -25mA 1.5 V OEx VOL Output Low Voltage VDD = 2.375V, IOL = 25mA 0.8 V IOZH High Impedance Leakage Current OEx = 0V, VOUT = VDD 1 µA IOZL High Impedance Leakage Current OEx = 0V, VOUT = 0V -1 µA TABLE 5D. AC CHARACTERISTICS, VDD = VDD1 = VDD2 = 2.5V±5%, TA = -40° TO 85°C Symbol Parameter fMAX Maximum Input Frequency tpLH Propagation Delay, Low-to-High 0 ≤ f ≤ 133MHz 1.0 tpHL Propagation Delay, High-to-Low 1.4 tsk(o) Output Skew; NOTE 3 tsk(pp) Par t-to-Par t Skew; NOTE 4 0 ≤ f ≤ 133MHz Measured on rising edge @VDDx/2 Measured on rising edge @VDDx/2 tR Output Rise Time tF Output Fall Time tPW Test Conditions Minimum tCYCLE/2 - 0.75 Output Pulse Width Typical Maximum Units 133 MHz 2.5 3.7 ns 2.6 3.5 ns 250 ps 750 ps 0.5 0.8 ns 0.9 1.7 tCYCLE/2 + 0.75 ns tCYCLE/2 ns NOTE 1: All parameters measured at fMAX unless noted otherwise. NOTE 2: Outputs terminated with 50Ω resistor connected to VDDx/2. NOTE 3: Defined as skew across outputs at the same supply voltages and with equal load conditions. NOTE 4: Defined as skew at different outputs on different devices operating at the same supply voltages and with equal load conditions. 8343I www.icst.com/products/hiperclocks.html 7 REV. B MARCH 8, 2001 ICS8343I Integrated Circuit Systems, Inc. LOW SKEW 1-TO-16 FANOUT BUFFER PACKAGE OUTLINE - Y SUFFIX D D2 θ E 25 24 32 1 2 3 L E1 E2 N 8 17 16 9 e A D1 A2 -Cccc C b A1 SEATING PLANE c TABLE 6. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N 1.60 A A1 0.05 A2 1.35 1.40 0.15 b 0.30 0.37 c 0.09 1.45 0.45 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 E 9.00 BASIC E1 7.00 BASIC E2 5.60 0.80 BASIC e L 0.45 q 0° 0.60 0.75 7° 0.10 ccc Reference Document: JEDEC Publication 95, MS-026 8343I www.icst.com/products/hiperclocks.html 8 REV. B MARCH 8, 2001 ICS8343I Integrated Circuit Systems, Inc. LOW SKEW 1-TO-16 FANOUT BUFFER TABLE 7. ORDERING INFORMATION Part/Order Number ICS8343YI ICS8343YIT Marking ICS8343YI ICS8343YI Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 2000 Temperature -40°C to 85°C -40°C to 85°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8343I www.icst.com/products/hiperclocks.html 9 REV. B MARCH 8, 2001