NEC UPD753106GC

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD753104, 753106, 753108
4-BIT SINGLE-CHIP MICROCONTROLLER
The µ PD753108 is one of the 75XL Series 4-bit single-chip microcontroller chips and has a data processing
capability comparable to that of an 8-bit microcontroller.
The existing 75X Series containing an LCD controller/driver supplies an 80-pin package.
The µ PD753108 supplies a 64-pin package (12 x 12 mm), which is suitable for small-scale systems.
It features expanded CPU functions and can provide high-speed operation at a low supply voltage of 1.8 V
compared with the existing µ PD75308B.
For detailed function descriptions, refer to the following user’s manual. Be sure to read the document
before designing.
µ PD753108 User’s Manual: U10890E
Features
Low voltage operation: VDD = 1.8 to 5.5 V
• Can be driven by two 1.5-V batteries
On-chip memory
• Program memory (ROM):
4096 x 8 bits (µ PD753104)
6144 x 8 bits (µ PD753106)
8192 x 8 bits (µ PD753108)
• Data memory (RAM):
512 x 4 bits
Capable of high-speed operation and variable instruction execution time for power saving
• 0.95, 1.91, 3.81, 15.3 µ s (@ 4.19 MHz with main system clock)
• 0.67, 1.33, 2.67, 10.7 µ s (@ 6.0 MHz with main system clock)
• 122 µ s (@ 32.768 kHz with subsystem clock)
Internal programmable LCD controller/driver
Small package:
64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
One-time PROM version: µ PD75P3116
Application
Remote controllers, cameras, hemadynamometers, electronic scale, gas meters, etc.
Unless otherwise indicated, references in this data sheet to the µ PD753108 mean the
µ PD753104 and µ PD753106.
The information in this document is subject to change without notice.
The mark
Document No. U10086EJ3V0DS00 (3rd edition)
Date Published April 1997 N
Printed in Japan
shows major revised points.
©
1995
µPD753104, 753106, 753108
Ordering Information
Part number
Package
ROM (x 8 bits)
µ PD753104GC-xxx-AB8
64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
4096
µ PD753104GK-xxx-8A8
64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
4096
µ PD753106GC-xxx-AB8
64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
6144
µ PD753106GK-xxx-8A8
64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
6144
µ PD753108GC-xxx-AB8
64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
8192
µ PD753108GK-xxx-8A8
64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
8192
Remark
2
xxx indicates the ROM code suffix.
µ PD753104, 753106, 753108
Functional Outline
Parameter
Function
• 0.95, 1.91, 3.81, 15.3 µs (@ 4.19 MHz with main system clock)
• 0.67, 1.33, 2.67, 10.7 µs (@ 6.0 MHz with main system clock)
• 122 µs (@ 32.768 kHz with subsystem clock)
Instruction execution time
On-chip memory
ROM
4096 x 8 bits ( µPD753104)
6144 x 8 bits ( µPD753106)
8192 x 8 bits ( µPD753108)
RAM
512 x 4 bits
General-purpose register
• 4-bit operation: 8 x 4 banks
• 8-bit operation: 4 x 4 banks
Input/
output
port
8
CMOS input
CMOS input/output
20
On-chip pull-up resistors which can be specified by software: 7
On-chip pull-up resistors which can be specified by software: 12
Also used for segment pins: 8
N-ch open-drain
input/output pins
Total
LCD controller/driver
4
On-chip pull-up resistors which can be specified by mask option, 13-V withstand
voltage
32
• Segment selection:
16/20/24 segments (can be changed to CMOS input/
output port in 4 time-unit; max. 8)
• Display mode selection: Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias),
1/3 duty (1/3 bias), 1/4 duty (1/3 bias)
• On-chip split resistor for LCD drive can be specified by mask option
Timer
5 channels
• 8-bit timer/event counter: 3 channels (16-bit timer/event counter, carrier generator,
timer with gate)
• Basic interval timer/watchdog timer: 1 channel
• Watch timer: 1 channel
Serial interface
• 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit
• 2-wire serial I/O mode
• SBI mode
Bit sequential buffer (BSB)
16 bits
Clock output (PCL)
• Φ, 524, 262, 65.5 kHz (@ 4.19 MHz with main system clock)
• Φ, 750, 375, 93.8 kHz (@ 6.0 MHz with main system clock)
Buzzer output (BUZ)
• 2, 4, 32 kHz
(@ 4.19 MHz with main system clock or
@ 32.768 kHz with subsystem clock)
• 2.93, 5.86, 46.9 kHz (@ 6.0 MHz with main system clock)
Vectored interrupt
External: 3, Internal: 5
Test input
External: 1, Internal: 1
System clock oscillator
• Ceramic or crystal oscillator for main system clock oscillation
• Crystal oscillator for subsystem clock oscillation
Standby function
STOP/HALT mode
Supply voltage
VDD = 1.8 to 5.5 V
Package
• 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
• 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
3
µPD753104, 753106, 753108
CONTENTS
1. PIN CONFIGURATION (Top View) ......................................................................................................6
2. BLOCK DIAGRAM ................................................................................................................................ 8
3. PIN FUNCTIONS ...................................................................................................................................9
3.1 Port Pins ......................................................................................................................................9
3.2 Non-port Pins ............................................................................................................................ 11
3.3 Pin Input/Output Circuits ......................................................................................................... 13
3.4 Recommended Connections for Unused Pins ....................................................................... 15
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ................................................ 16
4.1 Difference between Mk I Mode and Mk II Mode ......................................................................16
4.2 Setting Method of Stack Bank Select Register (SBS) ...........................................................17
5. MEMORY CONFIGURATION .............................................................................................................18
6. PERIPHERAL HARDWARE FUNCTION ........................................................................................... 23
6.1 Digital I/O Port ........................................................................................................................... 23
6.2 Clock Generator ........................................................................................................................23
6.3 Subsystem Clock Oscillator Control Functions ....................................................................25
6.4 Clock Output Circuit .................................................................................................................26
6.5 Basic Interval Timer/Watchdog Timer ..................................................................................... 27
6.6 Watch Timer .............................................................................................................................. 28
6.7 Timer/Event Counter .................................................................................................................29
6.8 Serial Interface ..........................................................................................................................33
6.9 LCD Controller/Driver ...............................................................................................................35
6.10 Bit Sequential Buffer ................................................................................................................ 37
7. INTERRUPT FUNCTION AND TEST FUNCTION .............................................................................. 38
8. STANDBY FUNCTION ........................................................................................................................40
9. RESET FUNCTION .............................................................................................................................41
10. MASK OPTION ...................................................................................................................................44
11. INSTRUCTION SET ............................................................................................................................ 45
12. ELECTRICAL SPECIFICATIONS ....................................................................................................... 59
13. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) ............................................................... 75
14. PACKAGE DRAWINGS ..................................................................................................................... 78
15. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 80
4
µPD753104, 753106, 753108
APPENDIX A. µPD75308B, 753108 AND 75P3116 FUNCTIONAL LIST .............................................. 81
APPENDIX B. DEVELOPMENT TOOLS ................................................................................................. 83
APPENDIX C. RELATED DOCUMENTS ................................................................................................ 87
5
µ PD753104, 753106, 753108
1. PIN CONFIGURATION (Top View)
• 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
µPD753104GC-xxx-AB8, µPD753106GC-xxx-AB8,
µPD753108GC-xxx-AB8
• 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
COM3
COM2
COM1
COM0
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
µPD753104GK-xxx-8A8, µPD753106GK-xxx-8A8,
µPD753108GK-xxx-8A8
BIAS
1
48
S12
VLC0
2
47
S13
VLC1
3
46
S14
VLC2
4
45
S15
P30/LCDCL
5
44
S16/P93
P31/SYNC
6
43
S17/P92
P32
7
42
S18/P91
P33
8
41
S19/P90
VSS
9
40
S20/P83
P50
10
39
S21/P82
P51
11
38
S22/P81
P52
12
37
S23/P80
6
26
27
28
29
30
31
32
P01/SCK
P03/SI/SB1
P10/INT0
P11/INT1
P12/INT2/TI1/TI2
P13/TI0
25
P02/SO/SB0
24
VDD
X2
P00/INT4
23
X1
IC
P63/KR3
Note
22
P20/PTO0
21
P21/PTO1
33
Note
34
16
20
15
P62/KR2
19
P61/KR1
XT2
P22/PCL/PTO2
XT1
P23/BUZ
35
18
36
14
17
13
RESET
P53
P60/KR0
Connect the IC (Internally Connected) pin directly to VDD.
µ PD753104, 753106, 753108
Pin Identification
P00 to P03
P10 to P13
P20 to P23
P30 to P33
P50 to P53
P60 to P63
P80 to P83
P90 to P93
KR0 to KR3
SCK
SI
SO
SB0, SB1
RESET
S0 to S23
COM0 to COM3
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Port 0
Port 1
Port 2
Port 3
Port 5
Port 6
Port 8
Port 9
Key Return 0 to 3
Serial Clock
Serial Input
Serial Output
Serial Data Bus 0, 1
Reset
Segment Output 0 to 23
Common Output 0 to 3
V LC0 to VLC2
BIAS
LCDCL
SYNC
TI0 to TI2
PTO0 to PTO2
BUZ
PCL
INT0, INT1, INT4
INT2
X1, X2
XT1, XT2
V DD
V SS
IC
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
LCD Power Supply 0 to 2
LCD Power Supply Bias Control
LCD Clock
LCD Synchronization
Timer Input 0 to 2
Programmable Timer Output 0 to 2
Buzzer Clock
Programmable Clock
External Vectored Interrupt 0, 1, 4
External Test Input 2
Main System Clock Oscillation 1, 2
Subsystem Clock Oscillation 1, 2
Positive Power Supply
Ground
Internally Connected
7
8
fLCD
INTT0
INTT1
TOUT0
8-BIT
TIMER/EVENT
COUNTER #0
INTBT
BASIC
INTERVAL
TIMER/
WATCHDOG
TIMER
INTW
WATCH
TIMER
INT0/P10
INT1/P11
INT4/P00
INT2/P12/TI1/TI2
KR0/P60 to
KR3/P63
4
BIT SEQ.
BUFFER (16)
INTERRUPT
CONTROL
INT1
INTCSI TOUT0
CLOCKED
SERIAL
INTERFACE
INTT2
8-BIT
TIMER/EVENT CASCADED
COUNTER #1 16-BIT
TIMER/
8-BIT
EVENT
TIMER/EVENT COUNTER
COUNTER #2
SI/SB1/P03
SO/SB0/P02
SCK/P01
PTO2/PCL/P22
TOUT0
PTO1/P21
TI1/TI2/P12/INT2
PTO0/P20
TI0/P13
BUZ/P23
CPU
CLOCK Φ
DECODE
AND
CONTROL
ALU
Note
PCL/PTO2/P22
BANK
SBS
SP(8)
IC
VDD
DATA MEMORY
(RAM)
512 x 4 BITS
GENERAL REG.
CY
The ROM capacity depends on the product.
X1 X2 XT1XT2
CLOCK
CLOCK SYSTEM CLOCK
STAND BY
OUTPUT DIVIDER GENERATOR
CONTROL
CONTROL
MAIN SUB
N
fx/2
PROGRAM
MEMORY Note
(ROM)
PROGRAM
COUNTER
VSS RESET
fLCD
4
4
BIAS
VLC0
VLC1
VLC2
SYNC/P31
LCDCL/P30
COM0 to COM3
S20/P83 to
S23/P80
4
4
S16/P93 to
S19/P90
4
S0 to S15
P90 to P93
P80 to P83
LCD
CONTROLLER/ 16
DRIVER
PORT9
PORT8
P60 to P63
P50 to P53
4
PORT5
4
P30 to P33
4
PORT3
PORT6
P20 to P23
4
4 P10 to P13
PORT1
PORT2
4 P00 to P03
PORT0
µ PD753104, 753106, 753108
2. BLOCK DIAGRAM
µ PD753104, 753106, 753108
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Pin Name
Input/Output
Alternate
Function
P00
Input
INT4
P01
Input/Output
SCK
P02
Input/Output
SO/SB0
P03
Input/Output
SI/SB1
P10
Input
INT0
P11
INT1
P12
TI1/TI2/INT2
P13
TI0
P20
Input/Output
PTO0
P21
PTO1
P22
PCL/PTO2
P23
BUZ
P30
Input/Output
LCDCL
P31
SYNC
P32
–
P33
–
P50-P53 Note 2
Notes 1.
2.
Input/Output
–
Function
4-bit input port (PORT0).
For P01 to P03, connection of on-chip pullup resistors can be specified by software in
3-bit units.
8-bit
I/O
No
After Reset
I/O Circuit
TYPE Note 1
Input
(B)
(F)-A
(F)-B
(M)-C
4-bit input port (PORT1).
Connection of on-chip pull-up resistors can
be specified by software in 4-bit units.
P10/INT0 can select noise elimination
circuit.
No
Input
(B)-C
4-bit input/output port (PORT2).
Connection of on-chip pull-up resistors can
be specified by software in 4-bit units.
No
Input
E-B
Programmable 4-bit input/output port
(PORT3).
This port can be specified for input/output
bit-wise.
Connection of on-chip pull-up resistors can
be specified by software in 4-bit units.
No
Input
E-B
N-ch open-drain 4-bit input/output port
(PORT5).
A pull-up resistor can be contained bit-wise
(mask option).
Withstand voltage is 13 V in open-drain mode.
No
High level
(when pullup resistors
are provided)
or highimpedance
M-D
Characters in parentheses indicate the Schmitt trigger input.
If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port),
low-level input leakage current increases when input or bit manipulation instruction is executed.
9
µ PD753104, 753106, 753108
3.1 Port Pins (2/2)
Pin Name
P60
Input/Output
Input/Output
Alternate
Function
KR0
P61
KR1
P62
KR2
P63
KR3
P80
Input/Output
S23
P81
S22
P82
S21
P83
S20
P90
Input/Output
S19
P91
S18
P92
S17
P93
S16
Notes 1.
2.
8-bit
I/O
After Reset
I/O Circuit
TYPE Note 1
Programmable 4-bit input/output port
(PORT6).
This port can be specified for input/output
bit-wise.
Connection of on-chip pull-up resistors can
be specified by software in 4-bit units.
No
Input
(F)-A
4-bit input/output port (PORT8).
Connection of on-chip pull-up resistors can
be specified by software in 4-bit units Note 2 .
Yes
Input
H
Input
H
4-bit input/output port (PORT9).
Connection of on-chip pull-up resistors can
be specified by software in 4-bit units Note 2 .
Characters in parentheses indicate the Schmitt trigger input.
When these pins are used as segment signal output pins, do not connect the on-chip pull-up resistor
by software.
10
Function
µ PD753104, 753106, 753108
3.2 Non-port Pins (1/2)
Pin Name
TI0
Input/Output
Input
Alternate
P13
TI1
P12/INT2/TI2
TI2
P12/INT2/TI1
PTO0
Output
After Reset
I/O Circuit
TYPE Note 1
Inputs external event pulses to the timer/event
counter.
Input
(B)-C
Timer/event counter output
Input
E-B
Input
(F)-A
Function
Function
P20
PTO1
P21
PTO2
P22/PCL
PCL
P22/PTO2
BUZ
P23
Optional frequency output (for buzzer output or
system clock trimming)
P01
Serial clock input/output
SO/SB0
P02
Serial data output
Serial data bus input/output
(F)-B
SI/SB1
P03
Serial data input
Serial data bus input/output
(M)-C
SCK
Input/Output
Clock output
INT4
Input
P00
Edge detection vectored interrupt input (both
rising edge and falling edge detection)
Input
(B)
INT0
Input
P10
Edge detection vectored
interrupt input (detection
edge can be selected).
INT0/P10 can select noise
elimination circuit.
Rising edge detection
testable input
Input
(B)-C
Input
(F)-A
INT1
P11
INT2
P12/TI1/TI2
KR0-KR3
Noise elimination circuit/
asynchronous selection
Asynchronous
Asynchronous
Input
P60-P63
S0-S15
Output
–
Segment signal output
Note 2
G-A
S16-S19
Output
P93-P90
Segment signal output
Input
H
S20-S23
Output
P83-P80
Segment signal output
Input
H
COM0-COM3
Output
–
Common signal output
Note 2
G-B
–
–
LCD drive power
On-chip split resistor is enabled (mask option).
–
–
BIAS
Output
–
Output for external split resistor disconnect
Note 3
–
LCDCL Note 4
Output
P30
Clock output for externally expanded driver
Input
E-B
SYNC Note 4
Output
P31
Clock output for externally expanded driver
synchronization
Input
E-B
VLC0 -VLC2
Notes 1.
2.
3.
4.
Falling edge detection testable input
Characters in parentheses indicate the Schmitt trigger input.
Each display output selects the following VLCX as input source.
S0-S15: VLC1, COM0-COM2: V LC2, COM3: VLC0
When a split resistor is contained ........ Low level
When no split resistor is contained ...... High-impedance
These pins are provided for future system expansion.
At present, these pins are used only as pins P30 and P31.
11
µ PD753104, 753106, 753108
3.2 Non-port Pins (2/2)
Alternate
Function
After Reset
I/O Circuit
TYPE Note
–
Crystal/ceramic connection pin for the main
system clock oscillation. When the external
clock is used, input the external clock to pin
X1, and the inverted phase of the external clock
to pin X2.
–
–
–
Crystal connection pin for the subsystem clock
oscillation. When the external clock is used, input
the external clock to pin XT1, and the inverted
phase of the external clock to pin XT2. Pin XT1 can
be used as a 1-bit input (test) pin.
–
–
Input
–
System reset input (low-level active)
–
(B)
IC
–
–
Internally connected. Connect directly to V DD.
–
–
VDD
–
–
Positive power supply
–
–
VSS
–
–
Ground potential
–
–
Pin Name
Input/Output
X1
Input
X2
–
XT1
Input
XT2
–
RESET
Note
12
Function
Characters in parentheses indicate the Schmitt trigger input.
µ PD753104, 753106, 753108
3.3 Pin Input/Output Circuits
The µ PD753108 pin input/output circuits are shown schematically.
(1/2)
TYPE A
TYPE D
VDD
VDD
data
P-ch
OUT
P-ch
IN
output
disable
N-ch
N-ch
Push-pull output that can be placed in output
high-impedance (both P-ch and N-ch off).
CMOS standard input buffer
TYPE E-B
TYPE B
VDD
P.U.R.
P.U.R.
enable
P-ch
IN
data
Type D
IN/OUT
output
disable
Type A
Schmitt trigger input with hysteresis characteristics
P.U.R. : Pull-Up Resistor
TYPE F-A
TYPE B-C
VDD
VDD
P.U.R.
P.U.R.
enable
P.U.R.
P-ch
P.U.R.
enable
P-ch
data
output
disable
IN/OUT
Type D
IN
Type B
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
13
µ PD753104, 753106, 753108
(2/2)
TYPE F-B
TYPE H
VDD
P.U.R.
P.U.R
enable
P-ch
output
disable
(P)
SEG
data
VDD
IN/OUT
TYPE G-A
P-ch
IN/OUT
data
output
disable
data
N-ch
output
disable
output
disable
(N)
TYPE E-B
P.U.R. : Pull-Up Resistor
TYPE G-A
TYPE M-C
VDD
P-ch
N-ch
VLC0
VLC1
P.U.R.
P-ch
N-ch
P.U.R.
enable
P-ch
P-ch N-ch
IN/OUT
data
OUT
N-ch
output
disable
SEG
data
N-ch
P-ch
N-ch
VLC2
N-ch
P.U.R. : Pull-Up Resistor
TYPE G-B
TYPE M-D
P.U.R.
(Mask Option)
P-ch
N-ch
VLC0
VLC1
IN/OUT
data
P-ch
N-ch
P-ch
output
disable
N-ch
OUT
input
instruction
COM
data
N-ch
(+13 V
withstand
voltage)
VDD
P-ch
Note
P.U.R.
N-ch
P-ch
P-ch
N-ch
VLC2
Voltage limitation
circuit
(+13 V withstand
voltage)
N-ch
Note
14
VDD
The pull-up resistor operates only when an input
instruction is executed (current flows from VDD to
the pin when the pin is low).
µ PD753104, 753106, 753108
3.4 Recommended Connections for Unused Pins
Table 3-1. List of Recommended Connections for Unused Pins
Pin
Recommended Connection
P00/INT4
Connect to VSS or V DD
P01/SCK
Connect to VSS or VDD via a resistor individually
P02/SO/SB0
P03/SI/SB1
Connect to VSS
P10/INT0, P11/INT1
Connect to VSS or VDD
P12/TI1/TI2/INT2
P13/TI0
P20/PTO0
Input state:
P21/PTO1
P22/PCL/PTO2
Connect to V SS or V DD via a resistor
individually
Output state: Leave open
P23/BUZ
P30/LCDCL
P31/SYNC
P32
P33
P50-P53
Input state:
Connect to V SS
Output state: Connect to V SS (do not connect a
pull-up resistor of mask option)
P60/KR0-P63/KR3
Input state:
Connect to V SS or V DD via a resistor
individually
Output state: Leave open
S0-S15
Leave open
COM0-COM3
S16/P93-S19/P90
Input state:
Connect to V SS or V DD via a resistor
individually
S20/P83-S23/P80
Output state: Leave open
VLC0-V LC2
Connect to VSS
BIAS
Only if all of VLC0 to V LC2 are unused, connect to V SS.
In other cases, leave open.
XT1 Note
Connect to VSS or VDD
XT2 Note
Leave open
IC
Connect directly to V DD
Note
When the subsystem clock is not used, specify SOS.0 = 1 (so as not
to use the on-chip feedback resistor).
15
µ PD753104, 753106, 753108
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE
4.1 Difference between Mk I Mode and Mk II Mode
The CPU of the µPD753108 has the following two modes: Mk I and Mk II, either of which can be selected. The
mode can be switched by bit 3 of the stack bank select register (SBS).
• Mk I mode:
Upward compatible with the µPD75308B. Can be used in the 75XL CPU with a ROM capacity
of up to 16 Kbytes.
• Mk II mode: Incompatible with the µ PD75308B. Can be used in all the 75XL CPU’s including those products
whose ROM capacity is more than 16 Kbytes.
Table 4-1. Differences between Mk I Mode and Mk II Mode
Mk I mode
Mk II mode
Number of stack bytes
for subroutine instructions
2 bytes
3 bytes
BRA !addr1 instruction
CALLA !addr1 instruction
Not available
Available
CALL !addr instruction
3 machine cycles
4 machine cycles
CALLF !faddr instruction
2 machine cycles
3 machine cycles
Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL
Series. Therefore, this mode is effective for enhancing software compatibility with
products exceeding 16 Kbytes.
When the Mk II mode is selected, the number of stack bytes used during execution of
subroutine call instructions increases by one byte per stack compared to the Mk I mode.
When the CALL !addr and CALLF !faddr instructions are used, the machine cycle
becomes longer by one machine cycle.
Therefore, use the Mk I mode if the RAM
efficiency and processing performance are more important than software compatibility.
16
µ PD753104, 753106, 753108
4.2 Setting Method of Stack Bank Select Register (SBS)
Switching between the Mk I mode and Mk II mode can be done by the stack bank select register (SBS). Figure
4-1 shows the format.
The SBS is set by a 4-bit memory manipulation instruction.
When using the Mk I mode, the SBS must be initialized to 100xB Note at the beginning of a program. When using
the Mk II mode, it must be initialized to 000xB Note.
Note
Set the desired value in the x position.
Figure 4-1. Stack Bank Select Register Format
Address
3
F84H
SBS3
2
1
SBS2 SBS1
0
Symbol
SBS0
SBS
Stack area specification
0
0
Memory bank 0
0
1
Memory bank 1
Other than above setting prohibited
0
0 must be set in the bit 2 position.
Mode switching specification
0
Mk II mode
1
Mk I mode
Caution Since SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the Mk
I mode. When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select the
Mk II mode.
17
µ PD753104, 753106, 753108
5. MEMORY CONFIGURATION
Program Memory (ROM) .... 4096 x 8 bits ( µPD753104)
.... 6144 x 8 bits ( µPD753106)
.... 8192 x 8 bits ( µPD753108)
• Addresses 0000H and 0001H
Vector table wherein the program start address and the values set for the RBE and MBE at the time a
RESET signal is generated are written. Reset start is possible from any address.
• Addresses 0002H to 000DH
Vector table wherein the program start address and the values set for the RBE and MBE by each vectored
interrupt are written. Interrupt processing can start from any address.
• Addresses 0020H to 007FH
Table area referenced by the GETI instruction Note.
Note
The GETI instruction realizes a 1-byte instruction on behalf of any 2-byte instruction, 3-byte
instruction, or two 1-byte instructions. It is used to decrease the number of program steps.
Data Memory (RAM)
• Data area ... 512 words x 4 bits (000H to 1FFH)
• Peripheral hardware area ... 128 words x 4 bits (F80H to FFFH)
18
µ PD753104, 753106, 753108
Figure 5-1. Program Memory Map (1/3)
(a) µPD753104
Address
7
6
0 0 0 H MBE RBE
0 0 2 H MBE RBE
0 0 4 H MBE RBE
0 0 6 H MBE RBE
0 0 8 H MBE RBE
0 0 A H MBE RBE
0 0 C H MBE RBE
5
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal reset start address
(high-order 4 bits)
Internal reset start address
(low-order 8 bits)
INTBT/INT4
start address
(high-order 4 bits)
INTBT/INT4
start address
(low-order 8 bits)
INT0
start address
(high-order 4 bits)
INT0
start address
(low-order 8 bits)
INT1
start address
(high-order 4 bits)
INT1
start address
(low-order 8 bits)
INTCSI
start address
(high-order 4 bits)
INTCSI
start address
(low-order 8 bits)
INTT0
start address
(high-order 4 bits)
INTT0
start address
(low-order 8 bits)
INTT1/INTT2
start address
(high-order 4 bits)
INTT1/INTT2
start address
(low-order 8 bits)
CALLF
!faddr
instruction
entry
address
Branch address
of BR BCXA, BR
BCDE, BR !addr,
BRA !addr1 Note or
CALLA !addr1 Note
instruction
CALL !addr
instruction
subroutine entry
address
BR $addr
instruction relative
branch address
–15 to –1,
+2 to +16
BRCB !caddr
instruction
branch
address
020H
GETI instruction reference table
07FH
080H
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
7FFH
800H
FFFH
Note
Can be used in Mk II mode only.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
19
µ PD753104, 753106, 753108
Figure 5-1. Program Memory Map (2/3)
(b) µPD753106
Address
7
6
0 0 0 0 H MBE RBE
0 0 0 2 H MBE RBE
0 0 0 4 H MBE RBE
0 0 0 6 H MBE RBE
0 0 0 8 H MBE RBE
0 0 0 A H MBE RBE
0 0 0 C H MBE RBE
5
0
0
0
0
0
0
0
0
Internal reset start address
(high-order 5 bits)
Internal reset start address
(low-order 8 bits)
INTBT/INT4
start address
(high-order 5 bits)
INTBT/INT4
start address
(low-order 8 bits)
INT0
start address
(high-order 5 bits)
INT0
start address
(low-order 8 bits)
INT1
start address
(high-order 5 bits)
INT1
start address
(low-order 8 bits)
INTCSI
start address
(high-order 5 bits)
INTCSI
start address
(low-order 8 bits)
INTT0
start address
(high-order 5 bits)
INTT0
start address
(low-order 8 bits)
INTT1/INTT2
start address
(high-order 5 bits)
INTT1/INTT2
start address
(low-order 8 bits)
CALLF
!faddr
instruction
entry
address
Branch address
of BR BCXA, BR
BCDE, BR !addr,
BRA !addr1 Note or
CALLA !addr1 Note
instruction
CALL !addr
instruction
subroutine entry
address
BR $addr
instruction relative
branch address
–15 to –1,
+2 to +16
BRCB !caddr
instruction
branch
address
0020H
GETI instruction reference table
007FH
0080H
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
07FFH
0800H
0FFFH
1000H
BRCB !caddr
instruction
branch
address
17FFH
Note
Can be used in Mk II mode only.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
20
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
µ PD753104, 753106, 753108
Figure 5-1. Program Memory Map (3/3)
(c) µPD753108
Address
7
6
0 0 0 0 H MBE RBE
0 0 0 2 H MBE RBE
0 0 0 4 H MBE RBE
0 0 0 6 H MBE RBE
0 0 0 8 H MBE RBE
0 0 0 A H MBE RBE
0 0 0 C H MBE RBE
5
0
0
0
0
0
0
0
0
Internal reset start address
(high-order 5 bits)
Internal reset start address
(low-order 8 bits)
INTBT/INT4
start address
(high-order 5 bits)
INTBT/INT4
start address
(low-order 8 bits)
INT0
start address
(high-order 5 bits)
INT0
start address
(low-order 8 bits)
INT1
start address
(high-order 5 bits)
INT1
start address
(low-order 8 bits)
INTCSI
start address
(high-order 5 bits)
INTCSI
start address
(low-order 8 bits)
INTT0
start address
(high-order 5 bits)
INTT0
start address
(low-order 8 bits)
INTT1/INTT2
start address
(high-order 5 bits)
INTT1/INTT2
start address
(low-order 8 bits)
CALLF
!faddr
instruction
entry
address
Branch address
of BR BCXA, BR
BCDE, BR !addr,
BRA !addr1 Note or
CALLA !addr1 Note
instruction
CALL !addr
instruction
subroutine entry
address
BR $addr
instruction relative
branch address
–15 to –1,
+2 to +16
BRCB !caddr
instruction
branch
address
0020H
GETI instruction reference table
007FH
0080H
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
07FFH
0800H
0FFFH
1000H
BRCB !caddr
instruction
branch
address
1FFFH
Note
Can be used in Mk II mode only.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
21
µ PD753104, 753106, 753108
Figure 5-2. Data Memory Map
Data memory
000H
General-purpose
register area
Memory bank
(32 x 4)
01FH
0
256 x 4
(224 x 4)
Stack area Note
Data area
static RAM
(512 x 4)
0FFH
100H
256 x 4
(224 x 4)
1
Display data
memory
1DFH
1E0H
(24 x 4)
1F7H
1F8H
1FFH
(8 x 4)
Not incorporated
F80H
128 x 4
Peripheral hardware area
FFFH
Note
22
Either memory bank 0 or 1 can be selected for the stack area.
15
µ PD753104, 753106, 753108
6. PERIPHERAL HARDWARE FUNCTION
6.1 Digital I/O Port
There are three kinds of I/O port.
• CMOS input ports (PORT 0, 1)
: 8
• CMOS input/output ports (PORT 2, 3, 6, 8, 9) : 20
• N-ch open-drain input/output ports (PORT 5) : 4
Total
32
Table 6-1. Types and Features of Digital Ports
Port name
PORT0
Function
4-bit input
PORT1
PORT2
4-bit input/
output
PORT3
Operation and features
Remarks
When the serial interface function is used, the dual
function pins function as output ports depending on the
operation mode.
Also used for the INT4, SCK,
SO/SB0, SI/SB1 pins.
4-bit input only port.
Also used for the INT0-INT2/
TI1/TI2, TI0 pins.
Can be set to input mode or output mode in 4-bit units.
Also used for the PTO0PTO2/PCL, BUZ pins.
Can be set to input mode or output mode bit-wise.
Also used for the LCDCL,
SYNC pins.
PORT5
4-bit input/
output
(N-ch opendrain, 13 V
withstand
voltage)
Can be set to input mode or output mode in 4-bit units.
On-chip pull-up resistor can be specified bit-wise
by mask option.
PORT6
4-bit input/
output
Can be set to input mode or output mode bit-wise.
Also used for the KR0-KR3 pins.
Can be set to input
mode or output mode
in 4-bit units.
Also used for the S20-S23 pins.
PORT8
PORT9
Ports 8 and 9 are paired
and data can be input/
output in 8-bit units.
—
Also used for the S16-S19 pins.
6.2 Clock Generator
The clock generator is a device that generates the clock which is supplied to peripheral hardware on the CPU
and is configured as shown in Figure 6-1.
The clock generator operates according to how the processor clock control register (PCC) and system clock
control register (SCC) are set.
There are two kinds of clocks, main system clock and subsystem clock.
The instruction execution time can also be changed.
• 0.95, 1.91, 3.81, 15.3 µs (main system clock: in 4.19-MHz operation)
• 0.67, 1.33, 2.67, 10.7 µs (main system clock: in 6.0-MHz operation)
• 122 µ s (subsystem clock: in 32.768-kHz operation)
23
µ PD753104, 753106, 753108
Figure 6-1. Clock Generator Block Diagram
· Basic interval timer (BT)
· Timer/event counter
· Serial interface
· Watch timer
· LCD controller/driver
· INT0 noise elimination circuit
· Clock output circuit
XT1
VDD
XT2
Subsystem
clock oscillator
fXT
Main system
clock oscillator
fX
LCD controller/driver
Watch timer
X1
VDD
X2
1/1 to 1/4096
Divider
1/2 1/4 1/16
Selector
WM.3
SCC
Oscillation
stop
SCC3
Divider
Selector
1/4
Internal bus
SCC0
PCC
Φ
· CPU
· INT0 noise
elimination circuit
· Clock output circuit
PCC0
PCC1
4
HALT F/F
PCC2
S
HALT Note
PCC3
STOP Note
R
PCC2,
PCC3
Clear
STOP F/F
Q
Q
Wait release signal from BT
S
RESET signal
R
Standby release signal from
interrupt control circuit
Note Instruction execution
Remarks 1.
24
f X = Main system clock frequency
2.
f XT = Subsystem clock frequency
3.
Φ = CPU clock
4.
PCC: Processor Clock Control Register
5.
SCC: System Clock Control Register
6.
One clock cycle (tCY ) of the CPU clock is equal to one machine cycle of the instruction.
µ PD753104, 753106, 753108
6.3 Subsystem Clock Oscillator Control Functions
The µ PD753108 subsystem clock oscillator has the following two control functions.
• Selects by software whether an on-chip feedback resistor is to be used or not Note.
• Reduces current consumption by decreasing the drive current of the on-chip inverter when the supply voltage
is high (V DD ≥ 2.7 V).
Note When the subsystem clock is not used, set SOS.0 to 1 (so as not to use the on-chip feedback resistor) by
software, connect XT1 to V SS or VDD, and open XT2.
This makes it possible to reduce the current
consumption in the subsystem clock oscillator.
The above functions can be used by switching the bits 0 and 1 of the sub-oscillator control register (SOS). (See
Figure 6-2.)
Figure 6-2. Subsystem Clock Oscillator
SOS.0
Feedback resistor
Inverter
SOS.1
XT1
XT2
VDD
25
µ PD753104, 753106, 753108
6.4 Clock Output Circuit
The clock output circuit is provided to output the clock pulses from the P22/PTO2/PCL pin to the remote control
wave outputs and peripheral LSI’s.
Clock output (PCL): Φ, 524, 262, 65.5 kHz (main system clock: in 4.19-MHz operation)
Φ, 750, 375, 93.8 kHz (main system clock: in 6.0-MHz operation)
Figure 6-3. Clock Output Circuit Block Diagram
From clock
generator
Φ
Selector
From timer/event
counter
(channel 2)
fX/23
Selector
Output buffer
fX/24
PCL/PTO2/P22
fX/26
PORT2.2
CLOM3
0
CLOM1 CLOM0
P22
output latch
CLOM
Bit 2 of PMGB
Port 2 I/O mode
specification bit
4
Internal bus
Remark Special care has been taken in designing the chip so that small-width pulses may not be output
when switching clock output enable/disable.
26
µ PD753104, 753106, 753108
6.5 Basic Interval Timer/Watchdog Timer
The basic interval timer/watchdog timer has the following functions.
Interval timer operation to generate a reference time interrupt
Watchdog timer operation to detect a runaway of program and reset the CPU
Selects and counts the wait time when the standby mode is released
Reads the contents of counting
Figure 6-4. Basic Interval Timer/Watchdog Timer Block Diagram
From clock
generator
Clear
fX/25
fX/27
MPX
Clear
Basic interval timer
(8-bit frequency divider)
Set
fX/29
BT
fX/212
3
Wait release signal
when standby is
released.
BTM3 BTM2 BTM1 BTM0 BTM
SET1 Note
4
BT
interrupt
request flag Vectored
interrupt
IRQBT request signal
Internal reset
signal
WDTM
SET1 Note
8
1
Internal bus
Note Instruction execution
27
µ PD753104, 753106, 753108
6.6 Watch Timer
The µ PD753108 has one watch timer channel which has the following functions.
Sets the test flag (IRQW) at 0.5-second intervals. The standby mode can be released by the IRQW.
0.5-second interval can be created by both the main system clock (4.194304 MHz) and subsystem clock
(32.768 kHz).
Convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the
fast feed mode.
Outputs the frequencies (2.048, 4.096, 32.768 kHz) to the P23/BUZ pin, usable for buzzer and trimming of
system clock oscillation frequencies.
Clears the frequency divider to make the watch start with zero seconds.
Figure 6-5. Watch Timer Block Diagram
fW
(512 Hz : 1.95 ms)
26
fW (256 Hz : 3.91 ms)
27
fX
128
From
clock
generator
(32.768 kHz)
Selector
fW
(32.768 kHz)
Divider
fXT
(32.768 kHz)
fW
214
fLCD
INTW
IRQW
set signal
Selector
2 Hz
0.5 sec
4 kHz 2 kHz
fW
fW
23
24
Clear
Selector
Output buffer
P23/BUZ
WM
WM7
PORT2.3
0
WM5
WM4
WM3
8
WM2
WM1
WM0
P23
output latch
Bit 2 of PMGB
Port 2 input/
output mode
Bit test instruction
Internal bus
Remark The values enclosed in parentheses are applied when f X = 4.194304 MHz and f XT = 32.768 kHz.
28
µ PD753104, 753106, 753108
6.7 Timer/Event Counter
The µ PD753108 has three channels of timer/event counters. Its configuration is shown in Figures 6-6 to 6-8.
The timer/event counter has the following functions.
Programmable interval timer operation
Square wave output of any frequency to the PTOn pin (n = 0 to 2)
Event counter operation
Divides the frequency of signal input via the TIn pin to 1-Nth of the original signal and outputs the divided
frequency to the PTOn pin (frequency divider operation).
Supplies the serial shift clock to the serial interface circuit.
Reads the count value.
The timer/event counter operates in the following four modes as set by the mode register.
Table 6-2. Operation Modes of Timer/Event Counter
Channel
Channel 0
Channel 1
Channel 2
Yes
Yes
Yes
No Note
No
Yes
PWM pulse generator mode
No
No
Yes
16-bit timer/event counter mode
No
Yes
No Note
Yes
No
Yes
Mode
8-bit timer/event counter mode
Gate control function
Gate control function
Carrier generator mode
Note Used for gate control signal generation
29
30
Caution
SET1 Note
From
fX/2
clock
fX/28
generator
fX/210
6
fX/24
–
Timer operation start
0
TM0
8
CP
When setting data to TM0, be sure to set bit 1 to 0.
MPX
TM06 TM05 TM04 TM03 TM02
Note Instruction execution
TI0/P13
Input
buffer
PORT1.3
–
8
Clear
Count register (8)
8
Comparator (8)
8
T0
TMOD0
Modulo register (8)
8
Internal bus
Match
TOE0
TOUT0
T0
enable flag
RESET
IRQT0
clear signal
INTT0
IRQT0
set signal
Output buffer
PTO0/P20
PORT2.0
Bit 2 of PMGB
Port 2
input/output
mode
To serial interface
P20
output latch
To timer/event counter (channel 2)
Reset
TOUT
F/F
Figure 6-6. Timer/Event Counter (Channel 0) Block Diagram
µ PD753104, 753106, 753108
SET1 Note
TM1
fX/2
fX/26
From clock
8
generator fX/2 10
fX/2
fX/212
5
Timer/event counter
(channel 2) output
MPX
8
Match
TOE1
T1
enable flag
INTT1
IRQT1
set signal
IRQT1 clear signal
RESET
Output buffer
P21/PTO1
Bit 2 of PMGB
Port 2
input/output
mode
PORT2.1
P21
output latch
Timer/event counter (channel 2) reload signal
Reset
TOUT
F/F
Timer/event counter (channel 2) comparator
(When 16-bit timer/event counter mode)
Timer/event counter (channel 2) match signal
(When 16-bit timer/event counter mode)
Selector
Clear
Count register (8)
8
Comparator (8)
8
T1
TMOD1
Modulo register (8)
Timer operation start
CP
16-bit timer/event counter mode
Decoder
TM16 TM15 TM14 TM13 TM12 TM11 TM10
Note Instruction execution
TI1/TI2/P12/INT2
Input buffer
PORT1.2
–
8
Internal bus
Figure 6-7. Timer/Event Counter (Channel 1) Block Diagram
µ PD753104, 753106, 753108
31
fX
fX/2
From clock fX/24
fX/26
generator
fX/28
fX/210
Note Instruction execution
TI1/TI2/P12/INT2
Input buffer
PORT1.2
TM2
SET1 Note
MPX
CP
MPX (8)
8
8
Match
Timer operation start
Timer/event counter
(channel 1) clear signal
(When 16-bit timer/event
counter mode)
Reset
TOUT
F/F
Timer/event counter
(channel 1) match signal
(When 16-bit timer/event
counter mode)
Clear
8
T2
Count register (8)
Comparator (8)
8
8
TMOD2
Modulo register (8) TGCE
TMOD2H
High-level period setting
modulo register (8)
8
16-bit timer/event counter mode
Timer event counter
(channel 0) TOUT F/F
Decoder
TM26 TM25 TM24 TM23 TM22 TM21 TM20
8
Internal bus
TC2
Selector
Timer/event counter
(channel 1) match signal
(When carrier generator mode)
Output buffer
RESET
IRQT2 clear signal
INTT2
IRQT2
set signal
Timer/event counter
(channel 1) clock input
P22/PCL/PTO2
PORT2.2 Bit 2 of PMGB
P22
Port 2
output latch input/output
From clock output circuit
Carrier generator mode
Overflow
Reload
TOE2 REMC NRZB NRZ
8
Selector
32
Selector
Figure 6-8. Timer/Event Counter (Channel 2) Block Diagram
µ PD753104, 753106, 753108
µ PD753104, 753106, 753108
6.8 Serial Interface
The µ PD753108 incorporates a clock-synchronous 8-bit serial interface. The serial interface can be used in
the following four modes.
• Operation stop mode
• 3-wire serial I/O mode
• 2-wire serial I/O mode
• SBI mode
33
P01/SCK
P02/SO/SB0
P03/SI/SB1
P01
output Iatch
Selector
Selector
CSIM
8/4
8
8
8
Serial clock control
circuit
Serial clock counter
Bus release/
command/
acknowledge
detection circuit
Shift register (SIO)
Address comparator
D
INTCSI
control circuit
Q
SO latch
CMDT
SET CLR
RELD
CMDD
ACKD
(8)
(8)
Match
RELT
Bit manipulation
Slave address register (SVA) (8)
Internal bus
SBIC
fX/23
fX/24
fX/26
TOUT0
(from timer/event
counter (channel 0))
IRQCSI
set signal
INTCSI
Bit test
External SCK
Serial clock
selector
Busy/
acknowledge
output circuit
ACKT
Bit test
ACKE
34
BSYE
Figure 6-9. Serial Interface Block Diagram
µ PD753104, 753106, 753108
µ PD753104, 753106, 753108
6.9 LCD Controller/Driver
The µPD753108 incorporates a display controller which generates segment and common signals according to
the display data memory contents and incorporates segment and common drivers which can drive the LCD panel
directly.
The µ PD753108 LCD controller/driver has the following functions:
Display data memory is read automatically by DMA operation and segment and common signals are
generated.
Display mode can be selected from among the following five:
<1> Static
<2> 1/2 duty (time multiplexing by 2), 1/2 bias
<3> 1/3 duty (time multiplexing by 3), 1/2 bias
<4> 1/3 duty (time multiplexing by 3), 1/3 bias
<5> 1/4 duty (time multiplexing by 4), 1/3 bias
A frame frequency can be selected from among four in each display mode.
A maximum of 24 segment signal output pins (S0 to S23) and four common signal output pins (COM0 to
COM3).
The segment signal output pins (S0 to S23) can be changed to the I/O ports (PORT8 and PORT9).
Split resistor can be incorporated to supply LCD drive power (mask option).
• Various bias methods and LCD drive voltages are applicable.
• When display is off, current flowing through the split resistor is cut.
Display data memory not used for display can be used for normal data memory.
It can also operate by using the subsystem clock.
35
36
1
2
3
0
3
0
2
Port 9
Input/output buffer
Port 8
Input/output buffer
1
3 2 1 0
4
3 2 1 0
4
Port 9
output latch
4
Port 8
output latch
4
8
register group C
0
1
Port mode
4
Decoder
LCD/port
selection
register
S23/P80
S16/P93
S15
S0
3 2 1 0
1E0H
3 2 1 0
Segment driver
3 2 1 0 3 2 1 0
1F0H
1EFH
3 2 1 0 3 2 1 0
Segment driver
3 2 1 0
1F7H
3 2 1 0
4
Internal bus
8
4
LCD drive
voltage control
Display
control
register
COM3 COM2 COM1 COM0 VLC2 VLC1 VLC0
Common driver
Timing fLCD
controller
Display mode register
Figure 6-10. LCD Controller/Driver Block Diagram
LCD drive
mode
switching
4
4
0
1
0
P31/SYNC P30/LCDCL
1
Port 3
Port mode
output latch register group A
µPD753104, 753106, 753108
µ PD753104, 753106, 753108
6.10 Bit Sequential Buffer ....... 16 Bits
The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be
easily performed by changing the address specification and bit specification in sequence, therefore it is useful
when processing a long data bit-wise.
Figure 6-11. Bit Sequential Buffer Format
FC3H
Address
3
Bit
Symbol
L register
2
1
FC2H
0
3
2
BSB3
L = FH
1
FC1H
0
3
BSB2
L = CH L = BH
2
1
FC0H
0
3
BSB1
L = 8H L = 7H
2
1
0
BSB0
L = 4H L = 3H
L = 0H
DECS L
INCS L
Remarks 1.
2.
In the pmem.@L addressing, the specified bit moves corresponding to the L register.
In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MBS specification.
37
µPD753104, 753106, 753108
7. INTERRUPT FUNCTION AND TEST FUNCTION
The µ PD753108 has eight types of interrupt sources and two types of test sources. Of these test sources, INT2
has two types of edge detection testable inputs.
The interrupt control circuit of the µ PD753108 has the following functions.
(1) Interrupt function
• Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the
interrupt enable flag (IExxx) and interrupt master enable flag (IME).
• Can set any interrupt start address.
• Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS).
• Test function of interrupt request flag (IRQxxx). An interrupt generation can be checked by software.
• Release the standby mode. An interrupt to be released can be selected by the interrupt enable flag.
(2) Test function
• Test request flag (IRQxxx) generation can be checked by software.
• Release the standby mode. The test source to be released can be selected by the test enable flag.
38
Note
Falling edge
detector
Rising edge
detector
Edge
detector
IRQT1
IRQT2
IRQW
INTT1
INTT2
INTW
IM2
IRQ2
IRQT0
INTT0
Selector
IRQCSI
INTCSI
IRQ1
IRQ0
IRQ4
Edge
detector
IRQBT
INTBT
Both edge
detector
IM0
4
Interrupt enable flag (IExxx)
Note Noise elimination circuit (Standby release is disabled when noise elimination circuit is selected.)
KR3/P63
KR0/P60
Selector
IM1
IM2
INT2/P12
INT1/P11
INT0/P10
INT4/P00
1
2
Internal bus
Figure 7-1. Interrupt Control Circuit Block Diagram
VRQn
IST1
IST0
Priority control
circuit
Decoder
IME IPS
Standby release
signal
Vector table
address
generator
µ PD753104, 753106, 753108
39
µPD753104, 753106, 753108
8. STANDBY FUNCTION
In order to reduce power dissipation while a program is in a standby mode, two types of standby modes (STOP
mode and HALT mode) are provided for the µ PD753108.
Table 8-1. Operation Status in Standby Mode
Mode
Item
STOP mode
HALT mode
Set instruction
STOP instruction
HALT instruction
System clock when set
Settable only when the main system
clock is used.
Settable both by the main system clock
and subsystem clock.
Operation
status
Clock generator
Main system clock stops oscillation.
Only the CPU clock Φ halts (oscillation
continues).
Basic interval timer/
watchdog timer
Operation stops.
Operable only when the main system
clock is oscillated.
BT mode : IRQBT is set in the
reference time interval
WT mode : Reset signal is generated
by BT overflow
Serial interface
Operable only when an external SCK
input is selected as the serial clock.
Operable only when an external SCK input
is selected as the serial clock or when the
main system clock is oscillated.
Timer/event counter
Operable only when a signal input to the
TI0 to TI2 pins is specified as the count
clock.
Operable only when a signal input to the
TI0 to TI2 pins is specified as the count
clock or when the main system clock is
oscillated.
Watch timer
Operable when f XT is selected as the
count clock.
Operable.
LCD controller/driver
Operable only when fXT is selected as the Operable.
LCDCL.
External interrupt
The INT1, 2, and 4 are operable.
Only the INT0 is not operated Note.
CPU
The operation stops.
Release signal
Note
Can operate only when the noise elimination circuit is not used (IM02 = 1) by bit 2 of the edge detection
mode register (IM0).
40
Interrupt request signal sent from the operable hardware enabled by the interrupt
enable flag or RESET signal input.
µ PD753104, 753106, 753108
9. RESET FUNCTION
There are two reset inputs: external reset signal (RESET) and reset signal sent from the basic interval timer/
watchdog timer. When either one of the reset signals are input, an internal reset signal is generated. Figure 91 shows the configuration of the above two inputs.
Figure 9-1. Configuration of Reset Function
RESET
Internal reset signal
Reset signal sent from the
basic interval timer/watchdog timer
WDTM
Internal bus
Generation of the RESET signal initializes each hardware as listed in Table 9-1. Figure 9-2 shows the timing
chart of the reset operation.
Figure 9-2. Reset Operation by RESET Signal Generation
Wait Note
RESET
signal
generated
Operation mode or
standby mode
HALT mode
Operation mode
Internal reset operation
Note
The following two times can be selected by the mask option.
217/fX (21.8 ms: @ 6.00-MHz operation, 31.3 ms: @ 4.19-MHz operation)
215/fX (5.46 ms: @ 6.00-MHz operation, 7.81 ms: @ 4.19-MHz operation)
41
µPD753104, 753106, 753108
Table 9-1. Status of Each Hardware After Reset (1/2)
RESET signal generation
in the standby mode
RESET signal generation
in operation
Sets the low-order 4 bits of
program memory’s address
0000H to the PC11-PC8 and the
contents of address 0001H to
the PC7-PC0.
Sets the low-order 4 bits of
program memory’s address
0000H to the PC11-PC8 and the
contents of address 0001H to
the PC7-PC0.
µ PD753106, Sets the low-order 5 bits of
µ PD753108 program memory's address
0000H to the PC12-PC8 and the
contents of address 0001H to
the PC7-PC0.
Sets the low-order 5 bits of
program memory's address
0000H to the PC12-PC8 and the
contents of address 0001H to
the PC7-PC0.
Hardware
Program counter (PC)
PSW
µ PD753104
Carry flag (CY)
Held
Undefined
Skip flag (SK0 to SK2)
0
0
Interrupt status flag (IST0, IST1)
0
0
Sets the bit 6 of program
memory’s address 0000H to the
RBE and bit 7 to the MBE.
Sets the bit 6 of program
memory’s address 0000H to the
RBE and bit 7 to the MBE.
Undefined
Undefined
1000B
1000B
Data memory (RAM)
Held
Undefined
General-purpose register (X, A, H, L, D, E, B, C)
Held
Undefined
Bank select register (MBS, RBS)
0, 0
0, 0
Undefined
Undefined
Bank enable flag (MBE, RBE)
Stack pointer (SP)
Stack bank select register (SBS)
Basic interval
Counter (BT)
timer/watchdog
Mode register (BTM)
0
0
timer
Watchdog timer enable flag (WDTM)
0
0
Timer/event
Counter (T0)
0
0
counter (T0)
Modulo register (TMOD0)
FFH
FFH
0
0
0, 0
0, 0
0
0
FFH
FFH
0
0
0, 0
0, 0
0
0
Mode register (TM0)
TOE0, TOUT F/F
Timer/event
Counter (T1)
counter (T1)
Modulo register (TMOD1)
Mode register (TM1)
TOE1, TOUT F/F
Timer/event
Counter (T2)
counter (T2)
Modulo register (TMOD2)
FFH
FFH
High-level period setting modulo
register (TMOD2H)
FFH
FFH
0
0
0, 0
0, 0
0, 0, 0
0, 0, 0
TGCE
0
0
Mode register (WM)
0
0
Mode register (TM2)
TOE2, TOUT F/F
REMC, NRZ, NRZB
Watch timer
42
µ PD753104, 753106, 753108
Table 9-1. Status of Each Hardware After Reset (2/2)
Serial interface
Hardware
RESET signal generation
in the standby mode
RESET signal generation
in operation
Shift register (SIO)
Held
Undefined
Operation mode register (CSIM)
0
0
SBI control register (SBIC)
0
0
Held
Undefined
Slave address register (SVA)
Clock generator,
Processor clock control register (PCC)
0
0
clock output
System clock control register (SCC)
0
0
circuit
Clock output mode register (CLOM)
0
0
Sub-oscillator control register (SOS)
0
0
LCD controller/
Display mode register (LCDM)
0
0
driver
Display control register (LCDC)
0
0
LCD/port selection register (LPS)
0
0
Reset (0)
Reset (0)
Interrupt
Interrupt request flag (IRQxxx)
function
Interrupt enable flag (IExxx)
0
0
Interrupt priority selection register (IPS)
0
0
INT0, 1, 2 mode registers (IM0, IM1, IM2)
0, 0, 0
0, 0, 0
Output buffer
Off
Off
Output latch
Cleared (0)
Cleared (0)
I/O mode registers (PMGA, B, C)
0
0
Pull-up resistor setting register (POGA, B)
0
0
Held
Undefined
Digital port
Bit sequential buffer (BSB0 to BSB3)
43
µPD753104, 753106, 753108
10. MASK OPTION
The µ PD753108 has the following mask options.
P50-P53 mask options
Selects whether or not to internally connect a pull-up resistor.
<1> Connect pull-up resistor internally bit-wise.
<2> Do not connect pull-up resistor internally.
VLC0-VLC2 pins, BIAS pin mask option
Selects whether or not to internally connect LCD-driving split resistors.
<1> Do not connect split resistor internally.
<2> Connect four 10-kΩ (typ.) split resistors simultaneously internally.
<3> Connect four 100-kΩ (typ.) split resistors simultaneously internally.
Standby function mask option
Selects the wait time with the RESET signal.
<1> 217/fx (21.8 ms: When fx = 6.0 MHz, 31.3 ms: When fx = 4.19 MHz)
<2> 215/fx (5.46 ms: When fx = 6.0 MHz, 7.81 ms: When fx = 4.19 MHz)
Subsystem clock mask option
Selects whether or not to use an internal feedback resistor.
<1> Use internal feedback resistor.
(Switch internal feedback resistor ON/OFF by software)
<2> Do not use internal feedback resistor.
(Disconnect internal feedback resistor by hardware)
44
µ PD753104, 753106, 753108
11. INSTRUCTION SET
(1) Expression formats and description methods of operands
The operand is described in the operand column of each instruction in accordance with the description
method for the operand expression format of the instruction. For details, refer to “RA75X ASSEMBLER
PACKAGE USERS’ MANUAL——LANGUAGE (EEU-1363)”. If there are several elements, one of them
is selected. Capital letters and the + and – symbols are key words and are described as they are.
For immediate data, appropriate numbers and labels are described.
Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the register flags can be described.
However, there are restrictions in the labels that can be described for fmem and pmem. For details, see
User’s Manual.
Expression
format
Description method
reg
reg1
X, A, B, C, D, E, H, L
X, B, C, D, E, H, L
rp
rp1
rp2
rp'
rp'1
XA,
BC,
BC,
XA,
BC,
rpa
rpa1
HL, HL+, HL–, DE, DL
DE, DL
n4
n8
4-bit immediate data or label
8-bit immediate data or label
mem
bit
8-bit immediate data or label
2-bit immediate data or label
fmem
pmem
FB0H-FBFH, FF0H-FFFH immediate data or label
FC0H-FFFH immediate data or label
addr
caddr
faddr
0000H-0FFFH immediate data
0000H-17FFH immediate data
0000H-1FFFH immediate data
0000H-0FFFH immediate data
0000H-17FFH immediate data
0000H-1FFFH immediate data
12-bit immediate data or label
11-bit immediate data or label
taddr
20H-7FH immediate data (where bit0 = 0) or label
PORTn
IExxx
RBn
MBn
PORT0-PORT3, PORT5, PORT6, PORT8, PORT9
IEBT, IET0-IET2, IE0-IE2, IE4, IECSI, IEW
RB0-RB3
MB0, MB1, MB15
addr1
(Mk II mode only)
BC,
DE,
DE
BC,
DE,
DE, HL
HL
DE, HL, XA', BC', DE', HL'
HL, XA', BC', DE', HL'
Note
or
or
or
or
or
or
label
label
label
label
label
label
(µ PD753104)
(µ PD753106)
(µ PD753108)
(µ PD753104)
(µ PD753106)
(µ PD753108)
Note mem can be only used for even address in 8-bit data processing.
45
µPD753104, 753106, 753108
(2) Legend in explanation of operation
46
A
: A register, 4-bit accumulator
B
: B register
C
: C register
D
: D register
E
: E register
H
: H register
L
: L register
X
: X register
XA
: XA register pair; 8-bit accumulator
BC
: BC register pair
DE
: DE register pair
HL
: HL register pair
XA’
: XA’ expanded register pair
BC’
: BC’ expanded register pair
DE’
: DE’ expanded register pair
HL’
: HL’ expanded register pair
PC
: Program counter
SP
: Stack pointer
CY
: Carry flag, bit accumulator
PSW
: Program status word
MBE
: Memory bank enable flag
RBE
: Register bank enable flag
PORTn
: Port n (n = 0 to 3, 5, 6, 8, 9)
IME
: Interrupt master enable flag
IPS
: Interrupt priority selection register
IExxx
: Interrupt enable flag
RBS
: Register bank selection register
MBS
: Memory bank selection register
PCC
: Processor clock control register
.
: Separation between address and bit
(xx)
: The contents addressed by xx
xxH
: Hexadecimal data
µ PD753104, 753106, 753108
(3) Explanation of symbols under addressing area column
*1
MB = MBE·MBS
(MBS = 0, 1, 15)
*2
MB = 0
*3
MBE = 0 : MB = 0 (000H to 07FH)
MB = 15 (F80H to FFFH)
MBE = 1 : MB = MBS (MBS = 0, 1, 15)
*4
MB = 15, fmem = FB0H to FBFH, FF0H to FFFH
*5
MB = 15, pmem = FC0H to FFFH
*6
µPD753104
addr = 000H to FFFH
µPD753106
addr = 0000H to 17FFH
µPD753108
addr = 0000H to 1FFFH
*7
addr
Data memory addressing
= (Current PC) – 15 to (Current PC) – 1
(Current PC) + 2 to (Current PC) + 16
addr1 = (Current PC) – 15 to (Current PC) – 1
(Current PC) + 2 to (Current PC) + 16
*8
µPD753104
caddr = 000H to FFFH
µPD753106
caddr = 0000H to 0FFFH (PC12 = 0) or
1000H to 17FFH (PC12 = 1)
µPD753108
caddr = 0000H to 0FFFH (PC12 = 0) or
1000H to 1FFFH (PC12 = 1)
*9
faddr = 0000H to 07FFH
*10
taddr = 0020H to 007FH
*11
µPD753104
addr1 = 000H to FFFH
µPD753106
addr1 = 0000H to 17FFH
µPD753108
addr1 = 0000H to 1FFFH
Remarks 1.
Program memory addressing
MB indicates memory bank that can be accessed.
2.
In *2, MB = 0 independently of how MBE and MBS are set.
3.
In *4 and *5, MB = 15 independently of how MBE and MBS are set.
4.
*6 to *11 indicate the areas that can be addressed.
47
µPD753104, 753106, 753108
(4) Explanation of number of machine cycles column
S denotes the number of machine cycles required by skip operation when a skip instruction is executed.
The value of S varies as follows.
• When no skip is made: S = 0
• When the skipped instruction is a 1- or 2-byte instruction: S = 1
• When the skipped instruction is a 3-byte instruction Note: S = 2
Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction
Caution The GETI instruction is skipped in one machine cycle.
One machine cycle is equal to one cycle of CPU clock (= t CY); time can be selected from among four types
by setting PCC.
48
µ PD753104, 753106, 753108
Instruction
group
Transfer
Mnemonic
MOV
XCH
Number
of bytes
Number
of machine
cycles
A, #n4
1
1
A <- n4
reg1, #n4
2
2
reg1 <- n4
XA, #n8
2
2
XA <- n8
String effect A
HL, #n8
2
2
HL <- n8
String effect B
rp2, #n8
2
2
rp2 <- n8
A, @HL
1
1
A <- (HL)
*1
A, @HL+
1
2+S
A <- (HL), then L <- L+1
*1
L=0
A, @HL–
1
2+S
A <- (HL), then L <- L–1
*1
L = FH
A, @rpa1
1
1
A <- (rpa1)
*2
XA, @HL
2
2
XA <- (HL)
*1
@HL, A
1
1
(HL) <- A
*1
@HL, XA
2
2
(HL) <- XA
*1
A, mem
2
2
A <- (mem)
*3
XA, mem
2
2
XA <- (mem)
*3
mem, A
2
2
(mem) <- A
*3
mem, XA
2
2
(mem) <- XA
*3
A, reg
2
2
A <- reg
XA, rp'
2
2
XA <- rp'
reg1, A
2
2
reg1 <- A
rp'1, XA
2
2
rp'1 <- XA
A, @HL
1
1
A <-> (HL)
*1
A, @HL+
1
2+S
A <-> (HL), then L <- L+1
*1
L=0
A, @HL–
1
2+S
A <-> (HL), then L <- L–1
*1
L = FH
A, @rpa1
1
1
A <-> (rpa1)
*2
XA, @HL
2
2
XA <-> (HL)
*1
A, mem
2
2
A <-> (mem)
*3
XA, mem
2
2
XA <-> (mem)
*3
A, reg1
1
1
A <-> reg1
XA, rp'
2
2
XA <-> rp'
Operand
Operation
Addressing
area
Skip condition
String effect A
49
µ PD753104, 753106, 753108
Instruction
group
Table
reference
Mnemonic
MOVT
Operand
Number
of bytes
Number
of machine
cycles
1
3
XA, @PCDE
Operation
Addressing
area
Skip condition
µPD753104
XA <- (PC 11–8+DE) ROM
µPD753106, 753108
XA <- (PC 12–8+DE) ROM
XA, @PCXA
1
3
µPD753104
XA <- (PC 11–8+XA) ROM
µPD753106, 753108
XA <- (PC 12–8+XA) ROM
Bit transfer
Operation
MOV1
ADDS
ADDC
SUBS
SUBC
Note
XA, @BCDE
1
3
XA <- (BCDE) ROM
Note
*6
XA, @BCXA
1
3
XA <- (BCXA)ROM
Note
*6
CY, fmem.bit
2
2
CY <- (fmem.bit)
*4
CY, pmem.@L
2
2
CY <- (pmem 7–2+L3–2.bit(L1–0 ))
*5
CY, @H+mem.bit
2
2
CY <- (H+mem3–0 .bit)
*1
fmem.bit, CY
2
2
(fmem.bit) <- CY
*4
pmem.@L, CY
2
2
(pmem 7–2+L3–2.bit(L 1–0)) <- CY
*5
@H+mem.bit, CY
2
2
(H+mem3–0 .bit) <- CY
*1
A, #n4
1
1+S
A <- A+n4
carry
XA, #n8
2
2+S
XA <- XA+n8
carry
A, @HL
1
1+S
A <- A+(HL)
XA, rp'
2
2+S
XA <- XA+rp'
carry
rp'1, XA
2
2+S
rp'1 <- rp'1+XA
carry
A, @HL
1
1
A, CY <- A+(HL)+CY
XA, rp'
2
2
XA, CY <- XA+rp'+CY
rp'1, XA
2
2
rp'1, CY <- rp'1+XA+CY
A, @HL
1
1+S
A <- A–(HL)
XA, rp'
2
2+S
XA <- XA–rp'
borrow
rp'1, XA
2
2+S
rp'1 <- rp'1–XA
borrow
A, @HL
1
1
A, CY <- A–(HL)–CY
XA, rp'
2
2
XA, CY <- XA–rp'–CY
rp'1, XA
2
2
rp'1, CY <- rp'1–XA–CY
carry
*1
*1
borrow
*1
Set “0” in B register if the µ PD753104 is used. Only low-order one bit of B register will be valid if the
µ PD753106 or 753108 is used.
50
*1
µ PD753104, 753106, 753108
Instruction
group
Operation
Number
of bytes
Number
of machine
cycles
A, #n4
2
2
A <- A ∧ n4
A, @HL
1
1
A <- A ∧ (HL)
XA, rp'
2
2
XA <- XA ∧ rp'
rp'1, XA
2
2
rp'1 <- rp'1 ∧ XA
A, #n4
2
2
A <- A ∨ n4
A, @HL
1
1
A <- A ∨ (HL)
XA, rp'
2
2
XA <- XA ∨ rp'
rp'1, XA
2
2
rp'1 <- rp'1 ∨ XA
A, #n4
2
2
A <- A v n4
A, @HL
1
1
A <- A v (HL)
XA, rp'
2
2
XA <- XA v rp'
rp'1, XA
2
2
rp'1 <- rp'1 v XA
RORC
A
1
1
CY <- A0 , A3 <- CY, An–1 <- An
NOT
A
2
2
A <- A
INCS
reg
1
1+S
reg <- reg+1
reg = 0
rp1
1
1+S
rp1 <- rp1+1
rp1 = 00H
@HL
2
2+S
(HL) <- (HL)+1
*1
(HL) = 0
mem
2
2+S
(mem) <- (mem)+1
*3
(mem) = 0
reg
1
1+S
reg <- reg–1
reg = FH
rp'
2
2+S
rp' <- rp'–1
rp' = FFH
reg, #n4
2
2+S
Skip if reg = n4
reg = n4
@HL, #n4
2
2+S
Skip if (HL) = n4
*1
(HL) = n4
A, @HL
1
1+S
Skip if A = (HL)
*1
A = (HL)
XA, @HL
2
2+S
Skip if XA = (HL)
*1
XA = (HL)
A, reg
2
2+S
Skip if A = reg
A = reg
XA, rp'
2
2+S
Skip if XA = rp'
XA = rp'
SET1
CY
1
1
CY <- 1
CLR1
CY
1
1
CY <- 0
SKT
CY
1
1+S
NOT1
CY
1
1
Mnemonic
AND
OR
XOR
Accumulator
manipulation
Increment
and
decrement
DECS
Comparison
Carry flag
manipulation
SKE
Operand
Operation
Skip if CY = 1
Addressing
area
Skip condition
*1
*1
*1
CY = 1
CY <- CY
51
µ PD753104, 753106, 753108
Instruction
group
Memory bit
manipulation
Mnemonic
SET1
CLR1
SKT
SKF
SKTCLR
AND1
OR1
XOR1
52
Number
of bytes
Number
of machine
cycles
mem.bit
2
2
(mem.bit) <- 1
*3
fmem.bit
2
2
(fmem.bit) <- 1
*4
pmem.@L
2
2
(pmem 7–2+L3–2 .bit(L1–0)) <- 1
*5
@H+mem.bit
2
2
(H+mem3–0 .bit) <- 1
*1
mem.bit
2
2
(mem.bit) <- 0
*3
fmem.bit
2
2
(fmem.bit) <- 0
*4
pmem.@L
2
2
(pmem 7–2+L3–2 .bit(L1–0)) <- 0
*5
@H+mem.bit
2
2
(H+mem3–0 .bit) <- 0
*1
mem.bit
2
2+S
Skip if (mem.bit) = 1
*3
(mem.bit) = 1
fmem.bit
2
2+S
Skip if (fmem.bit) = 1
*4
(fmem.bit) = 1
pmem.@L
2
2+S
Skip if (pmem 7–2+L3–2.bit(L 1–0)) = 1
*5
(pmem.@L) = 1
@H+mem.bit
2
2+S
Skip if (H+mem3–0 .bit) = 1
*1
(@H+mem.bit) = 1
mem.bit
2
2+S
Skip if (mem.bit) = 0
*3
(mem.bit) = 0
fmem.bit
2
2+S
Skip if (fmem.bit) = 0
*4
(fmem.bit) = 0
pmem.@L
2
2+S
Skip if (pmem 7–2+L3–2.bit(L 1–0)) = 0
*5
(pmem.@L) = 0
@H+mem.bit
2
2+S
Skip if (H+mem3–0 .bit) = 0
*1
(@H+mem.bit) = 0
fmem.bit
2
2+S
Skip if (fmem.bit) = 1 and clear
*4
(fmem.bit) = 1
pmem.@L
2
2+S
Skip if (pmem 7–2+L3–2.bit(L 1–0)) = 1 and clear
*5
(pmem.@L) = 1
@H+mem.bit
2
2+S
Skip if (H+mem3–0 .bit) = 1 and clear
*1
(@H+mem.bit) = 1
CY, fmem.bit
2
2
CY <- CY ∧ (fmem.bit)
*4
CY, pmem.@L
2
2
CY <- CY ∧ (pmem7–2 +L3–2.bit(L1–0 ))
*5
CY, @H+mem.bit
2
2
CY <- CY ∧ (H+mem3–0.bit)
*1
CY, fmem.bit
2
2
CY <- CY ∨ (fmem.bit)
*4
CY, pmem.@L
2
2
CY <- CY ∨ (pmem7–2 +L3–2.bit(L1–0 ))
*5
CY, @H+mem.bit
2
2
CY <- CY ∨ (H+mem3–0.bit)
*1
CY, fmem.bit
2
2
CY <- CY v (fmem.bit)
*4
CY, pmem.@L
2
2
CY <- CY v (pmem7–2+L3–2 .bit(L1–0))
*5
CY, @H+mem.bit
2
2
CY <- CY v (H+mem3–0.bit)
*1
Operand
Operation
Addressing
area
Skip condition
µ PD753104, 753106, 753108
Instruction
group
Branch
Mnemonic
BR Note
Operand
addr
Number
of bytes
Number
of machine
cycles
–
–
Operation
µPD753104
PC11–0 <- addr
Select appropriate instruction from among
BR !addr, BRCB !caddr and BR $addr
according to the assembler being used.
Addressing
area
Skip condition
*6
µPD753106, 753108
PC12–0 <- addr
Select appropriate instruction from
among BR !addr, BRCB !caddr and BR
$addr according to the assembler
being used.
addr1
–
–
µPD753104
PC11-0 <- addr1
Select appropriate instruction from
among BR !addr, BRA !addr1,
BRCB !caddr and BR $addr1 according
to the assembler being used.
*11
µPD753106, 753108
PC12–0 <- addr1
Select appropriate instruction from
among BR !addr, BRA !addr1, BRCB
!caddr and BR $addr1 according to the
assembler being used.
!addr
3
3
µPD753104
PC11–0 <- addr
*6
µPD753106, 753108
PC12–0 <- addr
$addr
1
2
µPD753104
PC11–0 <- addr
*7
µPD753106, 753108
PC12–0 <- addr
$addr1
1
2
µPD753104
PC11–0 <- addr1
µPD753106, 753108
PC12–0 <- addr1
Note
The above operations in the double boxes can be performed only in the Mk II mode. The other operations
can be performed only in the Mk I mode.
53
µ PD753104, 753106, 753108
Instruction
group
Branch
Mnemonic
BR
Operand
Number
of bytes
Number
of machine
cycles
2
3
PCDE
Operation
Addressing
area
Skip condition
µPD753104
PC 11–0 <- PC11-8+DE
µ PD753106, 753108
PC 12–0 <- PC12-8+DE
PCXA
2
3
µPD753104
PC 11–0 <- PC11-8+XA
µ PD753106, 753108
PC 12–0 <- PC12-8+XA
BCDE
2
3
µPD753104
PC 11–0 <- BCDE Note 1
*6
µ PD753106, 753108
PC 12–0 <- BCDE Note 2
BCXA
2
3
µPD753104
PC 11–0 <- BCXA Note 1
*6
µ PD753106, 753108
PC 12–0 <- BCXA Note 2
BRA
Note 3
!addr1
3
3
µPD753104
PC 11–0 <- addr1
*11
µ PD753106, 753108
PC 12–0 <- addr1
BRCB
!caddr
2
2
µPD753104
PC 11–0 <- caddr11–0
*8
µ PD753106, 753108
PC 12–0 <- PC12+caddr11–0
Subroutine
stack control
CALLA
Note 3
!addr1
3
3
µPD753104
(SP–2) <- x, x, MBE, RBE
(SP–6) (SP–3) (SP–4) <- PC 11–0
(SP–5) <- 0, 0, 0, 0
PC 11–0 <- addr1, SP <- SP–6
*11
µ PD753106, 753108
(SP–2) <- x, x, MBE, RBE
(SP–6) (SP–3) (SP–4) <- PC 11–0
(SP–5) <- 0, 0, 0, PC 12
PC 12–0 <- addr1, SP <- SP–6
Notes 1.
“0” must be set to B register.
2.
Only low-order one bit is valid in B register.
3.
The above operations in the double boxes can be performed only in the Mk II mode. The other
operations can be performed only in the Mk I mode.
54
µ PD753104, 753106, 753108
Instruction
group
Subroutine
stack control
Mnemonic
CALL Note
Operand
!addr
Number
of bytes
Number
of machine
cycles
3
3
Operation
µPD753104
(SP–3) <- MBE, RBE, 0, 0
(SP–4) (SP–1) (SP–2) <- PC11–0
PC11–0 <- addr, SP <- SP–4
Addressing
area
Skip condition
*6
µPD753106, 753108
(SP–3) <- MBE, RBE, 0, PC12
(SP–4) (SP–1) (SP–2) <- PC11–0
PC12–0 <- addr, SP <- SP–4
4
µPD753104
(SP–2) <- x, x, MBE, RBE
(SP–6) (SP–3) (SP–4) <- PC11–0
(SP–5) <- 0, 0, 0, 0
PC11–0 <- addr, SP <- SP–6
µPD753106, 753108
(SP–2) <- x, x, MBE, RBE
(SP–6) (SP–3) (SP–4) <- PC11–0
(SP–5) <- 0, 0, 0, PC12
PC12–0 <- addr, SP <- SP–6
CALLF Note
!faddr
2
2
µPD753104
(SP–3) <- MBE, RBE, 0, 0
(SP–4) (SP–1) (SP–2) <- PC11–0
PC11–0 <- 0+faddr, SP <- SP–4
*9
µPD753106, 753108
(SP–3) <- MBE, RBE, 0, PC12
(SP–4) (SP–1) (SP–2) <- PC11–0
PC12–0 <- 00+faddr, SP <- SP–4
3
µPD753104
(SP–2) <- x, x, MBE, RBE
(SP–6) (SP–3) (SP–4) <- PC11–0
(SP–5) <- 0, 0, 0, 0
PC11–0 <- 0+faddr, SP <- SP–6
µPD753106, 753108
(SP–2) <- x, x, MBE, RBE
(SP–6) (SP–3) (SP–4) <- PC11–0
(SP–5) <- 0, 0, 0, PC12
PC12–0 <- 00+faddr, SP <- SP–6
Note
The above operations in the double boxes can be performed only in the Mk II mode. The other operations
can be performed only in the Mk I mode.
55
µ PD753104, 753106, 753108
Instruction
group
Subroutine
stack control
Mnemonic
RET Note
Operand
Number
of bytes
Number
of machine
cycles
1
3
Operation
Addressing
area
Skip condition
µPD753104
PC 11–0 <- (SP) (SP+3) (SP+2)
MBE, RBE, 0, 0 <- (SP+1), SP <- SP+4
µPD753106, 753108
PC 11–0 <- (SP) (SP+3) (SP+2)
MBE, RBE, 0, PC12 <- (SP+1), SP <- SP+4
µPD753104
x, x, MBE, RBE <- (SP+4)
0, 0, 0, 0, <- (SP+1)
PC 11–0 <- (SP) (SP+3) (SP+2), SP <- SP+6
µPD753106, 753108
x, x, MBE, RBE <- (SP+4)
MBE, 0, 0, PC12 <- (SP+1)
PC 11–0 <- (SP) (SP+3) (SP+2), SP <- SP+6
RETS Note
1
3+S
µPD753104
MBE, RBE, 0, 0 <- (SP+1)
PC 11–0 <- (SP) (SP+3) (SP+2)
SP <- SP+4
then skip unconditionally
Unconditional
µPD753106, 753108
MBE, RBE, 0, PC12 <- (SP+1)
PC 11–0 <- (SP) (SP+3) (SP+2)
SP <- SP+4
then skip unconditionally
µPD753104
0, 0, 0, 0 <- (SP+1)
PC 11–0 <- (SP) (SP+3) (SP+2)
x, x, MBE, RBE <- (SP+4)
SP <- SP+6
then skip unconditionally
µPD753106, 753108
0, 0, 0, PC 12 <- (SP+1)
PC 11–0 <- (SP) (SP+3) (SP+2)
x, x, MBE, RBE <- (SP+4)
SP <- SP+4
then skip unconditionally
Note
The above operations in the double boxes can be performed only in the Mk II mode. The other operations
can be performed only in the Mk I mode.
56
µ PD753104, 753106, 753108
Instruction
group
Subroutine
stack control
Mnemonic
Operand
RETI Note 1
Number
of bytes
Number
of machine
cycles
1
3
Addressing
area
Operation
Skip condition
µPD753104
MBE, RBE, 0, 0 <- (SP+1)
PC11–0 <- (SP) (SP+3) (SP+2)
PSW <- (SP+4) (SP+5), SP <- SP+6
µPD753106, 753108
MBE, RBE, 0, PC12 <- (SP+1)
PC11–0 <- (SP) (SP+3) (SP+2)
PSW <- (SP+4) (SP+5), SP <- SP+6
µPD753104
0, 0, 0, 0 <- (SP+1)
PC 11–0 <- (SP) (SP+3) (SP+2)
PSW <- (SP+4) (SP+5), SP <- SP+6
µPD753106, 753108
0, 0, 0, PC12 <- (SP+1)
PC 11–0 <- (SP) (SP+3) (SP+2)
PSW <- (SP+4) (SP+5), SP <- SP+6
PUSH
rp
1
1
(SP–1) (SP–2) <- rp, SP <- SP–2
BS
2
2
(SP–1) <- MBS, (SP–2) <- RBS, SP <- SP–2
rp
1
1
rp <- (SP+1) (SP), SP <- SP+2
BS
2
2
MBS <- (SP+1), RBS <- (SP), SP <- SP+2
2
2
IME (IPS.3) <- 1
2
2
IExxx <- 1
2
2
IME (IPS.3) <- 0
IExxx
2
2
IExxx <- 0
A, PORTn
2
2
A <- PORTn
XA, PORTn
2
2
XA <- PORTn+1, PORTn
PORTn, A
2
2
PORTn <- A
PORTn, XA
2
2
PORTn+1, PORTn <- XA
HALT
2
2
Set HALT Mode (PCC.2 <- 1)
STOP
2
2
Set STOP Mode (PCC.3 <- 1)
NOP
1
1
No Operation
RBn
2
2
RBS <- n
(n = 0-3)
MBn
2
2
MBS <- n
(n = 0, 1, 15)
POP
Interrupt
control
EI
IExxx
DI
Input/output
IN Note 2
OUT Note 2
CPU control
Special
SEL
Notes 1.
(n = 0-3, 5, 6, 8, 9)
(n = 8)
(n = 3, 5, 6, 8, 9)
(n = 8)
The above operations in the double boxes can be performed only in the Mk II mode. The other
operations can be performed only in the Mk I mode.
2.
While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1, and
MBS must be set to 15.
57
µ PD753104, 753106, 753108
Instruction
group
Special
Mnemonic
GETI Note 1, 2
Operand
taddr
Number
of bytes
Number
of machine
cycles
1
3
Operation
µPD753104
• When TBR instruction
PC11–0 <- (taddr) 3–0 + (taddr+1)
Addressing
area
Skip condition
*10
––––––––––––––––––––––––––––––––––
–––––––––––––
• When TCALL instruction
(SP–4) (SP–1) (SP–2) <- PC11–0
(SP–3) <- MBE, RBE, 0, 0
PC11–0 <- (taddr) 3–0 + (taddr+1)
SP <- SP–4
––––––––––––––––––––––––––––––––––
–––––––––––––
• When instruction other than TBR and
TCALL instructions
(taddr) (taddr+1) instruction is executed.
Depending on
the reference
instruction
µPD753106, 753108
• When TBR instruction
PC12–0 <- (taddr) 4–0 + (taddr+1)
––––––––––––––––––––––––––––––––––
–––––––––––––
• When TCALL instruction
(SP–4) (SP–1) (SP–2) <- PC11–0
(SP–3) <- MBE, RBE, 0, PC12
PC12–0 <- (taddr) 4–0 + (taddr+1)
SP <- SP–4
––––––––––––––––––––––––––––––––––
–––––––––––––
• When instruction other than TBR and
TCALL instructions
(taddr) (taddr+1) instruction is executed.
3
µPD753104
• When TBR instruction
PC11–0 <- (taddr) 3–0 + (taddr+1)
––––––––––––––––––––––––––––––––––––– ––––
4
3
• When instruction other than TBR and
TCALL instructions
(taddr) (taddr+1) instruction is executed.
3
µPD753106, 753108
• When TBR instruction
PC12–0 <- (taddr) 4–0 + (taddr+1)
––––––––––––––––––––––––––––––––––––– ––––
Notes 1.
–––––––––––––
–––––––––––––
Depending on
the reference
instruction
–––––––––––––
• When TCALL instruction
(SP–6) (SP–3) (SP–4) <- PC11–0
(SP–5) <- 0, 0, 0, PC12
(SP–2) <- x, x, MBE, RBE
PC12–0 <- (taddr) 4–0 + (taddr+1)
SP <- SP–6
––––––––––––––––––––––––––––––––––––– ––––
3
*10
• When TCALL instruction
(SP–6) (SP–3) (SP–4) <- PC11–0
(SP–5) <- 0, 0, 0, 0
(SP–2) <- x, x, MBE, RBE
PC11–0 <- (taddr) 3–0 + (taddr+1)
SP <- SP–6
––––––––––––––––––––––––––––––––––––– ––––
4
Depending on
the reference
instruction
• When instruction other than TBR and
TCALL instructions
(taddr) (taddr+1) instruction is executed.
–––––––––––––
Depending on
the reference
instruction
The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI
instruction.
2.
The above operations in the double boxes can be performed only in the Mk II mode. The other
operations can be performed only in the Mk I mode.
58
µ PD753104, 753106, 753108
12. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (T A = 25 ˚C)
Parameter
Symbol
Test Conditions
Rating
Unit
–0.3 to +7.0
V
Supply voltage
VDD
Input voltage
VI1
Except port 5
–0.3 to VDD + 0.3
V
VI2
Port 5
On-chip pull-up resistor
–0.3 to VDD + 0.3
V
When N-ch open-drain
–0.3 to +14
V
–0.3 to VDD + 0.3
V
Per pin
–10
mA
Total of all pins
–30
mA
30
mA
Output voltage
VO
Output current high
I OH
Output current low
I OL
Per pin
Total of all pins
Operating ambient
temperature
TA
Storage temperature
Tstg
Note
220
–40 to +85
mA
Note
˚C
–65 to +150
˚C
When LCD is driven in normal mode: T A = –10 to +85 ˚C
Caution Exposure to Absolute Maximum Ratings even for instant may affect device reliability; exceeding
the ratings could cause parmanent damage. The parameters apply independently. The device
should be operated within the limits specified under DC and AC Characteristics.
CAPACITANCE (T A = 25 ˚C, VDD = 0 V)
Parameter
Symbol
Input capacitance
CIN
Output capacitance
COUT
I/O capacitance
CIO
Test Conditions
f = 1 MHz
Unmeasured pins returned to 0 V.
MIN.
TYP.
MAX.
Unit
15
pF
15
pF
15
pF
59
µ PD753104, 753106, 753108
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)
Resonator
Recommended constant
Ceramic
resonator
frequency (fx)
C1
C2
VDD
Crystal
resonator
C2
VDD
stabilization time Note 3
lation voltage range MIN.
X2
VDD = 4.5 to 5.5 V
Note 2
6.0
Note 2
10
MHz
ms
MHz
ms
30
1.0
6.0
Note 2
MHz
Note 1
X1 input
high/low-level width
(t XH, t XL )
Notes 1.
6.0
Unit
Note 1
Oscillation
frequency (fx)
MAX.
4
1.0
X1 input
X1
clock
After V DD reaches oscil-
stabilization time Note 3
External
TYP.
Note 1
Oscillation
frequency (fx)
C1
MIN.
1.0
Oscillation
X2
X1
Test conditions
Oscillation
X2
X1
Parameter
83.3
500
ns
The oscillation frequency and X1 input frequency indicate characteristics of the oscillator only. For
the instruction execution time, refer to the AC characteristics.
2.
When the oscillation frequency is 4.19 MHz < fx ≤ 6.0 MHz at 1.8 V ≤ V DD < 2.7 V, setting the processor
clock control register (PCC) to 0011 results in 1 machine cycle time being less than the required 0.95
µ s. Therefore, set PCC to a value other than 0011.
3.
The oscillation stabilization time is necessary for oscillation to stabilize after applying V DD or releasing
the STOP mode.
Caution When using the main system clock oscillator, wiring in the area enclosed with the dotted line in the
above figure should be carried out as follows to avoid an adverse effect from wiring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should be the same as VDD.
• Do not ground to the ground pattern in which a high current flows.
• Do not fetch a signal from the oscillator.
60
µ PD753104, 753106, 753108
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (T A = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)
Resonator
Recommended constant
Crystal
XT1
C3
R
frequency (f XT)
C4
Oscillation
External
TYP.
MAX.
Unit
32
32.768
35
kHz
1.0
2
s
Note 1
VDD = 4.5 to 5.5 V
XT1 input frequency
XT1
MIN.
stabilization time Note 2
VDD
10
32
100
kHz
5
15
µs
XT2
(f XT)
clock
Test conditions
Oscillation
XT2
resonator
Parameter
Note 1
X1 input high/low-level
width (t XTH, tXTL)
Notes 1.
2.
Caution
Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
The oscillation stabilization time is necessary for oscillation to stabilize after applying V DD.
When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line in the
above figure should be carried out as follows to avoid an adverse effect from wiring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should be the same as VDD.
• Do not ground to the ground pattern in which a high current flows.
• Do not fetch a signal from the oscillator.
The subsystem clock oscillator is designed as a low amplification circuit to provide low consumption
current, causing misoperation by noise more frequently than the main system clock oscillator.
Special care should therefore be taken for wiring method when the subsystem clock is used.
61
µ PD753104, 753106, 753108
RECOMMENDED OSCILLATOR CONSTANT
Ceramic Resonator (TA = –20 to +85 ˚C)
Manufacturer
Product name
Frequency
Oscillator
constant (pF)
(MHz)
C1
C2
Oscillation
voltage range (VDD)
MIN.
Kyocera
KBR-1000F/Y
1.0
100
100
1.8
Corporation
KBR-2.0MS
2.0
82
82
2.2
KBR-4.19MSA
4.19
33
33
1.8
KBR-4.19MKS
—
PBRC 4.19A
33
PBRC 4.19B
KBR-6.0MSA
On-chip capacitor
product
—
On-chip capacitor
product
33
33
PBRC 6.00B
—
—
—
—
PBRC 6.00A
5.5
33
33
KBR-6.0MKS
MAX.
—
—
6.0
Remarks
—
On-chip capacitor
product
33
—
—
—
On-chip capacitor
product
Ceramic Resonator (TA = –40 to +85 ˚C)
Manufacturer
Product name
Frequency
(MHz)
TDK
CCR1000K2
1.0
CCR2.0MC33
2.0
FCR4.19MC5
4.19
Oscillator
constant (pF)
C1
150
—
C2
150
Oscillation
voltage range (VDD)
MIN.
2.3
—
2.0
CCR6.0MC3
62
6.0
MAX.
5.5
—
On-chip capacitor
product
CCR4.19MC3
FCR6.0MC5
Remarks
2.2
µ PD753104, 753106, 753108
Ceramic Resonator (T A = –20 to +80 ˚C)
Manufacturer
Product name
Frequency
Oscillator
constant (pF)
(MHz)
C1
Oscillation
voltage range (VDD)
C2
MIN.
Murata Mfg.
CSB1000J
1.0
100
100
2.4
Co., Ltd.
CSA2.00MG
2.0
30
30
1.8
CST2.00MGW
CSA3.00MG
—
3.0
30
CST3.00MGW
CSA4.19MG
4.19
30
5.0
—
—
On-chip capacitor product
30
2.2
—
1.8
CST5.00MGW
—
—
2.2
CST5.00MGWU
On-chip capacitor product
1.8
6.0
30
30
2.5
CSA6.00MGU
—
1.8
CST6.00MGW
—
—
2.5
CST6.00MGWU
Note
Note
—
CSA5.00MGU
CSA6.00MG
Rd = 5.6 kΩ
On-chip capacitor product
30
30
5.5
—
—
—
MAX.
On-chip capacitor product
30
—
CST4.19MGW
CSA5.00MG
—
Remarks
On-chip capacitor product
1.8
If using the CSB1000J (1.0-MHz) ceramic resonator manufactured by Murata Mfg. Co., Ltd., a limiting
resistor (Rd = 5.6 kΩ) is required (see figure below). A limiting resistor is not required if using the other
recommended resonators.
Recommended Main System Clock Circuit Example (using Murata Mfg. Co., Ltd. CSB1000J)
X1
X2
CSB1000J
C1
Rd
C2
VDD
63
µ PD753104, 753106, 753108
Crystal Resonator
Manufacturer
Product name
Frequency
Oscillator
constant (pF)
(MHz)
Kinseki
HC-49/U
2.0
C1
15
C2
15
Oscillation
voltage range (V DD)
MIN.
Remarks
MAX.
1.8
5.5
6.0
2.5
5.5
4.19
1.8
5.5
6.0
2.5
5.5
T A = –20 to +70 °C
4.19
HC-49/U-S
T A = –10 to +70 °C
Caution The oscillator constant and the oscillation voltage range represent conditions for stable oscillation,
but do not guarantee an accurate oscillation frequency. For an application circuit requiring an
accurate oscillation frequency, it may be necessary to adjust the oscillation frequency of the
resonator in the application circuit, in which case inquiries should be directed to the manufacturer
of the resonator.
64
µ PD753104, 753106, 753108
DC CHARACTERISTICS (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)
Parameter
Output current low
Symbol
I OL
Test conditions
MIN.
TYP.
Per pin
Total of all pins
Input voltage high
VIH1
VIH2
VIH3
Input voltage low
X1, XT1
VIL1
Ports 2, 3, 5, 8, 9
VIL2
15
mA
150
mA
0.7VDD
VDD
V
1.8 ≤ V DD < 2.7 V
0.9VDD
VDD
V
2.7 ≤ V DD ≤ 5.5 V
0.8VDD
VDD
V
1.8 ≤ V DD < 2.7 V
0.9VDD
VDD
V
On-chip pull-up
2.7 ≤ V DD ≤ 5.5 V
0.7VDD
VDD
V
resistor
1.8 ≤ V DD < 2.7 V
0.9VDD
VDD
V
When N-ch
2.7 ≤ V DD ≤ 5.5 V
0.7VDD
13
V
open-drain
1.8 ≤ V DD < 2.7 V
0.9VDD
13
V
V DD–0.1
VDD
V
2.7 ≤ V DD ≤ 5.5 V
0
0.3V DD
V
1.8 ≤ V DD < 2.7 V
0
0.1V DD
V
2.7 ≤ V DD ≤ 5.5 V
0
0.2V DD
V
1.8 ≤ V DD < 2.7 V
0
0.1V DD
V
0
0.1
V
Ports 0, 1, 6, RESET
VIH4
Unit
2.7 ≤ V DD ≤ 5.5 V
Ports 2, 3, 8, 9
Port 5
MAX.
Ports 0, 1, 6, RESET
VIL3
X1, XT1
Output voltage high
VOH
SCK, SO, ports 2, 3, 6, 8, 9 IOH = –1.0 mA
Output voltage low
VOL1
SCK, SO, ports 2, 3, 5, 6, 8, 9
V DD–0.5
I OL = 15 mA,
V
0.2
2.0
V
0.4
V
0.2V DD
V
VDD = 4.5 to 5.5 V
I OL = 1.6 mA
VOL2
SB0, SB1
N-ch open-drain
pull-up resistor ≥ 1 kΩ
Input leakage
I LIH1
V IN = VDD
Pins other than X1, XT1
3
µA
current high
I LIH2
X1, XT1
20
µA
I LIH3
V IN = 13 V
Port 5 (When N-ch open-drain)
20
µA
Input leakage
I LIL1
V IN = 0 V
Pins other than X1, XT1, port 5
–3
µA
current low
I LIL2
X1, XT1
–20
µA
I LIL3
Port 5 (When N-ch open-drain)
When input instruction is not executed
–3
µA
–30
–27
–8
µA
µA
µA
Port 5 (When N-ch
open-drain) When input VDD = 5.0 V
instruction is executed VDD = 3.0 V
–10
–3
I LOH1
V OUT = VDD
SCK, SO/SB0, SB1, ports 2, 3, 6, 8, 9,
port 5 (When N-ch open-drain)
3
µA
I LOH2
V OUT = 13 V
Port 5 (When N-ch open-drain)
20
µA
Output leakage
current low
I LOL
V OUT = 0 V
–3
µA
On-chip pull-up resistor
RL1
V IN = 0 V
Output leakage
current high
RL2
Ports 0 to 3, 6, 8, 9
(Excluding P00 pin)
50
100
200
kΩ
Port 5 (mask option)
15
30
60
kΩ
65
µ PD753104, 753106, 753108
DC CHARACTERISTICS (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
LCD drive voltage
VLCD
VAC0 = 0
Test conditions
MIN.
TA = –40 to +85 °C
TA = –10 to +85 °C
VAC0 = 1
VAC current
Note 1
LCD split resistor
I VAC
Note 2
2.7
VDD
V
2.2
VDD
V
1.8
VDD
V
1
4
µA
50
100
200
kΩ
RLCD2
5
10
20
kΩ
LCD output voltage
VODS
deviation Note 3 (segment)
I DD1
I DD2
I DD1
I O = ±1.0 µ A
VLCD0 = VLCD
VLCD1 = VLCD x 2/3
VLCD2 = VLCD x 1/3
1.8 V ≤ VLCD ≤ V DD
0
±0.2
V
I O = ±5.0 µ A
VLCD0 = VLCD
VLCD1 = VLCD x 2/3
VLCD2 = VLCD x 1/3
2.2 V ≤ VLCD ≤ V DD
0
±0.2
V
I O = ±0.5 µ A
VLCD0 = VLCD
VLCD1 = VLCD x 2/3
VLCD2 = VLCD x 1/3
1.8 V ≤ VLCD ≤ V DD
0
±0.2
V
I O = ±1.0 µ A
VLCD0 = VLCD
VLCD1 = VLCD x 2/3
VLCD2 = VLCD x 1/3
2.2 V ≤ VLCD ≤ V DD
0
±0.2
V
6.0 MHz Note 5
VDD = 5.0 V ± 10%
Note 6
1.9
6.0
mA
Crystal oscillation VDD = 3.0 V ± 10%
Note 7
0.4
1.3
mA
HALT mode V DD = 5.0 V ± 10%
0.72
2.1
mA
V DD = 3.0 V ± 10%
0.27
0.8
mA
1.5
4.0
mA
0.25
0.75
mA
0.7
2.0
mA
0.23
0.7
mA
32.768 kHz Note 8 Low-voltage V DD = 3.0 V ± 10%
12
35.0
µA
V DD = 2.0 V ± 10%
4.5
12.0
µA
V DD = 3.0 V, TA = 25 ˚C
12
24.0
µA
Low current consump- V DD = 3.0 V ± 10%
6.0
18.0
µA
tion mode Note 10
V DD = 3.0 V, TA = 25 ˚C
6.0
12.0
µA
V DD = 3.0 V ± 10%
8.5
25
µA
V DD = 2.0 V ± 10%
3.0
9.0
µA
VDD = 3.0 V, T A = 25 ˚C
8.5
17
µA
Low current V DD = 3.0 V ± 10%
consumption
mode Note 10 VDD = 3.0 V, T A = 25 ˚C
3.5
12
µA
3.5
7.0
µA
VDD = 5.0 V ± 10%
0.05
10
µA
VDD = 3.0 V
0.02
5.0
µA
0.02
3.0
µA
C1 = C2 = 22 pF
4.19 MHz Note 5
VDD = 5.0 V ± 10% Note 6
Crystal oscillation VDD = 3.0 V ± 10% Note 7
I DD2
C1 = C2 = 22 pF
HALT mode V DD = 5.0 V ± 10%
V DD = 3.0 V ± 10%
I DD3
Crystal oscillation mode
I DD4
Note 9
HALT mode Lowvoltage
mode
I DD5
XT1 = 0 V
Note 11
STOP mode
±10%
66
Unit
RLCD1
LCD output voltage
VODC
deviation Note 3 (common)
Supply current Note 4
MAX.
VAC0 = 1, V DD = 2.0 V ± 10%
TYP.
Note 9
T A = 25 ˚C
µ PD753104, 753106, 753108
Notes 1.
Clear VAC0 to 0 in the low current consumption mode and STOP mode. When VAC0 is set to 1, the
current increases by about 1 µ A.
2.
Either R LCD1 or RLCD2 can be selected by the mask option.
3.
The voltage deviation is the difference from the output voltage corresponding to the ideal value of the
segment and common outputs (VLCDn; n = 0, 1, 2).
4.
Not including currents flowing in on-chip pull-up resistors or LCD split resistors.
5.
Including oscillation of the subsystem clock.
6.
When the processor clock control register (PCC) is set to 0011 and the device is operated in the highspeed mode.
7.
When PCC is set to 0000 and the device is operated in the low-speed mode.
8.
When the system clock control register (SCC) is set to 1001 and the device is operated on the
subsystem clock, with main system clock oscillation stopped.
9.
When the sub-oscillator control register (SOS) is set to 0000.
10.
When the SOS is set to 0010.
11.
When the SOS is set to 00x1, and the sub-oscillator feedback resistor is not used (x : don’t care).
67
µ PD753104, 753106, 753108
AC CHARACTERISTICS (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
CPU clock cycle
time
Test conditions
MAX.
Unit
0.67
64
µs
main system clock
0.95
64
µs
Operating on subsystem clock
114
125
µs
0
1.0
MHz
0
275
kHz
Operating on
t CY
Note 1
(minimum instruction execution
MIN.
VDD = 2.7 to 5.5 V
TYP.
122
time = 1 machine cycle)
TI0, TI1, TI2 input
f TI
VDD = 2.7 to 5.5 V
frequency
t TIH, tTIL
TI0, TI1, TI2 input
0.48
µs
1.8
µs
IM02 = 0
Note 2
µs
IM02 = 1
10
µs
INT1, 2, 4
10
µs
KR0-KR3
10
µs
10
µs
VDD = 2.7 to 5.5 V
high/low-level width
Interrupt input high/
t INTH, tINTL INT0
low-level width
RESET low-level width
Notes 1.
t RSL
tCY vs VDD
(At main system clock operation)
The cycle time (minimum instruction
execution time) of the CPU clock
64
60
(Φ) is determined by the oscillation
frequency of the connected
6
system clock control register (SCC)
5
and the processor clock control
register (PCC). The figure at the
right indicates the cycle time tCY
versus
supply
voltage
V DD
characteristic with the main system
Cycle Time tCY [µs]
resonator (and external clock), the
Operation Guaranteed
Range
4
3
2
clock operating.
2.
2tCY or 128/fx is set by setting the
interrupt mode register (IM0).
1
0.5
0
1
2
3
4
5
Supply Voltage VDD [V]
68
6
µ PD753104, 753106, 753108
SERIAL TRANSFER OPERATION
2-Wire and 3-Wire Serial I/O Modes (SCK...Internal clock output): (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high/low-level
Symbol
t KCY1
t KL1, t KH1
Test conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
width
SI
Note 1
setup time
t SIK1
VDD = 2.7 to 5.5 V
(to SCK↑)
SI
Note 1
hold time
t KSI1
VDD = 2.7 to 5.5 V
(from SCK↑)
SO
Note 1
output delay time
t KSO1
from SCK↓
Notes 1.
2.
RL = 1 kΩ,
Note 2
VDD = 2.7 to 5.5 V
CL = 100 pF
MIN.
TYP.
MAX.
Unit
1300
ns
3800
ns
tKCY1 /2–50
ns
t KCY1/2–150
ns
150
ns
500
ns
400
ns
600
ns
0
250
ns
0
1000
ns
Read as SB0 or SB1 when using the 2-wire serial I/O mode.
R L and CL are the load resistance and load capacitance of the SO output line.
2-Wire and 3-Wire Serial I/O Modes (SCK...External clock input): (T A = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high/low-level
Symbol
t KCY2
t KL2, t KH2
Test conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
width
SI
Note 1
setup time
t SIK2
VDD = 2.7 to 5.5 V
(to SCK↑)
SI
Note 1
hold time
t KSI2
VDD = 2.7 to 5.5 V
(from SCK↑)
SO
Note 1
output delay time
from SCK↓
Notes 1.
2.
t KSO2
RL = 1 kΩ,
Note 2
VDD = 2.7 to 5.5 V
CL = 100 pF
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
150
ns
400
ns
600
ns
0
300
ns
0
1000
ns
Read as SB0 or SB1 when using the 2-wire serial I/O mode.
R L and CL are the load resistance and load capacitance of the SO output line.
69
µ PD753104, 753106, 753108
SBI Mode (SCK...Internal clock output (master)): (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high/low-level
Symbol
t KCY3
t KL3, t KH3
Test conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
width
SB0, 1 setup time
t SIK3
VDD = 2.7 to 5.5 V
(to SCK↑)
SB0, 1 hold time (from SCK↑)
t KSI3
SB0, 1 output delay
t KSO3
time from SCK↓
RL = 1 kΩ,
Note
VDD = 2.7 to 5.5 V
CL = 100 pF
MIN.
TYP.
MAX.
Unit
1300
ns
3800
ns
tKCY3/2–50
ns
t KCY3/2–150
ns
150
ns
500
ns
tKCY3 /2
ns
0
250
ns
0
1000
ns
SB0, 1↓ from SCK↑
t KSB
t KCY3
ns
SCK↓ from SB0, 1↓
t SBK
t KCY3
ns
SB0, 1 low-level width
t SBL
t KCY3
ns
SB0, 1 high-level width
tSBH
t KCY3
ns
Note
R L and CL are the load resistance and load capacitance of the SB0, 1 output line.
SBI Mode (SCK...External clock input (slave)): (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high/low-level
Symbol
t KCY4
t KL4, t KH4
Test conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
width
SB0, 1 setup time
t SIK4
VDD = 2.7 to 5.5 V
(to SCK↑)
SB0, 1 hold time (from SCK↑)
t KSI4
SB0, 1 output delay
t KSO4
time from SCK↓
RL = 1 kΩ,
CL = 100 pF
Note
VDD = 2.7 to 5.5 V
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
150
ns
tKCY4 /2
ns
0
300
ns
0
1000
ns
SB0, 1↓ from SCK↑
t KSB
t KCY4
ns
SCK↓ from SB0, 1↓
t SBK
t KCY4
ns
SB0, 1 low-level width
t SBL
t KCY4
ns
SB0, 1 high-level width
tSBH
t KCY4
ns
Note
70
R L and CL are the load resistance and load capacitance of the SB0, 1 output line.
µ PD753104, 753106, 753108
AC Timing Test Point (Excluding X1, XT1 inputs)
VIH (MIN.)
VIL (MAX.)
VIH (MIN.)
VIL (MAX.)
VOH (MIN.)
VOL (MAX.)
VOH (MIN.)
VOL (MAX.)
Clock Timing
1/fX
tXL
tXH
VDD–0.1 V
0.1 V
X1 Input
1/fXT
tXTL
tXTH
VDD–0.1 V
0.1 V
XT1 Input
TI0, TI1, TI2 Timing
1/fTI
tTIL
tTIH
TI0, TI1, TI2
71
µ PD753104, 753106, 753108
Serial Transfer Timing
3-wire serial I/O mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK
tSIK1, 2
SI
tKSI1, 2
Input Data
tKSO1, 2
SO
Output Data
2-wire serial I/O mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK
tSIK1, 2
SB0, 1
tKSO1, 2
72
tKSI1, 2
µ PD753104, 753106, 753108
Serial Transfer Timing
Bus release signal transfer
tKCY3, 4
tKL3, 4
tKH3, 4
SCK
tKSB
tSBL
tSBH
tSIK3, 4
tSBK
tKSI3, 4
SB0, 1
tKSO3, 4
Command signal transfer
tKCY3, 4
tKL3, 4
tKH3, 4
SCK
tKSB
tSIK3, 4
tSBK
tKSI3, 4
SB0, 1
tKSO3, 4
Interrupt input timing
tINTL
tINTH
INT0, 1, 2, 4
KR0 to 3
RESET input timing
tRSL
RESET
73
µ PD753104, 753106, 753108
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS
(TA = –40 to +85 ˚C)
Parameter
Symbol
Release signal set time
tSREL
Oscillation stabilization
t WAIT
MIN.
TYP.
MAX.
Unit
µs
0
wait time Note 1
Notes 1.
Test conditions
Release by RESET
Note 2
ms
Release by interrupt request
Note 3
ms
The oscillation stabillization wait time is the time during which the CPU operation is stopped to prevent
unstable operation at the oscillation start.
2.
Either 2 17/fX or 215/fX can be selected by the mask option.
3.
Depends on the basic interval timer mode register (BTM) settings (see the table below).
BTM3
BTM2
—
—
—
—
0
0
1
1
BTM1
0
1
0
1
BTM0
0
1
1
1
Wait time
220/fx
217/fx
215/fx
213/fx
fx = at 4.19 MHz
(approx. 250 ms)
(approx. 31.3 ms)
(approx. 7.81 ms)
(approx. 1.95 ms)
220/fx
217/fx
215/fx
213/fx
fx = at 6.0 MHz
(approx. 175 ms)
(approx. 21.8 ms)
(approx. 5.46 ms)
(approx. 1.37 ms)
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
tSREL
STOP Instruction Execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
74
µ PD753104, 753106, 753108
13. CHARACTERISTIC CURVES (FOR REFERENCE ONLY)
I DD vs VDD (Main System Clock: 6.0-MHz Crystal Resonator)
(TA = 25 °C)
10
5.0
PCC = 0011
PCC = 0010
1.0
PCC = 0001
PCC = 0000
Supply Current IDD (mA)
0.5
Main system clock
HALT mode + 32-kHz oscillation
0.1
Subsystem clock operation
mode (SOS.1 = 0)
0.05
Main system clock STOP
mode + 32-kHz oscillation
(SOS.1 = 0)
Subsystem clock HALT mode
(SOS.1 = 0)
Main system clock STOP
mode + 32-kHz oscillation
(SOS.1 = 1) and subsystem
clock HALT mode (SOS.1 = 1)
0.01
0.005
X1
X2 XT1
Crystal
resonator
22 pF
0.001
0
1
2
3
4
5
XT2
Crystal
resonator
6.0 MHz
32.768 kHz
330 kΩ
22 pF
22 pF
22 pF
VDD
VDD
6
7
8
Supply Voltage VDD (V)
75
µ PD753104, 753106, 753108
I DD vs VDD (Main System Clock: 4.19-MHz Crystal Resonator)
(TA = 25 °C)
10
5.0
PCC = 0011
1.0
PCC = 0010
PCC = 0001
PCC = 0000
Supply Current IDD (mA)
0.5
Main system clock
HALT mode + 32-kHz oscillation
0.1
Subsystem clock operation
mode (SOS.1 = 0)
0.05
Subsystem clock HALT mode
(SOS.1 = 0)
Main system clock STOP
mode + 32-kHz oscillation
(SOS.1 = 0)
Main system clock STOP
mode + 32-kHz oscillation
and subsystem
clock HALT mode (SOS.1 = 1)
0.01
0.005
X1
X2 XT1
Crystal
resonator
22 pF
0.001
0
1
2
3
4
5
Supply Voltage VDD (V)
76
XT2
Crystal
resonator
4.19 MHz
32.768 kHz
330 kΩ
22 pF
22 pF
22 pF
VDD
VDD
6
7
8
µ PD753104, 753106, 753108
I OH vs VDD—VOH (Ports 2, 3, 6, 8 and 9)
(TA = 25 °C)
15
10
VDD = 5 V VDD = 4 V
IOH [mA]
VDD = 5.5 V
VDD = 2.2 V
VDD = 3 V
5
0
VDD = 1.8 V
0
0.5
1.0
1.5
2.0
2.5
3.0
VDD—VOH [V]
I OL vs VOL (Ports 2, 3, 6, 8 and 9)
(TA = 25 °C)
40
VDD = 5 V VDD = 4 V
30
VDD = 5.5 V
VDD = 3 V
IOL [mA]
VDD = 2.2 V
20
VDD = 1.8 V
10
0
0
0.5
1.0
1.5
2.0
VOL [V]
77
µ PD753104, 753106, 753108
14. PACKAGE DRAWINGS
64-PIN PLASTIC QFP (14 x 14 mm)
A
B
33
32
48
49
F
Q
5°±5°
S
D
C
detail of lead end
64
1
G
17
16
H
I M
J
M
P
K
N
L
P64GC-80-AB8-3
NOTE
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
78
ITEM
MILLIMETERS
INCHES
A
17.6 ± 0.4
0.693 ± 0.016
B
14.0 ± 0.2
0.551 +0.009
–0.008
C
14.0 ± 0.2
0.551+0.009
–0.008
D
17.6 ± 0.4
0.693 ± 0.016
F
1.0
0.039
G
1.0
0.039
H
0.35 ± 0.10
0.014 +0.004
–0.005
I
0.15
0.006
J
0.8 (T.P.)
0.031 (T.P.)
K
1.8 ± 0.2
0.071 ± 0.008
L
0.8 ± 0.2
0.031+0.009
–0.008
M
0.15+0.10
–0.05
0.006 +0.004
–0.003
N
0.10
0.004
P
2.55
0.100
Q
0.1 ± 0.1
0.004 ± 0.004
S
2.85 MAX.
0.112 MAX.
µ PD753104, 753106, 753108
64-PIN PLASTIC LQFP (12 x 12 mm)
A
B
48
49
33
32
Q
R
D
C
S
detail of lead end
F
64
17
16
1
H
I
M
J
K
M
P
G
N
L
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
14.8±0.4
0.583±0.016
B
12.0±0.2
0.472+0.009
–0.008
C
12.0±0.2
0.472 +0.009
–0.008
D
14.8±0.4
0.583±0.016
F
1.125
0.044
G
1.125
0.044
H
0.30±0.10
0.012+0.004
–0.005
I
0.13
0.005
J
0.65 (T.P.)
0.026 (T.P.)
K
1.4±0.2
0.055±0.008
L
0.6±0.2
0.024+0.008
–0.009
M
0.15 +0.10
–0.05
0.006 +0.004
–0.003
N
0.10
0.004
P
Q
1.4
0.055
R
0.125±0.075
5∞±5∞
0.005±0.003
5∞±5∞
S
1.7 MAX.
0.067 MAX.
P64GK-65-8A8-1
79
µ PD753104, 753106, 753108
15. RECOMMENDED SOLDERING CONDITIONS
The µ PD753108 should be soldered and mounted under the conditions recommended in the table below.
For details of recommended soldering conditions, refer to the information document “Semiconductor Device
Mounting Technology Manual” (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC sales representative.
Table 15-1. Surface Mounting Type Soldering Conditions
(1) µPD753104GC-xxx-AB8 : 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
µPD753106GC-xxx-AB8 : 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
µPD753108GC-xxx-AB8 : 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
Soldering
Method
Soldering Conditions
Symbol
Infrared reflow
Peak package’s surface temperature: 235 ˚C, Reflow time: 30 seconds or less
(at 210 ˚C or higher), Number of reflow processes: 3 max.
IR35-00-3
VPS
Peak package’s surface temperature: 215 ˚C, Reflow time: 40 seconds or less
(at 200 ˚C or higher), Number of reflow processes: 3 max.
VP15-00-3
Wave soldering
Solder temperature: 260 ˚C or below, Flow time: 10 seconds or less, Number of
flow processes: 1, Preheating temperature: 120 ˚C or below (package surface
temperature)
WS60-00-1
Partial heating
Pin temperature: 300 ˚C or below, Time: 3 seconds or less (per device side)
Caution
—
Use of more than one soldering method should be avoided (except for partial heating).
(2) µPD753104GK-xxx-8A8 : 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
µPD753106GK-xxx-8A8 : 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
µPD753108GK-xxx-8A8 : 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
Soldering
Method
Soldering Conditions
Symbol
Infrared reflow
Peak package’s surface temperature: 235 ˚C, Reflow time: 30 seconds or less
(at 210 ˚C or higher), Number of reflow processes: 2 max.
IR35-00-2
VPS
Peak package’s surface temperature: 215 ˚C, Reflow time: 40 seconds or less
(at 200 ˚C or higher), Number of reflow processes: 2 max.
VP15-00-2
Wave soldering
Solder temperature: 260 ˚C or below, Flow time: 10 seconds or less, Number of
flow processes: 1, Preheating temperature: 120 ˚C or below (package surface
temperature)
WS60-00-1
Partial heating
Pin temperature: 300 ˚C or below, Time: 3 seconds or less (per device side)
—
Caution Use of more than one soldering method should be avoided (except for partial heating).
80
µ PD753104, 753106, 753108
APPENDIX A. µPD75308B, 753108 AND 75P3116 FUNCTIONAL LIST
Parameter
Program memory
µ PD75308B
µ PD753108
µ PD75P3116
Mask ROM
0000H to 1F7FH
(8064 x 8 bits)
Mask ROM
0000H to 1FFFH
(8192 x 8 bits)
One-time PROM
0000H to 3FFFH
(16384 x 8 bits)
Data memory
000H to 1FFH
(512 x 4 bits)
CPU
75X Standard
75XL CPU
When main system clock is
selected
0.95, 1.91, 15.3 µs
(during 4.19-MHz operation)
• 0.95, 1.91, 3.81, 15.3 µs (during 4.19-MHz operation)
• 0.67, 1.33, 2.67, 10.7 µs (during 6.0-MHz operation)
When subsystem clock is
selected
122 µs (32.768-kHz operation)
SBS register
None
SBS.3 = 1: Mk I mode selection
SBS.3 = 0: Mk II mode selection
Stack area
000H to 0FFH
000H to 1FFH
Subroutine call instruction
stack operation
2-byte stack
When Mk I mode: 2-byte stack
When Mk II mode: 3-byte stack
BRA !addr1
CALLA !addr1
Unavailable
When Mk I mode: unavailable
When Mk II mode: available
Instruction
execution
time
Stack
Instruction
MOVT XA, @BCDE
MOVT XA, @BCXA
BR BCDE
BR BCXA
I/O port
Available
CALL !addr
3 machine cycles
Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles
CALLF !faddr
2 machine cycles
Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles
CMOS input
8
8
CMOS input/output
16
20
Bit port output
8
0
N-ch open-drain input/output
8
4
Total
40
32
Segment selection: 24/28/32
segments
(can be changed to CMOS
input/output port in 4 timeunit; max. 8)
Segment selection: 16/20/24 segments
(can be changed to CMOS input/output port in 4 time-unit;
max. 8)
LCD controller/driver
Display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias),
1/4 duty (1/3 bias)
On-chip split resistor for LCD driver can be specified by using
mask option.
Timer
3 channels
• Basic interval timer:
1 channel
• 8-bit timer/event counter:
1 channel
• Watch timer: 1 channel
No on-chip split resistor for
LCD driver
5 channels
• Basic interval timer/watchdog timer: 1 channel
• 8-bit timer/event counter: 3 channels
(can be used as 16-bit timer/event counter)
• Watch timer: 1 channel
81
µ PD753104, 753106, 753108
µPD75308B
Parameter
µ PD753108
µPD75P3116
Clock output (PCL)
• Φ, 524, 262, 65.5 kHz
(Main system clock:
during 4.19-MHz operation)
• Φ, 524, 262, 65.5 kHz
(Main system clock: during 4.19-MHz operation)
• Φ, 750, 375, 93.8 kHz
(Main system clock: during 6.0-MHz operation)
BUZ output (BUZ)
• 2 kHz
(Main system clock:
during 4.19-MHz operation)
• 2, 4, 32 kHz
(Main system clock: during 4.19-MHz operation or
subsystem clock: during 32.768-kHz operation)
• 2.93, 5.86, 46.9 kHz
(Main system clock: 6.0-MHz operation)
Serial interface
3 modes are available
• 3-wire serial I/O mode ... MSB/LSB can be selected for transfer first bit
• 2-wire serial I/O mode
• SBI mode
SOS
register
Feedback resistor cut flag
(SOS.0)
None
Contained
Sub-oscillator current cut flag
(SOS.1)
None
Contained
Register bank selection register (RBS)
None
Yes
Standby release by INT0
Unavailable
Available
Vectored interrupt
External: 3, internal: 3
External: 3, internal: 5
Supply voltage
VDD = 2.0 to 6.0 V
V DD = 1.8 to 5.5 V
Operating ambient temperature
TA = –40 to +85 ˚C
Package
• 80-pin plastic QFP
(14 x 20 mm)
• 80-pin plastic QFP
(14 x 14 mm)
• 80-pin plastic TQFP
(Fine pitch) (12 x 12 mm)
82
• 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
• 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
µ PD753104, 753106, 753108
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are provided for system development using the µ PD753108.
In the 75XL Series, the relocatable assembler which is common to the series is used in combination with the
device file of each product.
Language processor
RA75X relocatable assembler
Host machine
OS
PC-9800 Series
3.5-inch 2HD
µS5A13RA75X
Ver. 3.30 to
5-inch 2HD
µS5A10RA75X
Note
IBM PC/AT™ and
Refer to
3.5-inch 2HC
µS7B13RA75X
compatible machines
“OS for IBM PC ”
5-inch 2HC
µS7B10RA75X
Host machine
OS
PC-9800 Series
Supply media
MS-DOS
Ver. 3.30 to
Ver. 6.2
Note
Part number
(product name)
MS-DOS™
Ver. 6.2
Device file
Supply media
Part number
(product name)
3.5-inch 2HD
µS5A13DF753108
5-inch 2HD
µS5A10DF753108
Note
IBM PC/AT and
Refer to
3.5-inch 2HC
µS7B13DF753108
compatible machines
“OS for IBM PC ”
5-inch 2HC
µS7B10DF753108
Ver. 5.00 and later have the task swap function, but it cannot be used for this software.
Remark Operation of the assembler and the device file is guaranteed only on the above host machines and OSs.
83
µ PD753104, 753106, 753108
PROM write tools
Hardware
Software
PG-1500
PG-1500 is a PROM programmer which enables you to program single-chip microcontrollers
including PROM by stand-alone or host machine operation by connecting an attached board
and optional programmer adapter to PG-1500. It also enables you to program typical PROM
devices of 256K bits to 4M bits.
PA-75P3116GC
PROM programmer adapter for the µPD75P3116GC. Connect the programmer adapter to
PG-1500 for use.
PA-75P3116GK
PROM programmer adapter for the µ PD75P3116GK. Connect the programmer adapter to
PG-1500 for use.
PG-1500 controller
PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500
is controlled on the host machine.
Host machine
OS
PC-9800 Series
MS-DOS
Ver. 3.30 to
Supply media
Part number
(product name)
3.5-inch 2HD
µ S5A13PG1500
5-inch 2HD
µ S5A10PG1500
Ver. 6.2 Note
Note
IBM PC/AT and
Refer to
3.5-inch 2HD
µ S7B13PG1500
compatible machines
“ OS for IBM PC”
5-inch 2HC
µ S7B10PG1500
Ver. 5.00 and later have the task swap function, but it cannot be used for this software.
Remark Operation of the PG-1500 controller is guaranteed only on the above host machines and OSs.
84
µ PD753104, 753106, 753108
Debugging tool
The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the
µ PD753108.
The system configurations are described as follows.
Hardware
IE-75000-R
Note 1
In-circuit emulator for debugging the hardware and software when developing the application
systems that use the 75X Series and 75XL Series. When developing a µ PD753108
Subseries, the emulation board (IE-75300-R-EM) and emulation probe (EP-753108GC-R
or EP-753108GK-R) that are sold separately must be used with the IE-75000-R.
By connecting with the host machine and the PROM programmer, efficient debugging can
be made.
It contains the emulation board (IE-75000-R-EM) which is connected.
IE-75001-R
In-circuit emulator for debugging the hardware and software when developing the application
systems that use the 75X Series and 75XL Series. When developing a µ PD753108
Subseries, the emulation board (IE-75300-R-EM) and emulation probe (EP-753108GC-R
or EP-753108GK-R) that are sold separately must be used with the IE-75001-R.
It can debug the system efficiently by connecting the host machine and PROM programmer.
IE-75300-R-EM
Emulation board for evaluating the application systems that use a µ PD753108 Subseries.
It must be used with the IE-75000-R or IE-75001-R.
EP-753108GC-R
Emulation probe for the µPD753108GC.
It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM.
It is supplied with the 64-pin conversion socket EV-9200GC-64 which facilitates
connection to a target system.
EV-9200GC-64
EP-753108GK-R
TGK-064SBW
Software
Note 2
IE control program
Emulation probe for the µPD753108GK.
It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM.
It is supplied with the 64-pin conversion adapter TGK-064SBW which facilitates
connection to a target system.
Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronics interface
and controls the IE-75000-R or IE-75001-R on a host machine.
Host machine
OS
PC-9800 Series
MS-DOS
Ver. 3.30 to
Supply media
Part No.
(product name)
3.5-inch 2HD
µS5A13IE75X
5-inch 2HD
µS5A10IE75X
3.5-inch 2HC
µS7B13IE75X
5-inch 2HC
µS7B10IE75X
Ver. 6.2 Note 3
IBM PC/AT and
compatible machines
Notes 1.
2.
Refer to
“OS for IBM PC ”
Maintenance product.
This is a product of TOKYO ELETECH CORPORATION (Tokyo 03-5295-1661). For purchasing,
contact an NEC sales representative.
3.
Ver. 5.00 and later have the task swap function, but it cannot be used for this software.
Remarks 1. Operation of the IE control program is guaranteed only on the above host machines and OSs.
2. The µ PD753104, 753106, 753108 and 75P3116 are commonly referred to as the µ PD753108
Subseries.
85
µ PD753104, 753106, 753108
OS for IBM PC
The following IBM PC OS’s are supported.
OS
Version
PC DOS™
Ver. 3.1 to Ver. 6.3
J6.1/V Note to J6.3/V
MS-DOS
Ver. 5.0 to Ver. 6.22
5.0/V Note to 6.2/V Note
IBM DOS™
J5.02/V Note
Note
Note Only the English mode is supported.
Caution
86
Ver. 5.0 and later have the task swap function, but it cannot be used for this software.
µ PD753104, 753106, 753108
APPENDIX C. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Device Related Documents
Document No.
Document Name
English
Japanese
µPD753104, 753106, 753108 Data Sheet
U10086E (This document)
U10086J
µPD75P3116 Data Sheet
U11369E
U11369J
µPD753108 User’s Manual
U10890E
U10890J
µPD753108 Instruction Application Table
—
75XL Series Selection Guide
IEM-5600
U10453E
U10453J
Development Tool Related Documents
Document No.
Document Name
English
Hardware
Software
Japanese
IE-75000-R/IE-75001-R User’s Manual
EEU-1416
EEU-846
IE-75300-R-EM User’s Manual
U11354E
U11354J
EP-753108GC/GK-R User’s Manual
EEU-1495
EEU-968
PG-1500 User’s Manual
EEU-1335
U11940J
RA75X Assembler Package
Operation
EEU-1346
EEU-731
User’s Manual
Language
EEU-1363
EEU-730
PG-1500 Controller User’s Manual
PC-9800 Series
(MS-DOS) base
EEU-1291
EEU-704
IBM PC Series
(PC DOS) base
U10540E
EEU-5008
Other Related Documents
Document No.
Document Name
English
Japanese
IC Package Manual
C10943X
Semiconductor Device Mounting Technology Manual
C10535E
C10535J
Quality Grades on NEC Semiconductor Devices
C11531E
C11531J
NEC Semiconductor Device Reliability/Quality Control System
C10983E
C10983J
Electrostatic Discharge (ESD) Test
Guide to Quality Assurance for Semiconductor Devices
Microcomputer Product Series Guide
Caution
—
MEM-539
MEI-1202
C11893J
—
U11416J
The above related documents are subject to change without notice. For design purpose, etc.,
be sure to use the latest documents.
87
µ PD753104, 753106, 753108
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred.
Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to
avoid using insulators that easily build static electricity.
Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded
using wrist strap. Semiconductor devices must not be touched with bare
hands. Similar precautions need to be taken for PW boards with semiconductor
devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using a pull-up or pull-down circuitry.
Each unused pin should be connected to VDD or GND with a resistor, if it is
considered to have a possibility of being an output pin. All handling related
to the unused pins must be judged device by device and related specifications
governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately
after power-on for devices having reset function.
88
µ PD753104, 753106, 753108
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd.
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd.
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
J96. 8
89
µ PD753104, 753106, 753108
MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/
or other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5
90