TPIC5403 4-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995 • • • • • Low rDS(on) . . . 0.23 Ω Typ High Voltage Output . . . 60 V Extended ESD Capability . . . 4000 V Pulsed Current . . . 11.25 A Per Channel Fast Commutation Speed DW PACKAGE (TOP VIEW) DRAIN1 DRAIN1 GATE1 GND SOURCE1 SOURCE1 SOURCE2 SOURCE2 GND GATE2 DRAIN2 DRAIN2 description The TPIC5403 is a monolithic gate-protected power DMOS array that consists of four independent electrically isolated N-channel enhancement-mode DMOS transistors. Each transistor features integrated high-current zener diodes (ZCXa and ZCXb) to prevent gate damage in the event that an overstress condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the human-body model of a 100-pF capacitor in series with a 1.5-kΩ resistor. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 DRAIN3 DRAIN3 GATE3 GND SOURCE3 SOURCE3 SOURCE4 SOURCE4 GND GATE4 DRAIN4 DRAIN4 The TPIC5403 is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation over the case temperature range of – 40°C to 125°C. schematic DRAIN1 1, 2 23, 24 Q3 Q1 GATE1 D1 3 DRAIN2 5, 6 D3 22 Z3 Z1 ZC1b SOURCE1 ZC1a ZC3a SOURCE2 SOURCE3 DRAIN4 Q4 10 7, 8 19, 20 13, 14 11, 12 15 ZC2b GATE3 ZC3b Q2 GATE2 DRAIN3 Z2 D2 D4 Z4 ZC4a ZC2a GATE4 ZC4b 17, 18 SOURCE4 4, 9, 16, 21 GND NOTE A: For correct operation, no terminal may be taken below GND. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPIC5403 4-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995 absolute maximum ratings over operating case temperature range (unless otherwise noted)† Drain-to-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V Source-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V Drain-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V Gate-to-source voltage range, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 9 V to 18 V Continuous drain current, each output, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25 A Continuous source-to-drain diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25 A Pulsed drain current, each output, Imax, TC = 25°C (see Note 1 and Figure 15) . . . . . . . . . . . . . . . . . 11.25 A Continuous gate-to-source zener diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Pulsed gate-to-source zener diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 500 mA Single-pulse avalanche energy, EAS, TC = 25°C (see Figures 4, 15, and 16) . . . . . . . . . . . . . . . . . . . 17.2 mJ Continuous total power dissipation, TC = 25°C (see Figure 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.39 W Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Pulse duration = 10 ms, duty cycle = 2% 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC5403 4-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995 electrical characteristics, TC = 25°C (unless otherwise noted) PARAMETER V(BR)DSX Drain-to-source breakdown voltage VGS(th) Gate-to-source threshold voltage V(BR)GS V(BR)SG Gate-to-source breakdown voltage TEST CONDITIONS ID = 250 µA, ID = 1 mA, See Figure 5 VGS = 0 VDS = VGS, IGS = 250 µA ISG = 250 µA Source-to-gate breakdown voltage V(BR) Reverse drain-to-GND breakdown voltage (across D1, D2, D3, and D4) Drain-to-GND current = 250 µA VDS(on) Drain-to-source on-state voltage ID = 2.25 A, See Notes 2 and 3 VF(SD) Forward on-state voltage, source-to-drain VF MIN TYP MAX 60 1.5 UNIT V 1.75 2.2 V 18 V 9 V 100 V VGS = 10 V, 0.5 0.62 V IS = 2.25 A, VGS = 0 (Z1, Z2, Z3, Z4), See Notes 2 and 3 and Figure 12 0.9 1.1 V Forward on-state voltage, GND-to-drain ID = 2.25 A (D1, D2, D3, D4), See Notes 2 and 3 2.5 IDSS Zero gate voltage drain current Zero-gate-voltage VDS = 48 V,, VGS = 0 TC = 25°C TC = 125°C IGSSF Forward gate current, drain short circuited to source VGS = 15 V, IGSSR Reverse gate current, drain short circuited to source Ilk lkg rDS( DS(on)) V 0.05 1 0.5 10 VDS = 0 20 200 nA VSG = 5 V, VDS = 0 10 100 nA Leakage current, current drain-to-GND drain to GND VDGND = 48 V TC = 25°C TC = 125°C 0.05 1 0.5 10 TC = 25°C 0.23 0.27 drain to source on-state on state resistance Static drain-to-source VGS = 10 V, ID = 2.25 A,, See Notes 2 and 3 and Figures 6 and 7 TC = 125°C 0.35 0.4 VDS = 15 V, ID = 1.125 A, See Notes 2 and 3 and Figure 9 gfs Forward transconductance Ciss Short-circuit input capacitance, common source Coss Short-circuit output capacitance, common source Crss Short-circuit reverse-transfer capacitance, common source VDS = 25 V, f = 1 MHz, µA µA Ω 1.6 VGS = 0, See Figure 11 2.1 S 200 250 100 175 60 75 pF F NOTES: 2. Technique should limit TJ – TC to 10°C maximum. 3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. source-to-drain and GND-to-drain diode characteristics, TC = 25°C PARAMETER trr Reverse recovery time Reverse-recovery QRR Total diode charge TEST CONDITIONS IS = 1.125 A, VGS = 0, 0 See Figures 1 and 14 VDS = 48 V, di/dt = 100 A/µs A/µs, POST OFFICE BOX 655303 MIN TYP Z1, Z2, Z3, and Z4 80 D1, D2, D3, and D4 160 Z1, Z2, Z3, and Z4 0.12 D1, D2, D3, and D4 0.5 • DALLAS, TEXAS 75265 MAX UNIT ns µC 3 TPIC5403 4-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995 resistive-load switching characteristics, TC = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX 32 55 27 50 14 30 7 15 td(on) td(off) Turn-on delay time tr2 tf2 Rise time Qg Total gate charge Qgs(th) Threshold gate-to-source charge Qgd Gate-to-drain charge LD Internal drain inductance 5 LS Internal source inductance 5 Rg Internal gate resistance Turn-off delay time RL = 20 Ω,, See Figure 2 VDD = 25 V,, tf1 = 10 ns, tr1 = 10 ns,, Fall time VDS = 48 V, V See Figure 3 ID = 1 1.125 125 A A, VGS = 10 V, V 6.6 8 0.6 0.7 2.8 3.2 UNIT ns nC nH Ω 0.25 thermal resistance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RθJA Junction-to-ambient thermal resistance See Notes 4 and 7 90 °C/W RθJB Junction-to-board thermal resistance See Notes 5 and 7 49 °C/W RθJP Junction-to-pin thermal resistance See Notes 6 and 7 28 °C/W NOTES: 4. 5. 6. 7. 4 Package mounted on an FR4 printed-circuit board with no heatsink Package mounted on a 24 inch2, 4-layer FR4 printed-circuit board Package mounted in intimate contact with infinite heatsink All outputs with equal power POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC5403 4-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION 1.5 Reverse di/dt = 100 A/µs I S – Source-to-Drain Diode Current – A 0.75 0 – 0.75 25% of IRM† – 1.5 – 2.25 Shaded Area = QRR –3 IRM† VDS = 48 V VGS = 0 TJ = 25°C Z1 – Z4‡ – 3.75 trr(SD) – 4.25 0 50 100 150 200 250 300 350 400 450 500 Time – ns † IRM = maximum recovery current ‡ The above waveform is representative of D1, D2, D3, and D4 in shape only. Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode VDD = 25 V tr1 RL Pulse Generator 10 V VDS VGS 0V VGS 50 Ω 50 Ω td(off) td(on) DUT Rgen tf1 tr2 tf2 CL 30 pF (see Note A) VDD VDS VDS(on) VOLTAGE WAVEFORMS TEST CIRCUIT NOTE A: CL includes probe and jig capacitance. Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPIC5403 4-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION Current Regulator 12-V Battery 0.2 µF Qg Same Type as DUT 50 kΩ 10 V 0.3 µF Qgs(th) VDD Qgd VGS VDS Gate Voltage DUT IG = 100 µA 0 Time VOLTAGE WAVEFORM IG CurrentSampling Resistor ID CurrentSampling Resistor TEST CIRCUIT Figure 3. Gate-Charge Test Circuit and Voltage Waveform VDD = 25 V tw 159 µH Pulse Generator (see Note A) ID 15 V VDS VGS 0V IAS (see Note B) VGS 50 Ω tav DUT ID 0V Rgen 50 Ω V(BR)DSX = 60 V Min VDS 0V VOLTAGE AND CURRENT WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω. B. Input pulse duration (tw) is increased until peak current IAS = 11.25 A. I V t av AS (BR)DSX Energy test level is defined as E 17.2 mJ. AS 2 + + Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC5403 4-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995 TYPICAL CHARACTERISTICS STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 0.6 2.5 ID = 2.25 A ID = 1 mA 1.5 ID = 100 µA ÁÁ ÁÁ ÁÁ ÁÁ 1 ÁÁ ÁÁ ÁÁ 0.5 0 – 40 – 20 0 20 40 60 80 100 120 140 160 TJ – Junction Temperature – °C 0.4 VGS = 10 V 0.2 VGS = 15 V 0 – 40 – 20 PRODUCT PREVIEW 2 On-State Resistance –Ω VDS = VGS rDS(on) – Static Drain-to-Source VGS(th) – Gate-to-Source Threshold Voltage – V GATE-TO-SOURCE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 0 20 40 60 80 100 120 140 160 TJ – Junction Temperature – °C Figure 5 Figure 6 DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 10 0.5 TJ = 25°C VGS = 15 V VGS = 10 V 9 VGS = 6 V ÁÁ ÁÁ ÁÁ ÁÁ I D – Drain Current – A 8 On-State Resistance –Ω rDS(on) – Static Drain-to-Source 0.4 0.3 VGS = 10 V ÁÁ ÁÁ 0.2 VGS = 15 V ∆VGS = 0.4 V TJ = 25°C (unless otherwise noted) 7 6 5 4 VGS = 4 V 3 2 1 0.1 0.1 0 1 10 ID – Drain Current – A 100 0 1 Figure 7 7 8 9 2 3 4 5 6 VDS – Drain-to-Source Voltage – V 10 Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPIC5403 4-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995 TYPICAL CHARACTERISTICS DRAIN CURRENT vs GATE-TO-SOURCE VOLTAGE DISTRIBUTION OF FORWARD TRANSCONDUCTANCE 45 Percentage of Units – % 40 10 Total Number of Units = 688 VDS = 15 V ID = 1.125 A TJ = 25°C TJ = 40°C 9 35 30 25 TJ = 75°C 15 10 6 5 4 3 2 2.225 2.2 2.175 2.150 2.125 2.1 2.075 0 2.050 0 2.025 1 2 5 1.975 TJ = 150°C 7 ÁÁ ÁÁ 20 TJ = 125°C TJ = 25°C 8 I D – Drain Current – A 50 0 1 7 8 2 3 4 5 6 VGS – Gate-to-Source Voltage – V 9 10 gfs – Forward Transconductance – S Figure 9 Figure 10 CAPACITANCE vs DRAIN-TO-SOURCE VOLTAGE 400 10 320 280 240 I SD – Source-to-Drain Diode Current – A VGS = 0 f = 1MHz TJ = 25°C Ciss @ 0 V = 301 pF Coss @ 0 V = 384 pF Crss @ 10 V = 144 pF 360 C – Capacitance – pF SOURCE-TO-DRAIN DIODE CURRENT vs SOURCE-TO-DRAIN VOLTAGE Ciss 200 160 Coss 120 Crss 80 40 0 0 4 8 12 16 20 24 28 32 36 40 VGS = 0 TJ = 40°C TJ = 125°C 1 TJ = 25°C TJ = 150°C TJ = 75°C 0.1 0.1 VDS – Drain-to-Source Voltage – V Figure 11 8 1 VSD – Source-to-Drain Voltage – V Figure 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10 TPIC5403 4-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995 TYPICAL CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE AND GATE-TO-SOURCE VOLTAGE vs GATE CHARGE 12 ID = 1.125 A TJ = 25°C See Figure 3 50 10 VDD = 20 V 8 40 VDD = 30 V 30 6 20 4 VDD = 48 V 10 2 VGS – Gate-to-Source Voltage – V VDS – Drain-to-Source Voltage – V 60 VDD = 20 V 0 0 0 1 2 3 4 5 Qg – Gate Charge – nC 6 7 Figure 13 REVERSE-RECOVERY TIME vs REVERSE di/dt t rr – Reverse-Recovery Time – ns 175 VDS = 48 V VGS = 0 IS = 1.125 A TJ = 25°C See Figure 1 150 125 D1, D2, D3, and D4 100 75 50 Z1, Z2, Z3, and Z4 25 0 0 100 200 300 400 500 600 Reverse di/dt – A/µs Figure 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TPIC5403 4-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995 THERMAL INFORMATION MAXIMUM DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE 100 I D – Maximum Drain Current – A TC = 25°C 1 µs† 10 10 ms† 1 ms† 500 µs† 1 RθJP‡ RθJA§ DC Conditions 0.1 0.1 1 10 VDS – Drain-to-Source Voltage – V 100 † Less than 2% duty cycle ‡ Device mounted in intimate contact with infinite heatsink. § Device mounted on FR4 printed circuit board with no heatsink. Figure 15 MAXIMUM PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE I AS – Maximum Peak Avalanche Current – A 100 See Figure 4 10 TC = 25°C TC = 125°C 1 0.01 0.1 1.0 10 tav – Time Duration of Avalanche – ms Figure 16 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100 TPIC5403 4-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995 THERMAL INFORMATION DW PACKAGE† JUNCTION-TO-BOARD THERMAL RESISTANCE vs PULSE DURATION 100 RθJB – Junction-to-Board Thermal Resistance – °C/W DC Conditions d = 0.5 d = 0.2 10 d = 0.1 d = 0.05 d = 0.02 1 d = 0.01 tc Single Pulse tw ID 0 0.1 0.0001 0.001 0.1 0.01 1 10 100 tw – Pulse Duration – s † Device mounted on 24in2, 4-layer FR4 printed-circuit board with no heatsink. NOTE A: ZθJB(t) = r(t) RθJB tw = pulse duration tc = cycle time d = duty cycle = tw / tc Figure 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 PACKAGE OPTION ADDENDUM www.ti.com 8-Apr-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TPIC5403DW OBSOLETE SOIC DW Pins Package Eco Plan (2) Qty 24 TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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