SN75DP126 www.ti.com SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 DisplayPort™ 1:2 Re-Driver Switch with TMDS Translator Check for Samples: SN75DP126 FEATURES 1 • 2 • • • • • • • • • One Dual-Mode DisplayPort™ (DP++) Input; Switchable to One DP++ Output or One TMDS Output Compatible with HDMI 1.4b and DVI Supports DP v1.1a and DP v1.2 Signaling Including HBR2 Data Rates to 5.4 Gbps Supports HDMI 1.4b with TMDS Clock Frequencies up to 340 MHz with 10 m Cable Glue-less interface to AMD, Intel, and NVIDIA Graphics Processors Auto-Configuration Through Link Training for DisplayPort Connection Integrated DDC-Accessible DP-HDMI Adaptor ID for HDMI/DVI Sink Recognition Output Signal Conditioning with Tunable Voltage Swing and Pre-Emphasis Gain for both DisplayPort and TMDS Outputs Highly-Configurable Input-Variable Equalizer Two Device Options Including a Dual PowerSupply Configuration for Lowest Power 2-kV ESD HBM Protection • • Temperature Range: 0°C to 85°C 56-Pin 5 mm x 11 mm QFN Package APPLICATIONS • • • • Notebook PC Desktop PC PC Docking Station PC Standalone Video Card DESCRIPTION The SN75DP126 switches one Dual-Mode DisplayPort (DP++) input to one Dual-Mode DisplayPort (DP++) sink output or one HDMI/DVI sink output. The HDMI/DVI output has a built-in level translator compliant with DVI 1.0 and HDMI 1.4b standard TMDS signaling, and is specified up to a maximum data rate of 3.4 Gbps, supporting resolutions greater than 1920 X 1440 and HDTV deep color at 1080p. An integrated DP-HDMI Adaptor ID buffer can be accessed when the HDMI/DVI sink is selected to indicate support for HDMI signaling. The device compensates for PCB-related frequency loss and switching-related loss to provide the optimum electrical performance from source to sink. The DP++ Main Link signal inputs feature-configurable equalizers with selectable boost settings. At the SN75DP126 DP++ Main Link output, four primary levels of differential output voltage (VOD) swing and four primary levels of pre-emphasis are available as well as a secondary level of boost adjustment, programmed through I2C, for fine-tuning the Main Link output. The device can monitor the AUX channel and automatically adjust output signaling levels and input equalizers based on DP Link Training commands. At the SN75DP126 HDMI/DVI output, the differential output voltage swing and pre-emphasis levels are configurable. The SN75DP126 output signal conditioning and EQ parameters are programmable through the I2C interface, the VSadj terminal, and the I2C_CTL_EN terminal. The HDMI/DVI sink TMDS output slew rate is controlled by the SRC control input. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DisplayPort is a trademark of VESA Standards Association. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated SN75DP126 SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The SN75DP126 offers separate AUX and DDC source interfaces that connect to the DisplayPort AUX sink channel and the HDMI DDC sink channel, that seamlessly interface to graphics processor (GPU) comprising separate DDC and AUX interfaces as well as GPUs with combined DDC/AUX. Other sideband circuits such as Hot Plug Detect (HPD) are optimized to reduce external components providing a seamless connection to Intel, AMD, and NVIDIA graphics processors. The SN75DP126 is optimized for mobile applications, and contains activity-detection circuitry on the DP++ Main Link input that transitions to a low-power Output Disable mode in the absence of a valid input signal. Other low power modes are supported, including a Standby mode with typical dissipation of ~2 mW when no video sink (for example, monitor) is connected. The device is characterized for an extended operational temperature range from 0°C to 85°C. TYPICAL IMPLEMENTATIONS The SN75DP126 supports graphics processors with unified AUX/DDC configurations, where the source AUX channel is multiplexed with the source DDC channel, as illustrated in Figure 1. Graphics processors with separate AUX and DDC channels (ie. non-unified) are also supported, where the separate channels are directly routed to the separate channels on the SN75DP126, maintaining the AC coupling on the AUX channel. In the non-unified configuration, it is recommended to implement 2-kΩ pull-up resistors on the source-side DDC channel. See Figure 2. SN75DP126 4 diff DP_OUT[3:0] DP Connector GPU w/ Unified DDC & AUX Channels DP_HPD_SNK GPU 4 diff CAD_SNK IN[3:0] MAIN[3:0] HPD HPD_SRC CAD CAD_SRC AUX_SNK 1M 3.3V 2kW 100kW 2kW 100kW 3.3V DDC AUX_SRCp AUX_SRCn AUX 100kWresistors shall be placed on the AUX_SNK side to ensure proper device internal channel biasing, and to ensure the sink device identifies the source during power down conditions. 4 diff 3.3V RI2C HDMI (or DVI) Connector SCL_SRC SDA_SRC TMDS_OUT[2:0] RI2C TMDS_CLK 2 IC SCL_CTL SDA_CTL Optional I2C interface may be used to fully configure output signal conditioning and EQ settings. 10kW resistors are recommended for RI2C. SCL_SNK SDA_SNK Figure 1. GPU with a Unified AUX/DDC Configuration 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 SN75DP126 www.ti.com SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 SN75DP126 4 diff DP_OUT[3:0] DP Connector GPU w/ Separate DDC & AUX Channels DP_HPD_SNK GPU MAIN[3:0] 4 diff CAD_SNK IN[3:0] HPD HPD_SRC CAD CAD_SRC AUX_SNK 1M 3.3V 100kΩ 2kΩ DDC SCL_SRC SDA_SRC AUX AUX_SRCp AUX_SRCn 3.3V 100kΩ resistors shall be placed on the AUX_SNK side to ensure proper device internal channel biasing, and to ensure the sink device identifies the source during power down conditions. 4 diff 3.3V RI 2C 100kΩ TMDS_OUT[2:0] RI2C HDMI (or DVI) Connector 2kΩ TMDS_CLK 2 IC SCL_CTL SDA_CTL Optional I2 C interface may be used to fully configure output signal conditioning and EQ settings. 10kΩ resistors are recommended for RI 2C. SCL_SNK SDA_SNK Figure 2. GPU with Separate DDC and AUX Channels Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 3 SN75DP126 SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com BLOCK DIAGRAM CAD_SNK CADin CAD_SRC CADout HPD_SRC HPDout MLOUT_Select HPDAin DP_HPD_SNK HPDBin TMDS_HPD_SNK AMPL 130kW VIterm 50W 50W 130kW EQ DP_OUT[3:0]p IN0p DP++ Drivers EQ IN0n DP_OUT[3:0]n TMDS_CLKp EQ VIterm 50W TMDS Driver 1:2 Mux TMDS_CLKn EQ 50W TMDS_OUT[2:0]p IN3p TMDS Drivers EQ TMDS_OUT[2:0]n CADin HPDAin HPDBin IN3n SCL_CTL/EQ SDA_CTL/PRE VSadj PRE_EMPH OE SRC SRC MLOUT_Select EQ Local I2C VCC VREG VDD_DREG OE I2C_CTL_EN CTRL HDMI_EN# CADout HPDout VDD applies to the Dual-supply “DS” package PRIORITY GND Training Logic VDD or VDD_DREG AMPL PRE_EMPH ctrl_inB ctrl_outA ctrl_outB ctrl_inA 150kW EN ctrl_outA ctrl_inA AUX_SRCp AUX_SNKp AUX_SNKn AUX_SRCn vcc RDDC CADout ctrl_inB RDDC SCL_SRC SDA_SRC 4 VDD OVS DP-HDMI Adaptor ID SCL_SNK (DDC 80h/81h) SDA_SNK ctrl_outB Submit Documentation Feedback ctrl_outB Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 SN75DP126 www.ti.com SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 TMDS_CLKn TMDS_OUT0n TMDS_CLKp VCC TMDS_OUT0p T TMDS_OUT1p TMDS_OUT1n NC TMDS_OUT2p T T MDS_OUT2n DP_OUT3p DP_OUT3n DP_OUT2p DP_OUT2n 27 50 51 NC OVS HDMI_EN# 53 26 SN75DP126SS 52 25 24 (Top View) 54 23 22 55 7 8 9 21 10 11 12 13 14 15 16 17 18 19 20 AUX_SRCp AUX_SRCn HPD_SRC 6 SCL_SRC SDA_SRC DA_SRC 5 IN3n VCC 4 IN2n IN3p 3 IN1n NC IN2p 2 IN0n IN1p I2C_CTL_EN 56 1 SCL_SNK SDA_SNK EN TMDS_HPD_SNK NC VDD_DREG CAD_SNK CAD_SRC PRIORITY SRC DP_HPD_SNK VSadj DP_OUT1p DP_OUT1n VCC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 49 SCL_CTL/EQ SDA_CTL/PRE VCC IN0p AUX_SNKp AUX_SNKn DP_OUT0p DP_OUT0n NC TERMINAL ASSIGNMENTS TMDS_CLKn TMDS_OUT0n TMDS_CLKp VDD TMDS_OUT0p TMDS_OUT1p TMDS_OUT1n NC TMDS_OUT2p T MDS_OUT2n DP_OUT3p DP_OUT3n U DP_OUT2p DP_OUT2n 27 50 51 NC OVS HDMI_EN# 53 26 SN75DP126DS 52 25 24 (Top View) (Top View) 54 23 22 55 8 9 21 10 11 12 13 14 15 16 17 18 19 20 AUX_SRCp AUX_SRCn HPD_SRC 7 SCL_SRC SDA_SRC 6 IN3n VDD 5 IN2n IN3p 4 IN1n NC IN2p 3 IN0n IN1p 2 VCC IN0p I2C_CTL_EN 56 1 SCL_SNK SDA_SNK EN TMDS_HPD_SNK NC VDD_DREG CAD_SNK CAD_SRC PRIORITY SRC DP_HPD_SNK VSadj DP_OUT1p DP_OUT1n VDD 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 49 SCL_CTL/EQ SDA_CTL/PRE AUX_SNKp AUX_SNKn DP_OUT0p DP_OUT0n NC Figure 3. SN75DP126SS Single Supply Figure 4. SN75DP126DS Dual Supply Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 5 SN75DP126 SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com PIN FUNCTIONS PIN SIGNAL NO. I/O DESCRIPTION DISPLAYPORT AND HDMI MAIN LINK TERMINALS IN0p, IN0n 5, 6 IN1p, IN1n 7, 8 DisplayPort Main Link Lane 0 Differential Input IN2p, IN2n 10, 11 IN3p, IN3n 12, 13 DisplayPort Main Link Lane 3 Differential Input DP_OUT0p, DP_OUT0n 47, 46 DisplayPort Main Link Lane 0 Differential Output DP_OUT1p, DP_OUT1n 45, 44 DP_OUT2p, DP_OUT2n 42, 41 DP_OUT3p, DP_OUT3n 40, 39 DisplayPort Main Link Lane 3 Differential Output TMDS_CLKp, TMDS_CLKn 30, 29 HDMI/DVI Clock TMDS Differential Output TMDS_OUT0p, TMDS_OUT0n 32, 31 TMDS_OUT1p, TMDS_OUT1n 35, 34 TMDS_OUT2p, TMDS_OUT2n 37, 36 100Ω Differential Input 100Ω Differential Output 100Ω Differential Output (Failsafe) DisplayPort Main Link Lane 1 Differential Input DisplayPort Main Link Lane 2 Differential Input DisplayPort Main Link Lane 1 Differential Output DisplayPort Main Link Lane 2 Differential Output HDMI/DVI Data Lane 0 TMDS Differential Output HDMI/DVI Data Lane 1 TMDS Differential Output HDMI/DVI Data Lane 2 TMDS Differential Output AUX CHANNEL AND DDC DATA TERMINALS AUX_SRCp, AUX_SRCn 17, 18 AUX_SNKp, AUX_SNKn 49, 50 SCL_SRC, SDA_SRC 15, 16 SCL_SNK, SDA_SNK 28, 27 Source Side Bidirectional DisplayPort Auxiliary Data Channel. These signals are connected to the AUX_SNK channel when the DisplayPort sink is selected; AC coupling should be implemented. Sink Side Bidirectional DisplayPort Auxiliary Data Channel. I/O (Failsafe) Source Side Bidirectional I2C Display Data Channel (DDC) for TMDS modes. These terminals include integrated 60 kΩ pull-up resistors. HDMI/DVI Sink Side Bidirectional I2C Display Data Channel (DDC). HOT PLUG DETECT AND CAD TERMINALS Hot Plug Detect Output to the Source. HPD_SRC 19 Output CAD_SRC 52 TMDS_HPD_SNK 25 CAD_SNK 22 6 Source Side Cable Adapter Detect Output. When the DisplayPort sink is selected, this output represents the condition of the CAD_SNK input, active high as default; polarity may be programmed through the local I2C interface. When the HDMI/DVI sink is selected, this output is driven high. 21 DP_HPD_SNK This output shall be driven high when the source shall be connected to either the HDMI/DVI sink or the DisplayPort sink, and driven low when no sink is selected. This output will be asserted for a fixed period of time during active (PRIORITY based) transition from one sink to the other. Input (Failsafe) DisplayPort Hot Plug Detect Input from Sink. This device input is 5-V tolerant, and includes an integrated 130 kΩ pull-down resistor. Note: pull this input high during compliance testing or use I2C control interface to go into compliance test mode and control DP_HPD_SNK and HPD_SRC by software. HDMI/DVI Hot Plug Detect Input from Sink. This device input is 5-V tolerant, and includes an integrated 130 kΩ pull-down resistor. Input DisplayPort Cable Adapter Detect Input. An external 1MΩ resistor to GND is recommended. This terminal is used to select DP mode (low input) or TMDS mode (high input) when the DisplayPort sink is selected . Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 SN75DP126 www.ti.com SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 PIN FUNCTIONS (continued) PIN SIGNAL NO. I/O DESCRIPTION CONTROL TERMINALS VSadj 56 HDMI_EN# 55 PRIORITY HDMI/DVI Sink Differential Voltage Swing Control. An external resistor connecting this pin to GND determines the output voltage swing. A value of 4.7 kΩ is recommended to provide a typical swing of 1000 mV. VSadj resistor values of 4.7 kΩ ± 1 kΩ control the output voltage swing in a near-linear function of approximately 2 mV/100 Ω. Note: this input does not impact the output when a DisplayPort sink is selected and operating in TMDS mode (as supported by the DP++ source) Input HDMI/DVI Sink Type Control. When this input is low, the output is HDMI 1.4b compliant when the HDMI/DVI sink is selected. When this input is high, the output is DVI 1.0 compliant when the HDMI/DVI sink is selected. Output Select Priority. Selects the priority for the output in the case both DP_HPD_SNK and TMDS_HPD_SNK are high indicating two sinks are connected. When low, the DisplayPort sink has priority selection. When high, the HDMI/DVI sink has priority. Note: An external RC circuit should be connected to the PRIORITY pin to insure that the SN76DP126 functions properly with some non-compliant monitors. See the SN75DP126 Reference Schematics for more information. 20 TMDS Slew Rate Control. When the HDMI/DVI sink is selected, the slew rate is controlled by the HDMI_EN# input and by the SRC control input: VIL = TMDS rise and fall times meet tT1 specifications SRC 51 3-Level Input VIM (between VIL and VIH) = TMDS rise and fall times meet tT2 specifications (Recommended setting) VIH = TMDS rise and fall times meet tT3 specifications Note: this input does not impact the output when a DisplayPort sink is selected and operating in TMDS mode (as supported by the DP++ source) Source Side DDC Input/Output Buffer Control Input. When the HDMI/DVI sink is selected, the DDC VOL and VIL is controlled by the OVS control input: OVS 54 3-Level Input VIL = Source DDC interface meets VOL(3) and VIL(3) specifications VIM (between VIL and VIH) = Source DDC interface meets VOL(2) and VIL(2) specifications VIH = Source DDC interface meets VOL(1) and VIL(1) specifications I2C_CTL_EN 1 3-Level Input SCL_CTL/EQ 2 3-Level Input (Failsafe) Local I2C Interface Enable Control and Target Address Select. When low, the local I2C interface is disabled; when input is between VIL and VIH levels, the local I2C interface is enabled and is addressed at 0x58h (Write) and 0x59h (Read); when input is high, the local I2C interface is enabled and is addressed at 0x5Ah (Write) and 0x5Bh (Read). Local I2C Interface Clock, or Equalizer Setting Control Input. When I2C_CTL_EN is input high or floating, this terminal is the local I2C interface clock used to configure SN75DP126. When I2C_CTL_EN is low, this terminal can be used to configure the input EQ. Local I2C Interface Data, or TMDS Pre-emphasis Control Input. When I2C_CTL_EN is input high or floating, this terminal is the local I2C interface data signal. When I2C_CTL_EN is low, this terminal configures the HDMI/DVI sink TMDS output pre-emphasis as: SDA_CTL/PRE 3 I/O 3-Level Input (Failsafe) VIL = 0 dB pre-emphasis applied to TMDS output VIM = Not Recommended VIH = 2 dB pre-emphasis applied to TMDS output When 2 dB pre-emphasis is enabled, the steady state TMDS output swing is reduced from that selected by VSadj, and the transition time is reduced from that selected by SRC. Note: this input does not impact the output when a DisplayPort sink is selected and operating in TMDS mode (as supported by the DP++ source), whereas no pre-emphasis is applied to the output signal in this condition. Device Enable / Reset (Power Down). This input incorporates internal pullup of 150 kΩ, and only 1.2-V tolerant (the high level shall be limited to 1.2 V). EN 26 When high, the device is enabled for normal operation. Low-Voltage When low, the device is in power down mode; all outputs excluding HPD_SRC and CAD_SRC are highInput impedance, and inputs excluding DP_HPD_SNK, TMDS_HPD_SNK, and CAD_SNK are ignored; all local I2C (Failsafe) and DPCD registers are reset to their default values when this input is low. At power up, the EN input must not be de-asserted until the VCC supply has reached at least the minimum recommended supply voltage level. SUPPLY AND GROUND TERMINALS VCC VDD SN75DP126SS 4, 14, 33, 43 SN75DP126DS 4 SN75DP126DS 14, 33, 43 3.3-V Supply 1.05-V Supply Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 7 SN75DP126 SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com PIN FUNCTIONS (continued) PIN SIGNAL I/O NO. DESCRIPTION SN75DP126SS: Digital voltage regulator decoupling; install 1uF to GND. VDD_DREG 23 GND SN75DP126DS: Treat same as VDD; this pin will be most noisy of all VDD terminals and needs a de-coupling capacitor nearby. Exposed Thermal Pad NC 9, 53, 38, 48, 24 Ground. Reference GND connection shall be made to the exposed thermal pad. No connect. These terminals may be left unconnected, or connect to GND. ORDERING INFORMATION (1) (1) PART NUMBER PART MARKING PACKAGE SN75DP126DSRHUR DP126DS 56-pin QFN Reel SN75DP126SSRHUR DP126SS 56-pin QFN Reel For the most current package and ordering information, see Packet Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Supply voltage range Voltage range VALUE UNIT VCC –0.3 to 4.0 V VDD, VDD_DREG –0.3 to 1.3 V Main Link I/O Differential Voltage –0.3 to 1.4 V DP_HPD_SNK, TMDS_HPD_SNK, SCL_SNK, SDA_SNK –0.3 to 5.5 V EN –0.3 to 1.3 V All Other Terminals –0.3 to 4.0 V ±2 kV ±1000 V Human Body Model Electrostatic discharge (2) All Terminals Charged-device model (1) (2) (3) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Tested in accordance with JEDEC Standard 22, Test Method A114-B Tested in accordance with JEDEC Standard 22, Test Method C101-A THERMAL INFORMATION THERMAL METRIC (1) RHU (QFN-56) θJA Junction-to-ambient thermal resistance 35 θJCtop Junction-to-case (top) thermal resistance 25 θJB Junction-to-board thermal resistance 15 ψJT Junction-to-top characterization parameter 2 ψJB Junction-to-board characterization parameter 10 θJCbot Junction-to-case (bottom) thermal resistance 8 (1) 8 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 SN75DP126 www.ti.com SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN VCC Supply voltage VDD Digital core and Main Link supply voltage TA Operating free-air temperature TS Storage temperature TCASE Case temperature NOM MAX 3 3.3 3.6 1.0 1.05 1.2 V 0 85 °C -65 150 °C 97.1 UNIT V °C DP++ MAIN LINK TERMINALS VID Peak-to-peak input differential voltage; RBR, HBR, HBR2 0.3 1.40 dR(DP) Data rate; DisplayPort sink 5.4 dR(HDMI) Data rate; HDMI sink 3.4 CAC AC coupling capacitance (each DP input and each DP output line) 75 Rtdiff Differential output termination resistance; DisplayPort sink and HDMI sink 80 VOterm Output termination voltage (AC coupled) tSK(HBR2) Intra-pair skew at the input at 5.4 Gbps 20 ps tSK(HBR) Intra-pair skew at the input at 2.7 Gbps 100 ps tSK(RBR) Intra-pair skew at the input at 1.62 Gbps 300 ps 100 0 Vpp Gbps Gbps 200 nF 120 Ω 2 V AUX CHANNEL DATA TERMINALS VI-DC DC Input Voltage, AUX_SRCp/n and AUX_SNKp/n (DP and TMDS modes) -0.5 VID Differential input voltage amplitude (DP mode only) 300 dR(AUX) Data rate (before Manchester encoding) 0.8 dR(FAUX) Data rate Fast AUX (300ppm frequency tolerance) tjccin_adj Cycle-to-cycle AUX input jitter adjacent cycle (DP mode only) tjccin Cycle-to-cycle AUX input jitter within one cycle (DP mode only) CAC AUX AC coupling capacitance 3.6 1 V 1400 mVPP 1.2 Mbps 720 Mbps 0.05 UI 0.1 UI 75 200 nF DP_HPD_SNK, TMDS_HPD_SNK, SCL/SDA_SNK –0.3 5.5 V All other DDC, local I2C, and control terminals –0.3 3.6 DDC, LOCAL I2C, AND CONTROL TERMINALS VI-DC VIH DC Input Voltage High-level input voltage SCL/SDA_SRC 2.1 2 All other DDC, Local I C, and control terminals VIL Low-level input voltage (1) VIM Mid-level input voltage (2) dR Data rate VTH(EN) EN input threshold voltage fSCL SCL clock frequency standard I2C mode tw(L) SCL clock low period standard I2C mode VCC–0.5 0.5 VCC/2–0.3 V VCC/2+0.3 100 280 kbps 800 100 SCL clock high period standard I C mode Cbus Total capacitive load for each bus line (DDC and local I2C terminals) mV kHz μs 4.7 2 tw(H) (1) (2) V μs 4.0 400 pF VIL for SCL_SRC and SDA_SRC are listed in the AUX/DDC/I2C Electrical Characteristics Table. VIM is only applicable for 3-Level control pins. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 9 SN75DP126 SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com POWER SUPPLY ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER (1) TEST CONDITIONS MIN TYP MAX UNIT 138 242 mA 73 125 mA 42 70 mA 130 160 mA 4 DP Lanes; DP Sink Maximum Conditions: DP at 5.4-Gbps PRBS, VOD = 510 mVpp, PRE = 6 dB; AUX at 1-Mbps PRBS, VID = 1000 mVpp; EQ = 6 dB Typical Conditions: DP at 5.4-Gbps PRBS, VOD = 510 mVpp, PRE = 0 dB AUX and I2C Idle; EQ = 3 dB 2 DP Lanes; DP Sink Maximum Conditions: DP at 5.4-Gbps PRBS, VOD = 510 mVpp, PRE = 6 dB; AUX at 1-Mbps PRBS, VID = 1000 mVpp; EQ = 6 dB Typical Conditions: DP at 5.4-Gbps PRBS, VOD = 510 mVpp, Device current under normal operation ICC PRE = 0 dB AUX and I2C Idle; EQ = 3 dB 1 DP Lanes; DP Sink Maximum Conditions: DP at 5.4-Gbps PRBS, VOD = 510 mVpp, PRE = 6 dB; AUX at 1-Mbps PRBS, VID = 1000 mVpp; EQ = 6 dB Typical Conditions: DP at 5.4-Gbps PRBS, VOD = 510 mVpp, PRE = 0 dB AUX and I2C Idle; EQ = 3 dB 4 DP Lanes; HDMI Sink Maximum Conditions: TMDS at 3.4 Gbps, VOD = 1200 mVpp, VID = 1000 mVpp Typical Conditions: TMDS at 3.4 Gbps, VOD = 1000 mVpp, DDC and I2C Idle ISD Shutdown mode current 4 DP Lanes 0.55 4.00 mA ISBY Standby mode current 4 DP Lanes. 0.85 4.00 mA ID3 D3 power down mode current 4 DP Lanes. 10 15 mA IOD Output disable (squelch) mode 4 DP Lanes. current 53 75 mA (1) Values are VCC supply measurements for SN75DP126SS and VDD supply measurements for the SN75DP126DS; the maximum VCC supply measurement for the SN75DP126DS is 8 mA during normal operation and 0.5 mA during shutdown, standby, and D3 power down modes. MAIN LINK INPUT ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP See Table 4 for EQ setting details; Max value represents the typical value for the maximum configurable EQ setting AEQ(HBR) Equalizer gain for RBR/HBR AEQ(HBR2) Equalizer gain for HBR2 AEQ(TMDS_D) Equalizer gain for DP sink in TMDS mode; data lanes AEQ(TMDS_C) MAX UNIT 9 dB 18 dB 9 dB Equalizer gain for DP sink in TMDS mode; clock lane 3 dB AEQ(HDMI_D) EQ gain, HDMI sink; data lanes 9 dB AEQ(HDMI_C) EQ gain, HDMI sink; clock lane 3 dB RIN Input termination impedance 60 Ω VIterm Input termination voltage 2 V 40 AC coupled; self-biased 0 SQUELCH_SENSITIVITY = 00 VSQUELCH 10 Squelch threshold voltage 50 60 SQUELCH_SENSITIVITY = 01 (default) 115 SQUELCH_SENSITIVITY = 10 160 SQUELCH_SENSITIVITY = 11 200 Submit Documentation Feedback mVPP Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 SN75DP126 www.ti.com SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 DISPLAYPORT MAIN LINK OUTPUT ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VOD(L0) VOD(L1) VOD(L2) Output Differential Voltage Swing VPRE(L0); 675 Mbps D10.2 Test Pattern; BOOST = 01; 100-Ω Rtdiff Termination VOD(L3) VOD(TMDS) 675 Mbps D10.2 Test Pattern; BOOST = 01 ΔVOD(L0L1) ΔVOD(L1L2) Output Peak-to-Peak Differential Voltage Delta ΔVODn = 20 × log(VODL(n+1) / VODL(n)) Per PHY_CTS section 3.2 at TP2 ΔVOD(L2L3) VPRE(L0) MIN TYP MAX 238 340 442 357 510 663 484 690 897 700 1000 1300 420 600 780 1.7 3.5 5.3 1.6 2.5 3.5 0.8 3.5 6.0 0 0.25 All VOD options; Any BOOST setting VPRE(L1) Driver output pre-emphasis VPRE(L2) VPRE(L3) VOD = VOD(L0), VOD(L1), or VOD(L2); BOOST = 01 3.5 VOD = VOD(L0) or VOD(L1); BOOST = 01 6.0 VOD = VOD(L0); BOOST = 01 VPRE(BOOST) Output VPRE Boost mVPP dB dB 9.5 BOOST = 10 +15 BOOST = 00 –15 ΔVPRE(L1L0) ΔVPRE(L2L1) UNIT %dB 2.0 Pre-emphasis Delta Per PHY_CTS section 3.3 at TP2 1.6 ΔVPRE(L3L2) dB 1.6 ΔVConsBit Non-transition bit voltage variation ROUT Driver output impedance VOCM(SS) Steady state output common mode voltage VOCM(PP) Output common mode noise IOS Short circuit current limit Per PHY_CTS section 3.3.5 40 50 0 Per PHY_CTS section 3.10 RBR, HBR 20 HBR2 30 Main Link outputs shorted to GND 30 %V 60 Ω 2 V mVRMS 50 mA DISPLAYPORT MAIN LINK OUTPUT SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER tPD Propagation delay time tSK1 Intra-pair output skew tSK2 Inter-pair output skew TEST CONDITIONS MIN TYP MAX 350 Signal input skew = 0 ps; dR = 2.7 Gbps, VPRE = 0 dB, 800 mVpp , D10.2 clock pattern at device input; see Figure 6 Δtjit Total peak to peak residual jitter VOD(L0); VPRE(L0); EQ = 8 dB; clean source; minimum input and output cabling; 1.62 Gbps, 2.7 Gbps, and 5.4-Gbps PRBS7 data pattern. tsq_enter Squelch Entry Time Time from active DP signal turned off to ML output off with noise floor minimized tsq_exit Squelch Exit Time Time from DP signal on to ML output on ps 20 ps 70 ps 15 ps 10 120 μs 0 1 μs Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 UNIT 11 SN75DP126 SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com Vlterm 0V to2V 50Ω 50Ω 50Ω 50Ω D+ Rx VD+ VID Tx D- Y VY Z VD- VZ VOD = VY - VZ VOCM = (VY + VZ) 2 VID = VD+ - VDVICM = (VD+ + VD-) 2 Figure 5. DisplayPort Sink Main Link Test Circuit tOUTxp(f) tOUTxn(r) tOUTxn(f) tOUTxp(r) DP_OUTxp 50% DP_OUTxn tSK1 = 0.5 x | (tOUTxp(r) -tOUTxn(f)) + (tOUTxp(f) -tOUTxn(r)) | DP_OUTyp tSK2 DP_OUTyn Figure 6. DisplayPort Sink Main Link Skew Measurements HDMI/DVI MAIN LINK OUTPUT ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER VOH TEST CONDITIONS Single-end high level output voltage VSadj = 4.7 kΩ VOL Single-end low level output voltage VSadj = 4.7 kΩ VSWING Single-end output voltage swing VSadj = 4.7 kΩ; SDA_CTL/PRE ≤ VIL ΔVSWING Change in single-end output voltage swing per 100Ω ΔVSadj VOCM(SS) Steady state output common mode voltage ΔVOCM(SS) Change in steady state output common mode voltage between logic levels VOD(PP) Peak-to-peak output differential voltage VOD(SS) Steady state output differential voltage IOS Short circuit current limit 12 MIN TYP MAX VCC –10 VCC +10 mV VCC –600 VCC –400 mV 400 600 mV 20 VSadj = 4.7 kΩ; SDA_CTL/PRE ≤ VIL VCC -200 mV –5 5 mV 800 1200 640 VSadj = 4.7 kΩ; SDA_CTL/PRE ≤ VIL 1000 VSadj = 4.7 kΩ; SDA_CTL/PRE ≥ VIH 630 Submit Documentation Feedback mV VCC –300 VSadj = 4.7 kΩ; SDA_CTL/PRE ≥ VIH VID = 500 mV UNIT mVPP mVPP 15 mA Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 SN75DP126 www.ti.com SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 HDMI/DVI MAIN LINK SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) MAX UNIT tPLH Propagation delay time (low to high) PARAMETER TEST CONDITIONS 250 600 ps tPHL Propagation delay time (high to low) 250 800 ps 75 140 SRC at VIM; SDA_CTL/PRE ≤ VIL; 340 MHz 85 160 SRC ≥ VIH; SDA_CTL/PRE ≤ VIL; 340 MHz 100 200 SRC ≤ VIL; SDA_CTL/PRE ≤ VIL; 340 MHz tT1 tT2 Transition time (rise and fall time); measured at 20% and 80% levels tT3 MIN TYP ps tSK1(T) Intra-pair output skew 0.15tbit ps tSK2(T) Inter-pair output skew 30 ps ΔtJIT Total peak to peak residual jitter; clock and data lanes 30 ps tsq_enter Squelch Entry Time tsq_exit Squelch Exit Time SRC at VIM; dR = 3.4 Gbps; 0 dB VPRE; EQ = 13 dB dR = 3.4 Gbps tSK1(T) 10 120 0 1 μs tSK1(T) DP_OUTxp 50% DP_OUTxn tSK2(T) DP_OUTyp DP_OUTyn Figure 7. HDMI/DVI Sink TMDS Output Skew Measurements VOC DVOC(SS) Figure 8. HDMI/DVI TMDS Output Common Mode Measurement Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 13 SN75DP126 SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com (1) The FR4 trace between TTP1 and TTP2 is designed to emulate 1-8” of FR4, AC coupling cap and connector. Trace width –4 mils. (2) All Jitter is measured at a BER of 10-9 (3) Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP1 (4) VCC = 3.3 V (5) RT = 50Ω (6) The input signal from parallel Bert does not have any pre-emphasis. Refer to recommended operating conditions. Figure 9. HDMI/DVI TMDS Output Jitter Measurement HPD/CAD/EN ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN HPD_SNK, CAD_SNK 2.1 EN 0.8 TYP MAX UNIT VIH High-level input voltage VIL Low-level input voltage VOH High-level output voltage IOH = 500 µA; HPD_SRC, CAD_SRC 2.7 3.6 V VOL Low-level output voltage IOH = 500 µA; HPD_SRC, CAD_SRC 0 0.1 V RoutCAD CAD series output resistance (1) DP_HPD_SNK = CAD_SNK = VCC 150 RoutHPD HPD series output resistance DP_HPD_SNK = TMDS_HPD_SNK = VCC 150 ILEAK IH_HPD IH_CAD IL_HPD IL_CAD Failsafe condition leakage current V HPD_SNK, CAD_SNK 1.08 EN 0.285 V Ω Ω VCC = 0 V; V(pin) = 1.2 V; EN 20 VCC = 0 V; V(pin) = 3.3 V; DP_HPD_SNK, TMDS_HPD_SNK 40 High level input current Device powered; VIH = 1.9 V; IH_HPD includes RpdHPD resistor current 30 Low level input current Device powered; VIL = 0.8 V; IL_HPD includes RpdHPD resistor current 30 1 1 μA μA μA RpdHPD HPD input termination to GND; V =0V DP_HPD_SNK and TMDS_HPD_SNK CC 100 130 160 kΩ REN EN terminal pull-up resistor 120 150 180 kΩ 14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 SN75DP126 www.ti.com SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 HPD/CAD SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tPD(HPD) Propagation delay DP/TMDS_HPD_SNK to HPD_SRC; rising edge and falling edge See Figure 11; not valid during switching time tS(HPD) tPD(CAD) Propagation delay CAD_SNK to CAD_SRC; rising edge and falling edge tSK(HPD_CAD) MIN TYP MAX UNIT 120 ns See Figure 14 50 ns Output skew HPD_SRC to CAD_SRC when HDMI/DVI sink is selected; rising edge and falling edge See Figure 14 50 ns tT(HPD1) HPD logic switch time See Figure 12 tT(HPD2) HPD logic switch pause time tT(HPD3) HPD logical disconnect timeout x_HPD_SNK 350 ms See Figure 12 4.1 ms See Figure 13 350 ms HPD_SRC TP TP 130 kW 100 kW SN75DP126 Figure 10. HPD Test Circuit VCC x_HPD_SNK 50% 0V tPD(HPD) HPD_SRC VCC 50% 0V Figure 11. HPD Timing Diagram #1 Figure 12. HPD Timing Diagram #2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 15 SN75DP126 SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com x_HPD _SNK VCC 50% 0V HPD Logical Disconnect Timeout tT(HPD3) HPD _SRC VOH 50% V OL Logically Disconnected Device Logically Connected Figure 13. HPD Logic Disconnect Timeout SINK_PORT_SELECT = 00 PRIORITY CAD_SNK DP_HPD_SNK tPD(HPD) TMDS_HPD_SNK HPD_SRC tT(HPD1) tPD(HPD) tSK(HPD_CAD) tPD(CAD) CAD_SRC Hi-Z DP Main Link Valid Display Port Signal Data Valid TMDS Signal Data Hi-Z Valid HDMI/DVI (TMDS) Data TMDS Main Link Figure 14. HPD and CAD Logic Description and Timing Diagram 16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 SN75DP126 www.ti.com SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 AUX/DDC/I2C ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER CIO TEST CONDITIONS MIN TYP MAX I/O capacitance VIO = 0 V; f(test) = 1 MHz On resistance AUX_SRCn to AUX_SNKn in DP mode VCC = 3.0 V w/ VI = 2.6 V or VCC = 3.6 V w/ VI = 3.4 V; IO = 5 mA 10 Ω On resistance AUX_SRCp to AUX_SNKp in DP mode VCC = 3.0 V w/ VI = 0.3 V or VCC = 3.6 V w/ VI = 0.4 V; IO = 500 mA 10 Ω On resistance SCL/SDA_SRC to AUX_SNK in TMDS mode VI = 0.4 V; IO = 3 mA 30 Ω ΔrON On resistance variation with input signal voltage change in DP mode VCC = 3.6 V, IO = 5 mA, VI = 2.6 V to 3.4 V VCC = 3.0 V, IO = 5 mA, VI = 0 V to 0.4 V 5 Ω VID(HYS) Differential input hysteresis By design (simulation only) rON ILEAK Failsafe condition leakage current 10 UNIT 50 AUX/DDC High level input current C IH_I2C I2C High level input current IL_AUX AUX Low level input current IL_I2C I2C Low level input current IL_DDCSR DDC Low level input current mV VCC = 0 V; V(pin) = 3.3 V; SCL/SDA_SNK 40 VCC = 0 V; V(pin) = 3.3 V; AUX_SNK p/n 20 VCC = 0 V; V(pin) = 3.3 V; SCL_CTL/EQ, SDA_CTL/PRE, AUX_SRCp 5 VCC = 0 V; V(pin) = 3.3 V; AUX_SRCn, SCL/SDA_SRC IH_AUX_DD pF μA 60 5 Device powered; VI = VCC μA 20 5 Device powered; VI = GND ; IL_DDCSRC includes RDDC resistor current 40 μA 80 C VAUX+ AUX_SNKp voltage Per PHY_CTS section 3.19 0 0.4 V VAUX– AUX_SNKn voltage Per PHY_CTS section 3.18 2.4 3.6 V S1122 AC coupled AUX line insertion loss VID = 400 mV, 360 MHz sine wave 3 dB RDDC Switchable pullup resistor on DDC at source side (SCL_DDC, SDA_DDC) CAD_SNK = VIH 72 kΩ VIL1 VIL2 SCL/SDA_SRC low-level input voltage 48 60 OVS ≥ VIH 0.4 OVS at VIM 0.4 VIL3 OVS ≤ VIL 0.3 VOL1 OVS ≥ VIH 0.6 0.7 VOL2 OVS at VIM 0.5 0.6 VOL3 SCL/SDA_SRC low-level output voltage OVS ≤ VIL 0.4 0.5 VOL4 SCL/SDA_SNK and SCL/SDA_CTL lowIO = 3 mA level output voltage 0.4 V V V AUX/DDC/I2C SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP UNIT 400 ps 3 ns 3 ns AUX intra-pair skew tPLH(AUX) AUX propagation delay, low to high tPHL(AUX) AUX propagation delay, high to low tPLH1(DDC) DDC propagation delay, low to high (1) Source to Sink; CAD_SNK ≥ VIH; 100-kbps pattern; DDC propagation delay, high to low (1) CL (Sink) = 400 pF; see Figure 17 360 ns 230 ns DDC propagation delay, low to high (1) Sink to Source; CAD_SNK ≥ VIH; 100-kbps pattern; DDC propagation delay, high to low (1) CL (Source) = 100 pF; see Figure 18 250 ns 200 ns tPHL1(DDC) tPLH2(DDC) tPHL2(DDC) (1) VID = 400 mV, see Figure 15 MAX tsk(AUX) CAD_SNK ≤ VIL; 1-Mbps pattern; see Figure 16 Applies to DDC pass through to DisplayPort sink and the HDMI/DVI sink. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 17 SN75DP126 SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com AUX/DDC/I2C SWITCHING CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER tPU(AUX) TEST CONDITIONS Main link D3 wakeup time MIN TYP MAX VID = 0.1 V, VICM = 2 V source side (before AC coupling caps) 50 UNIT µs 2 Local I C Refer to the I2C-Bus Specification, Version 2.1 (January 2000); SN75DP126 meets the switching characteristics for standard mode transfers up to 100 kbps. 2.2 V 2.2 V AUX Input 1.8 V 50% Differential AUX Input 0V tPHL(AUX) 1.8 V tPLH(AUX) tsk(AUX) Figure 15. AUX Skew Measurement Differential 0 V AUX Output Figure 16. AUX Delay Measurement 3.3 V SCL_SRC SDA_SRC Input VCC/2 VOL VIL 0V tPLH2 tPHL1 5V tPLH1 SCL_SNK SDA_SNK Output VCC/2 VOL4 0V Figure 17. DDC Propagation Delay – Source to Sink 18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 SN75DP126 www.ti.com SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 5V SCL_SNK SDA_SNK Input VCC/2 0V tPHL2 tPLH2 3.3 V SCL_SRC SDA_SRC Output VCC/2 VOL 0V Figure 18. DDC Propagation Delay – Sink to Source Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 19 SN75DP126 SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS Trace Length (inches) 2 6 10 14 18 22 2 6 10 14 18 22 Input Mode 10 8 DisplayPort HBR2 6 6 dB Setting Gain - Hz 4 2 0 10 dB Setting TMDS 3.4 Gbps 15 dB Setting -2 -4 Recommended Fixed EQ Setting 10dB 10dB 10dB 13dB 15dB 15dB 13dB 13dB 13dB 13dB 15dB 15dB -6 10M 100M 1G 10G Frequency - Hz Figure 19. Typical EQ Gain Curves (1) Figure 20. Characterization Test Board Trace Lengths vs. EQ Setting Gain represents SN75DP126 design simulation. VSadj Typical Curve 1.4 1.2 VOD (V) 1 0.8 0.6 0.4 0 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 0.2 VSadj (kΩ) Figure 21. VOD vs. VSadj 20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 SN75DP126 www.ti.com SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS (CONTINUED) Figure 22. Main Link Input with 22-inch Trace; DisplayPort Sink Figure 23. SN75DP126 Output; 22-inch Input Trace; 15 dB EQ Setting; DP Sink Figure 24. Main Link Input with 22-inch Trace; TMDS Sink Figure 25. SN75DP126 Output; 22-inch Input Trace; 15 dB EQ Setting; TMDS Sink Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 21 SN75DP126 SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com APPLICATION INFORMATION Operating Modes Overview EN=0 DP_HPD_SNK=0 for tT(HPD) EN=1 Shutdown Mode Standby Mode HPD_SRC=0 = tT(HPD1) D3 Power Down Mode DP_HPD_SNK=0 for tT(HPD1) “Enter D3” AUX cmd TMDS_HPD_SNK=0 for tT(HPD1) (and CAD_SNK=0) TMDS_HPD_SNK=1 for tT(HPD1) DP_HPD_SNK=1 for tT(HPD1) “Exit D3" AUX cmd (or CAD_SNK=1) (or DP_HPD_SNK=1 and PRIORITY=1) HDMI/DVI Active Mode DP_HPD_SNK=1 (transition if PRIORITY=0) (CAD_SRC=1) Squelch event TMDS_HPD_SNK=1 DisplayPort Active Mode (transition if PRIORITY=1) (CAD_SRC=CAD_SNK) Local I2C Selected (EN=1) Squelch release Squelch release Any DP State * invalid DPCD register entry Output Disable Mode Squelch event DPCD register corrected Compliance Test Mode * DP states include DisplayPort Active Mode, D3 Power Down Mode, and Compliance Test Mode Figure 26. SN75DP126 Operating Modes Flow Diagram 22 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 SN75DP126 www.ti.com SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 Table 1. Description of SN75DP126 Operating Modes MODE CHARACTERISTICS CONDITIONS Shutdown Mode Least amount of power consumption (most circuitry turned off); HPD_SRC output is asserted if either DP_HPD_SNK or TMDS_HPD_SNK are input active (high); all other outputs are high-impedance; all other inputs are ignored; the local I2C interface is inactive; in this state all local I2C registers and DPCD registers are set to default values. EN is low Standby Mode Main Link outputs are disabled; the local I2C interface is active; in this state, the HPD_SRC (and CAD_SRC) outputs are driven low for at least tT(HPD) to indicate no sink connectivity to the source; the SN75DP126 passes through this state when transitioning from one active sink to the other for reasons of PRIORITY selection, where the HPD_SRC de-assertion for at least tT(HPD) communicates the sink plug event to the source. EN is high; Either no sink is connected, or both sinks are connected and PRIORITY causes a transition from one sink to the other sink The DisplayPort sink is selected and data transfer is enabled (normal operation); the Main Link output is either TMDS mode (CAD_SNK = 1) or DisplayPort mode (CAD_SNK = 0). DisplayPort Active Mode D3 Power Down Mode In TMDS mode, the DDC source-side channel (SCL/SDA_SRC) is connected to the sink DDC channel (AUX_SNK p/n) through a low-resistance circuit; and the CAD_SRC output is driven high. In TMDS mode the output signal swing is 600 mVpp unless this setting is adjusted through local I2C interface programming; the Main Link input equalizer settings depend on device control inputs and local I2C settings. In DisplayPort mode the AUX source-side channel is connected to the sink AUX channel through a low-resistance circuit; and the CAD_SRC output is driven low. The AUX monitor is active for Link Training, which automatically updates the DPCD registers to enable the Main Link outputs (this Link Training operation may be de-activated and overridden by direct local I2C programming); transactions other than Link Training and D3 power management commands are ignored on the AUX interface; the Main Link output signal conditioning (pre-emphasis and VOD) and Main Link input equalizer settings depend on the Link Training, device control inputs, and local I2C settings. DisplayPort D3 low-power mode; DisplayPort sink Main Link outputs are disabled; local I2C interface is active; AUX monitor is active. EN is high; DP_HPD_SNK is high, but after entering this state, DP_HPD_SNK can be low for less than tT(HPD) (for example, sink interrupt request to source); If both TMDS_HPD_SNK and DP_HPD_SNK are high, then a low input on PRIORITY causes the DisplayPort sink selection EN is high; DisplayPort sink is selected, and operating in DisplayPort mode (CAD_SNK = 0); “Enter D3” AUX command has been performed The HDMI/DVI sink is selected and data transfer is enabled (normal operation); the HDMI/DVI Main Link output (TMDS signaling) is enabled. HDMI/DVI Active Mode The DDC source-side channel (SCL/SDA_SRC) is connected to the HDMI/DVI sink DDC channel (SCL/SDA_SNK) through an I2C buffer that separates the capacitive load between the source and sink; the DP-HDMI Adapter ID buffer containing a read-only phrase DP-HDMI ADAPTOR<EOT> converted to ASCII characters at DDC (I2C target) addresses 80h(Write)/81h(Read) per the VESA DisplayPort Interoperability Guidelines Version 1.1a EN is high; TMDS_HPD_SNK is high; If both TMDS_HPD_SNK and DP_HPD_SNK are high, then a high input on PRIORITY causes the HDMI/DVI sink selection The HDMI/DVI Main Link output signal conditioning (pre-emphasis and VOD) and Main Link input equalizer settings depend on the device control inputs and local I2C settings. Output Disable Mode When low-signal levels on the source Main Link input are sensed (a squelch event) when in either sink-side is selected for active mode, a transition to this state occurs and the sink-side Main Link outputs are disabled; when the source Main Link input signal levels are above a pre-determined threshold, a transition back to the appropriate active mode occurs. EN is high; Other than a disabled Main Link output, this state characteristics are identical to DPCD register 101h or 103h entry the active state from where the transition occurred. is invalid A transition to this state may occur from DisplayPort Active Mode, D3 Power Down Mode, or Compliance Test Mode when DPCD writes (from the local I2C or the AUX channel) update the DPCD 101h or 103h registers with invalid values; this action causes the DP sink to issue an interrupt and re-train the link. Compliance Test Mode Through local I2C registers the device can be forced into ignoring TMDS_HPD_SNK, DP_HPD_SNK, and CAD_SNK; HPD_SRC and CAD_SRC outputs are programmed through local I2C registers (default output low); all other configurations (such as output signal conditioning and EQ settings) are programmable through the local I2C registers in this state. EN is high; Local I2C programming selects the this mode Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 23 SN75DP126 SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com Implementing the EN Signal The SN75DP126 EN input gives control over the device reset and to place the device into Shutdown mode. When EN is low, all DPCD and local I2C registers are reset to their default values, and all Main Link lanes are disabled. It is critical to reset the digital logic of the SN75DP126 after the VCC supply (and VDD supply for SN75DP126DS) is stable (that is, the power supply has reached the minimum recommended operating voltage). To reset the digital logic, transition the EN input from a low level to a high level. A system may provide a control signal to the EN signal that transitions low to high after the power supply is (or supplies are) stable, or implement an external capacitor connected between EN and GND, to allow delaying the EN signal during power up. Both implementations are shown in the following figures. VDD or VDD_DREG GPO open drain output EN C EN REN = 150 kW C controller SN75DP126 Figure 28. EN Input from Active Controller SN75DP126 Figure 27. External Capacitor Controlled EN When implementing the external capacitor, the size of the external capacitor depends on the power up ramp of the VCC (and VDD when applicable) supply, where a slower ramp-up results in a larger value external capacitor. Refer to the latest reference schematic for the SN75DP126 device and/or consider approximately 200nF capacitor as a reasonable first estimate for the size of the external capacitor. When implementing an EN input from an active controller, it is recommended to use an open drain driver if the EN input is driven. This protects the EN input from damage of an input voltage greater than VDD_DREG (or VDD). Hot Plug Detect (HPD) and Cable Adapter Detect (CAD) Description The SN75DP126 drives the source-side Hot Plug Detect (HPD_SRC) signal output high to indicate to the GPU or graphics source that at least one sink has been detected and selected for connectivity; when no sink is selected the HPD_SRC is driven low. A high-level DP_HPD_SNK input indicates a DisplayPort sink device is connected, and a high-level TMDS_HPD_SNK input indicates a HDMI/DVI sink device is connected. When DP_HPD_SNK is high, the DisplayPort sink is selected if the TMDS_HPD_SNK input is low. When TMDS_HPD_SNK is high, the HDMI/DVI sink is selected if the DP_HPD_SNK input is low. If both DP_HPD_SNK and TMDS_HPD_SNK inputs are high, then the PRIORITY input determines which sink is selected. When the DisplayPort sink is selected, the CAD_SNK input indicates whether a DP sink (CAD_SNK = low) or a TMDS sink (CAD_SNK = high) is connected. The level of CAD_SNK is passed to the CAD_SRC output when the DisplayPort sink is selected. When the HDMI/DVI sink is selected, the CAD_SRC output is driven high regardless of the value input on CAD_SRC. A sink is determined to be disconnected when the corresponding HPD_SNK input goes low for a duration of tT(HPD). When switching from one sink to the other based on the PRIORITY selection, that is, both sinks are connected and either PRIORITY has changed or the sink with higher PRIORITY was connected after the sink with lower PRIORITY, the SN75DP126 asserts HPD_SRC for a duration at least tT(HPD) before the switchover connection is established. Through the local I2C interface it is possible to force the device to ignore DP_HPD_SNK, TMDS_HPD_SNK, and CAD_SNK, and control HPD_SRC and CAD_SRC directly. 24 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 SN75DP126 www.ti.com SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 When the EN pin is de-asserted (device is in power down mode), the HPD path from DP_HPD_SNK and/or TMDS_HPD_SNK to HPD_SRC is not reset. As a result, the source may need to retrain the link once EN is asserted (device is in active mode). See Figure 14 and Table 2 for more information about the HPD and CAD functions. OVS Function Description The SN75DP126 provides an output-voltage select (OVS) control for the source side buffers on the DDC I2C lines. When the sink side is driven low, the corresponding source side driver turns on and drives the source side down to a low-level output voltage, VOL. The value of VOL and VIL on the source side of the SN75DP126 depends on setting of the OVS pin. VOL is always higher than VIL on the source side to prevent lockup of the buffers on the DDC I2C lines. When the sink side is pulled up, the source side driver turns off and the sink side pin is highimpedance. When the source side is driven below VIL by an external I2C driver, both the sink and source side drivers are turned on. The sink side driver drives the sink side to near 0V, and the source side driver is on, but is overridden by the external I2C driver. When the source side is released by the external I2C driver, the source side driver is still on, so the source side is only able to rise to VOL. However, the sink side driver turns off because the source side is above the VIL threshold. If no external I2C driver is keeping the sink side low, the sink side rises causing the source side driver to turn off. See Figure 17 and Figure 18 for more information. It is important that any external I2C driver on the source side is able to drive the bus below VIL to achieve full operation. If the source side cannot be driven below VIL, the sink side driver may not recognize and transmit the low value to the sink side. AUX and DDC Configuration Details The SN75DP126 connectivity between source-side AUX and DDC channels and the sink-side AUX and DDC channels is described in Table 3. Refer to the BLOCK DIAGRAM for more information about the AUX and DDC switches, buffers, and logic elements represented in Table 2. Note that the DDC interface incorporates 60kΩ pull-up resistors on SDA_SRC and SCL_SRC which are enabled when CAD_SRC is driven high, and disabled (turned off) when CAD_SRC is driven low. Table 2. AUX and DDC Switch, Buffers, and Logic Element Control 0 1 X 1 1 0 0 1 X 1 1 0 1 0 X 1 (1) 1 1 (1580h/81h DDC Buffer) 14DP-HDMI ADAPTOR ID12 AUX MONITOR (Link Training) HDMI/DVI DDC LEVEL- CAD_SRC (Source-Side Output) OFF OFF OFF OFF OFF OFF no sink selected; low power mode 0 ON OFF ON OFF ON OFF DisplayPort sink selected; operating in DP mode; AUX_SNK connects to AUX_SRC and Link Training enabled 1 1 OFF ON ON OFF OFF OFF DisplayPort sink selected; operating in TMDS mode; AUX_SNK connects to source-side DDC (SCL/SDA_SRC) X 1 OFF ON OFF ON OFF ON HDMI/DVI sink selected; connect the source-side DDC to sink-side DDC; enable the DP-HDMI Adaptor ID accessed via DDC addresses 80h/81h SHIFTI I/O BUFFERS DP AUX_SNK SWITCH X DDC_SRC SWITCH 0 AUX_SRC SWITCH 0 OUTPUTS AND CONTROLS CAD_SNK PRIORITY DP_HPD_SNK TMDS_HPD_SNK INPUTS COMMENTS14 (1) 0 0 1 1 (1) 0 After transitioning from HDMI/DVI mode to low power mode, CAD_SRC will remain high regardless of the status of CAD_SNK Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 25 SN75DP126 SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com Source-Side Main Link EQ Configuration Details A variety of EQ settings are available through external pin configuration to accommodate for different PCB loss and GPU settings. The I2C interface is utilized to fully customize EQ configuration, lane-by-lane, beyond the input pin configuration options, as described in Table 3. Table 3. Source-Side Main Link EQ Configurations ≤ VIL ≤ VIL VIM ≥ VIH 0 VIM (1) (2) (3) VIM or ≥ VIH (Register 04.2) TMDS SIGNAL MODE (3) (TMDS DATA) SOURCE LANES IN[2:0] TMDS SIGNAL MODE (3) (TMDS CLOCK) SOURCE LANE IN[3] 6 dB at 2.7 GHz 3 dB at 1.35 GHz 6 dB at 2.7 GHz 6 dB at 2.7 GHz 3 dB at 1.35 GHz 13 dB at 2.7GHz 13 dB at 2.7 GHz 3 dB at 1.35 GHz 13 dB at 2.7 GHz 3 dB at 1.35 GHz DISPLAYPORT SIGNAL MODE (1) (2) SOURCE LANES IN[3:0] 1 AEQ(L0) = 8 dB at 2.7 GHz AEQ(L1) = 6 dB at 2.7 GHz AEQ(L2) = 3.5 dB at 2.7 GHz AEQ(L3) = 0 dB at 2.7 GHz 0 6 dB at 2.7 GHz X 1 AEQ(L0) = 15 dB at 2.7 GHz AEQ(L1) = 13 dB at 2.7 GHz AEQ(L2) = 10 dB at 2.7 GHz AEQ(L3) = 6 dB at 2.7 GHz 0 13 dB at 2.7 GHz X 18 dB at 2.7 GHz 18 dB at 2.7 GHz 3 dB at 1.35 GHz 1 AEQ(Lx) = 0 dB at 2.7 GHz (default) EQ settings for each link training level can be selected via local I2C 0 dB at 2.7 GHz (default) EQ settings selected via local I2C, training level L1 (AEQ_L1_LANEx_SET registers) 3 dB at 1.35 GHz 0 0 dB at 2.7 GHz (default) EQ settings selected via local I2C; training level L1 (AEQ_L1_LANEx_SET registers) 0 dB at 2.7 GHz (default) EQ settings selected via local I2C; training level L1 (AEQ_L1_LANEx_SET registers) 3 dB at 1.35 GHz X ≥ VIH 1 LINK_TRAINING_ENABLE (3-Level Input) EQ SETTINGS SCL_CTL/EQ (3-Level Input) I2C_CTL_EN (Register 05.7) EQ_I2C_ENABLE INPUTS X DisplayPort mode is active when the DisplayPort sink is selected and the CAD_SNK input is low In DisplayPort signaling mode, the EQ gain may be applied after the Link Training is complete TMDS mode is active when the DisplayPort sink is selected and the CAD_SNK input is high, or when the HDMI/DVI sink is selected Link Training and DPCD Description The SN75DP126 can monitor the auxiliary interface access to DisplayPort Configuration Data (DPCD) registers during Link Training in DisplayPort mode, to select the output voltage swing VOD, output pre-emphasis, and the EQ setting of the Main Link. The AUX monitor for SN75DP126 supports Link Training in 1-Mbps Manchester mode, and is disabled during TMDS modes of operation. The DPCD registers monitored by SN75DP126 are listed below. Bit fields not listed are reserved and values written to reserved fields are ignored. 26 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 SN75DP126 www.ti.com SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 Table 4. DPCD Registers Utilized by the SN75DP126 AUX Monitor ADDRESS 00100h 00101h NAME LINK_BW_SET LANE_COUNT_SET DESCRIPTION Bits 7:0 = Link Bandwidth Setting Write Values: 06h – 1.62 Gbps per lane 0Ah – 2.7 Gbps per lane (default) 14h – 5.4 Gbps per lane Note: any other value is reserved; the SN75DP126 will revert to 5.4 Gbps operation when any other value is written Read Values: 00h – 1.62 Gbps per lane 01h – 2.7 Gbps per lane (default) 02h – 5.4 Gbps per lane Bits 4:0 = Lane Count Write Values: 0h – All lanes disabled (default) 1h – One lane enabled 2h – Two lanes enabled 4h – Four lanes enabled Note: any other value is invalid and disables all Main Link output lanes Read Values: 0h – All lanes disabled (default) 1h – One lane enabled 3h – Two lanes enabled Fh – Four lanes enabled 00103h TRAINING_LANE0_SET Write Values: Bits 1:0 = Output Voltage VOD Level 00 – Voltage swing level 0 (default) 01 – Voltage swing level 1 10 – Voltage swing level 2 11 – Voltage swing level 3 Bits 4:3 = Pre-emphasis Level 00 – Pre-emphasis level 0 (default) 01 – Pre-emphasis level 1 10 – Pre-emphasis level 2 11 – Pre-emphasis level 3 Note: the following combinations are not allowed for bits [1:0]/[4:3]: 01/11, 10/10, 10/11, 11/01, 11/10, 11/11; setting to any of these invalid combinations disables all Main Link lanes until the register value is changed back to a valid entry Read Values: Bits 1:0 = Output Voltage VOD Level 00 – Voltage swing level 0 (default) 01 – Voltage swing level 1 10 – Voltage swing level 2 11 – Voltage swing level 3 Bits 3:2 = Pre-emphasis Level 00 – Pre-emphasis level 0 (default) 01 – Pre-emphasis level 110 – Pre-emphasis level 2 11 – Pre-emphasis level 3 00104h TRAINING_LANE1_SET Sets the VOD and pre-emphasis levels for lane 1 00105h TRAINING_LANE2_SET Sets the VOD and pre-emphasis levels for lane 2 00106h TRAINING_LANE3_SET Sets the VOD and pre-emphasis levels for lane 3 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 27 SN75DP126 SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com Table 4. DPCD Registers Utilized by the SN75DP126 AUX Monitor (continued) ADDRESS 0010F 0110F 00600h NAME DESCRIPTION Write Values: Bits 1:0 = Lane 0 Post Cursor 2 00 – IN0 expects post cursor2 level 0; 01 – IN0 expects post cursor2 level 1; 10 – IN0 expects post cursor2 level 2; 11 – IN0 expects post cursor2 level 3; Bits 5:4 = Lane 1 Post Cursor 2 00 – IN1 expects post cursor2 level 0; 01 – IN1 expects post cursor2 level 1; 10 – IN1 expects post cursor2 level 2; 11 – IN1 expects post cursor2 level 3; Read Values: Bits 1:0 = Lane 0 Post Cursor 2 00 – IN0 expects post cursor2 level 0; 01 – IN0 expects post cursor2 level 1; 10 – IN0 expects post cursor2 level 2; 11 – IN0 expects post cursor2 level 3; Bits 3:2 = Lane 1 Post Cursor 2 00 – IN1 expects post cursor2 level 0; 01 – IN1 expects post cursor2 level 1; 10 – IN1 expects post cursor2 level 2; 11 – IN1 expects post cursor2 level 3; TRAINING_LANE0_1_SET2 OUT0 OUT0 OUT0 OUT0 transmits at transmits at transmits at transmits at post cursor post cursor post cursor post cursor 2 level 0 2 level 0 2 level 0 2 level 0 OUT1 OUT1 OUT1 OUT1 transmits at transmits at transmits at transmits at post cursor post cursor post cursor post cursor 2 level 0 2 level 0 2 level 0 2 level 0 OUT0 OUT0 OUT0 OUT0 transmits at transmits at transmits at transmits at post cursor post cursor post cursor post cursor 2 level 0 2 level 0 2 level 0 2 level 0 OUT1 OUT1 OUT1 OUT1 transmits at transmits at transmits at transmits at post cursor post cursor post cursor post cursor 2 level 0 2 level 0 2 level 0 2 level 0 Bit definition identical to that of TRAINING_LANE_0_1_SET2 but for lanes 2 (IN2/OUT2) and lane 3 (IN3/OUT3) TRAINING_LANE2_3_SET2 Bits 1:0 = Power Mode Write Values: 01 – Normal mode (default) 10 – Power down mode; D3 Standby Mode The Main Link and all analog circuits are shut down and the AUX channel is monitored during the D3 Standby Mode. The device exits D3 Standby Mode by access to this register, when CAD_SNK goes high, or if DP_HPD_SNK goes low for longer than tT(HPD), which indicates that the DP sink was disconnected, or that the PRIORITY control has selected the HDMI/DVI sink. Note: setting the register to the invalid combination 0600h[1:0] = 00 or 11 is ignored by the device and the device remains in normal mode Read Values: 00 – Normal mode (default) 01 – Power-down mode; D3 Standby Mode SET_POWER Local I2C Interface Overview The SN75DP126 local I2C interface is enabled when EN is input high, and the I2C_CTL_EN control input is not input low. The SCL_CTL and SDA_CTL terminals are used for I2C clock and I2C data respectively. The SN75DP126 I2C interface conforms to the two-wire serial interface defined by the I2C Bus Specification, Version 2.1 (January 2000), and supports the standard mode transfer up to 100 kbps. The device address byte is the first byte received following the START condition from the master device. The 7 bit device address for SN75DP126 is factory preset to 010110x with the least significant bit being determined by the I2C_CTL_EN 3-level control input. Table 5 clarifies the SN75DP126 target address. Table 5. SN75DP126 I2C Target Address Description SN75DP126 I2C TARGET ADDRESS BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (W/R) 0 1 0 1 1 0 X 0/1 I2C_CTL_EN = Low : Local I2C interface is disabled. I2C_CTL_EN = Between VIL and VIH: X = 0, Address Cycle is 0x58 (Write) and 0x59 (Read). I2C_CTL_EN = High: X = 1, Address Cycle is 0x5A (Write) and 0x5B (Read). The following procedure is followed to write to the SN75DP126 I2C registers: 1. The master initiates a write operation by generating a start condition (S), followed by the SN75DP126 7-bit address and a zero-value “W/R” bit to indicate a write cycle 2. The SN75DP126 acknowledges the address cycle 3. The master presents the sub-address (I2C register within SN75DP126) to be written, consisting of one byte of data, MSB-first 28 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 SN75DP126 www.ti.com SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 4. 5. 6. 7. The SN75DP126 acknowledges the sub-address cycle The master presents the first byte of data to be written to the I2C register The SN75DP126 acknowledges the byte transfer The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the SN75DP126 8. The master terminates the write operation by generating a stop condition (P) The following procedure is followed to read the SN75DP126 I2C registers. 1. The master initiates a read operation by generating a start condition (S), followed by the SN75DP126 7-bit address and a one-value “W/R” bit to indicate a read cycle 2. The SN75DP126 acknowledges the address cycle 3. The SN75DP126 transmit the contents of the memory registers MSB-first starting at register 00h 4. The SN75DP126 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I2C master acknowledges reception of each data byte transfer 5. If an ACK is received, the SN75DP126 transmits the next byte of data 6. The master terminates the read operation by generating a stop condition (P) Note that no sub-addressing is included for the read procedure, and reads start at register offset 00h and continue byte by byte through the registers until the I2C master terminates the read operation. Refer to Table 6 for SN75DP126 local I2C register descriptions. Reads from reserved fields not described return zeros, and writes are ignored. Table 6. SN75DP126 Local I2C Control and Status Registers ADDRESS BIT(S) DESCRIPTION ACCESS SINK_PORT_SELECT 00 – DP_HPD_SNK and TMDS_HPD_SNK select the sink; when both are asserted, the PRIORITY control input is used where PRIORITY = LOW selects the DisplayPort sink (default) 3:2 01 – DP_HPD_SNK and TMDS_HPD_SNK select the sink; when both are asserted, the PRIORITY control input is used where PRIORITY = LOW selects the HDMI/DVI sink RW 10 – Force DisplayPort sink selection regardless of device HPD and control inputs 11 – Force HDMI/DVI sink selection regardless of device HPD and control inputs 01h FORCE_HPD_SRC 1 0 – Enter Standby mode when DP_HPD_SNK and TMDS_HPD_SNK are input low, and drive HPD_SRC high when DP_HPD_SNK or TMDS_HPD_SNK are input high (default) RW 1 – Drive HPD_SRC output high regardless of DP_HPD_SNK and TMDS_HPD_SNK inputs FORCE_SHUTDOWN_MODE 0 0 – SN75DP126 is forced to Shutdown mode RW 1 – Shutdown mode is determined by EN input, normal operation (default) 02h 7:0 TI_TEST. This field defaults to zero value, and should not be modified. RW SQUELCH_SENSITIVITY. Input Main Link squelch sensitivity is selected by this field, and determines the transitions to and from the Output Disable mode. 00 – Main Link IN0p/n squelch detection threshold set to 60 mVpp 5:4 01 – Main Link IN0p/n squelch detection threshold set to 115 mVpp (default) RW 10 – Main Link IN0p/n squelch detection threshold set to 160 mVpp 03h 11 – Main Link IN0p/n squelch detection threshold set to 200 mVpp SQUELCH_ENABLE 3 0 – Main Link IN0p/n squelch detection enabled (default) RW 1 – Main Link IN0p/n squelch detection disabled Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 29 SN75DP126 SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com Table 6. SN75DP126 Local I2C Control and Status Registers (continued) ADDRESS BIT(S) 3 DESCRIPTION ACCESS TI_TEST. This field defaults to zero value, and should not be modified. RW LINK_TRAINING_ENABLE 04h 2 0 – DisplayPort sink Link Training is disabled. VOD and Pre-emphasis are configured through the I2C register interface; the EQ is fixed when this bit is zero. RW 1 – DisplayPort sink Link Training is enabled (default) 1 Reserved - Do not change this value R/W EQ_I2C_ENABLE 7 0 – EQ settings controlled by device inputs only (default) RW 1 – EQ settings controlled by I2C register settings AEQ_L0_LANE0_SET. This field selects the EQ setting for Lane 0 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 0 pre-emphasis. 6:4 05h 2:0 000 – 0 dB EQ gain (default) 100 – 5 dB (HBR); 10 dB (HBR2) 001 – 1.5 dB (HBR); 3.5 dB (HBR2) 101 – 6 dB (HBR); 13 dB (HBR2) 010 – 3 dB (HBR); 6 dB (HBR2) 110 – 7 dB (HBR); 15 dB (HBR2) 011 – 4 dB (HBR); 8 dB (HBR2) 111 – 9 dB (HBR); 18 dB (HBR2) AEQ_L1_LANE0_SET. This field selects the EQ setting for Lane 0 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 1 pre-emphasis. This field also selects the fixed EQ setting for the following nonAEQ modes: RW RW MM ● I2C_EQ_ENABLE is set, the DisplayPort sink is selected, and Link Training is disabled MM ● I2C_EQ_ENABLE is set and the TMDS sink is selected. 06h 6:4 2:0 30 000 – 0 dB EQ gain (default) 100 – 5 dB (HBR); 10 dB (HBR2) 001 – 1.5 dB (HBR); 3.5 dB (HBR2) 101 – 6 dB (HBR); 13 dB (HBR2) 010 – 3 dB (HBR); 6 dB (HBR2) 110 – 7 dB (HBR); 15 dB (HBR2) 011 – 4 dB (HBR); 8 dB (HBR2) 111 – 9 dB (HBR); 18 dB (HBR2) AEQ_L2_LANE0_SET. This field selects the EQ setting for Lane 0 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 2 pre-emphasis. 000 – 0 dB EQ gain (default) 100 – 5 dB (HBR); 10 dB (HBR2) 001 – 1.5 dB (HBR); 3.5 dB (HBR2) 101 – 6 dB (HBR); 13 dB (HBR2) 010 – 3 dB (HBR); 6 dB (HBR2) 110 – 7 dB (HBR); 15 dB (HBR2) 011 – 4 dB (HBR); 8 dB (HBR2) 111 – 9 dB (HBR); 18 dB (HBR2) AEQ_L3_LANE0_SET. This field selects the EQ setting for Lane 0 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 3 pre-emphasis. 000 – 0 dB EQ gain (default) 100 – 5 dB (HBR); 10 dB (HBR2) 001 – 1.5 dB (HBR); 3.5 dB (HBR2) 101 – 6 dB (HBR); 13 dB (HBR2) 010 – 3 dB (HBR); 6 dB (HBR2) 110 – 7 dB (HBR); 15 dB (HBR2) 011 – 4 dB (HBR); 8 dB (HBR2) 111 – 9 dB (HBR); 18 dB (HBR2) Submit Documentation Feedback RW RW Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 SN75DP126 www.ti.com SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 Table 6. SN75DP126 Local I2C Control and Status Registers (continued) ADDRESS BIT(S) DESCRIPTION ACCESS 07h 6:4 AEQ_L0_LANE1_SET. This field selects the EQ setting for Lane 1 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 0 pre-emphasis. RW 2:0 000 – 0 dB EQ gain (default) 100 – 5 dB (HBR); 10 dB (HBR2) 001 – 1.5 dB (HBR); 3.5 dB (HBR2) 101 – 6 dB (HBR); 13 dB (HBR2) 010 – 3 dB (HBR); 6 dB (HBR2) 110 – 7 dB (HBR); 15 dB (HBR2) 011 – 4 dB (HBR); 8 dB (HBR2) 111 – 9 dB (HBR); 18 dB (HBR2) AEQ_L1_LANE1_SET. This field selects the EQ setting for Lane 1 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 1 pre-emphasis. This field also selects the fixed EQ setting for the following nonAEQ modes: RW MM ● I2C_EQ_ENABLE is set, the DisplayPort sink is selected, and Link Training is disabled MM ● I2C_EQ_ENABLE is set and the TMDS sink is selected. 08h 6:4 2:0 09h 6:4 2:0 000 – 0 dB EQ gain (default) 100 – 5 dB (HBR); 10 dB (HBR2) 001 – 1.5 dB (HBR); 3.5 dB (HBR2) 101 – 6 dB (HBR); 13 dB (HBR2) 010 – 3 dB (HBR); 6 dB (HBR2) 110 – 7 dB (HBR); 15 dB (HBR2) 011 – 4 dB (HBR); 8 dB (HBR2) 111 – 9 dB (HBR); 18 dB (HBR2) AEQ_L2_LANE1_SET. This field selects the EQ setting for Lane 1 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 2 pre-emphasis. 000 – 0 dB EQ gain (default) 100 – 5 dB (HBR); 10 dB (HBR2) 001 – 1.5 dB (HBR); 3.5 dB (HBR2) 101 – 6 dB (HBR); 13 dB (HBR2) 010 – 3 dB (HBR); 6 dB (HBR2) 110 – 7 dB (HBR); 15 dB (HBR2) 011 – 4 dB (HBR); 8 dB (HBR2) 111 – 9 dB (HBR); 18 dB (HBR2) AEQ_L3_LANE1_SET. This field selects the EQ setting for Lane 1 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 3 pre-emphasis. 000 – 0 dB EQ gain (default) 100 – 5 dB (HBR); 10 dB (HBR2) 001 – 1.5 dB (HBR); 3.5 dB (HBR2) 101 – 6 dB (HBR); 13 dB (HBR2) 010 – 3 dB (HBR); 6 dB (HBR2) 110 – 7 dB (HBR); 15 dB (HBR2) 011 – 4 dB (HBR); 8 dB (HBR2) 111 – 9 dB (HBR); 18 dB (HBR2) AEQ_L0_LANE2_SET. This field selects the EQ setting for Lane 2 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 0 pre-emphasis. 000 – 0 dB EQ gain (default) 100 – 5 dB (HBR); 10 dB (HBR2) 001 – 1.5 dB (HBR); 3.5 dB (HBR2) 101 – 6 dB (HBR); 13 dB (HBR2) 010 – 3 dB (HBR); 6 dB (HBR2) 110 – 7 dB (HBR); 15 dB (HBR2) 011 – 4 dB (HBR); 8 dB (HBR2) 111 – 9 dB (HBR); 18 dB (HBR2) AEQ_L1_LANE2_SET. This field selects the EQ setting for Lane 2 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 1 pre-emphasis. This field also selects the fixed EQ setting for the following nonAEQ modes: RW RW RW RW MM ● I2C_EQ_ENABLE is set, the DisplayPort sink is selected, and Link Training is disabled MM ● I2C_EQ_ENABLE is set and the TMDS sink is selected. 000 – 0 dB EQ gain (default) 100 – 5 dB (HBR); 10 dB (HBR2) 001 – 1.5 dB (HBR); 3.5 dB (HBR2) 101 – 6 dB (HBR); 13 dB (HBR2) 010 – 3 dB (HBR); 6 dB (HBR2) 110 – 7 dB (HBR); 15 dB (HBR2) 011 – 4 dB (HBR); 8 dB (HBR2) 111 – 9 dB (HBR); 18 dB (HBR2) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 31 SN75DP126 SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com Table 6. SN75DP126 Local I2C Control and Status Registers (continued) ADDRESS BIT(S) DESCRIPTION ACCESS 0Ah 6:4 AEQ_L2_LANE2_SET. This field selects the EQ setting for Lane 2 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 2 pre-emphasis. RW 2:0 0Bh 6:4 2:0 000 – 0 dB EQ gain (default) 100 – 5 dB (HBR); 10 dB (HBR2) 001 – 1.5 dB (HBR); 3.5 dB (HBR2) 101 – 6 dB (HBR); 13 dB (HBR2) 010 – 3 dB (HBR); 6 dB (HBR2) 110 – 7 dB (HBR); 15 dB (HBR2) 011 – 4 dB (HBR); 8 dB (HBR2) 111 – 9 dB (HBR); 18 dB (HBR2) AEQ_L3_LANE2_SET. This field selects the EQ setting for Lane 2 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 3 pre-emphasis. 000 – 0 dB EQ gain (default) 100 – 5 dB (HBR); 10 dB (HBR2) 001 – 1.5 dB (HBR); 3.5 dB (HBR2) 101 – 6 dB (HBR); 13 dB (HBR2) 010 – 3 dB (HBR); 6 dB (HBR2) 110 – 7 dB (HBR); 15 dB (HBR2) 011 – 4 dB (HBR); 8 dB (HBR2) 111 – 9 dB (HBR); 18 dB (HBR2) AEQ_L0_LANE3_SET. This field selects the EQ setting for Lane 3 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 0 pre-emphasis. 000 – 0 dB EQ gain (default) 100 – 5 dB (HBR); 10 dB (HBR2) 001 – 1.5 dB (HBR); 3.5 dB (HBR2) 101 – 6 dB (HBR); 13 dB (HBR2) 010 – 3 dB (HBR); 6 dB (HBR2) 110 – 7 dB (HBR); 15 dB (HBR2) 011 – 4 dB (HBR); 8 dB (HBR2) 111 – 9 dB (HBR); 18 dB (HBR2) AEQ_L1_LANE3_SET. This field selects the EQ setting for Lane 3 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 1 pre-emphasis. This field also selects the fixed EQ setting for the following nonAEQ mode: RW RW RW MM ● I2C_EQ_ENABLE is set, the DisplayPort sink is selected, and Link Training is disabled 0Ch 6:4 2:0 32 000 – 0 dB EQ gain (default) 100 – 5 dB (HBR); 10 dB (HBR2) 001 – 1.5 dB (HBR); 3.5 dB (HBR2) 101 – 6 dB (HBR); 13 dB (HBR2) 010 – 3 dB (HBR); 6 dB (HBR2) 110 – 7 dB (HBR); 15 dB (HBR2) 011 – 4 dB (HBR); 8 dB (HBR2) 111 – 9 dB (HBR); 18 dB (HBR2) AEQ_L2_LANE3_SET. This field selects the EQ setting for Lane 3 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 2 pre-emphasis. 000 – 0 dB EQ gain (default) 100 – 5 dB (HBR); 10 dB (HBR2) 001 – 1.5 dB (HBR); 3.5 dB (HBR2) 101 – 6 dB (HBR); 13 dB (HBR2) 010 – 3 dB (HBR); 6 dB (HBR2) 110 – 7 dB (HBR); 15 dB (HBR2) 011 – 4 dB (HBR); 8 dB (HBR2) 111 – 9 dB (HBR); 18 dB (HBR2) AEQ_L3_LANE3_SET. This field selects the EQ setting for Lane 3 when I2C_EQ_ENABLE is set, the DisplayPort sink is selected, Link Training is enabled, and the Link Training results in Level 3 pre-emphasis. 000 – 0 dB EQ gain (default) 100 – 5 dB (HBR); 10 dB (HBR2) 001 – 1.5 dB (HBR); 3.5 dB (HBR2) 101 – 6 dB (HBR); 13 dB (HBR2) 010 – 3 dB (HBR); 6 dB (HBR2) 110 – 7 dB (HBR); 15 dB (HBR2) 011 – 4 dB (HBR); 8 dB (HBR2) 111 – 9 dB (HBR); 18 dB (HBR2) Submit Documentation Feedback RW RW Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 SN75DP126 www.ti.com SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 Table 6. SN75DP126 Local I2C Control and Status Registers (continued) ADDRESS BIT(S) 15h 4:3 DESCRIPTION ACCESS DP_BOOST. Controls the output pre-emphasis amplitude when the DisplayPort sink is selected; allows to reduce or increase all pre-emphasis settings by ~10%. Setting this field will impact VOD when pre-emphasis is disabled. RW This setting also impacts the output in TMDS mode for the DisplayPort sink connection when the DisplayPort sink CAD_SNK input is high. 00 – Pre-emphasis reduced by ~10%; VOD reduced by 10% if pre-emphasis is disabled. 01 – Pre-emphasis nominal (default) 10 – Pre-emphasis increased by ~10%; VOD increased by 10% if pre-emphasis is disabled. 11 – Reserved 2 DP_TMDS_VOD. Sets the target output swing in TMDS mode when the DisplayPort sink is selected, where CAD_SNK input is high. RW 0 – Low TMDS output swing for DisplayPort sink channel (default) 1 – High TMDS output swing for DisplayPort sink channel 1:0 DP_TMDS_VPRE. Controls the output pre-emphasis in TMDS mode when the DisplayPort sink is selected, where CAD_SNK input is high. RW 00 – No TMDS pre-emphasis for DisplayPort sink channel (default) 01 – Low TMDS pre-emphasis for DisplayPort sink channel 10 – High TMDS pre-emphasis for DisplayPort sink channel 11 – Reserved 17h 3 DP_HPD_TEST_MODE 0 – Normal HPD operating mode. (default) RW 1 – DisplayPort sink compliance test mode. DP_HPD_SNK is pulled high internally, the TMDS_HPD_SNK is pulled low internally, and the HPD_SRC output is driven high and the Main Link is activated depending on the squelch setting. 1 CAD_OUTPUT_INVERT RW 0 – CAD_SRC output high means TMDS cable adapter detected when the DisplayPort sink is selected (default) 1 – CAD_SRC output low means TMDS cable adapter detected when the DisplayPort sink is selected CAD_TEST_MODE 0 0 – Normal CAD mode. CAD_SRC reflects the status of CAD_SNK, based on the value of CAD_OUTPUT_INVERT, when the DisplayPort sink is selected (default) 1 – Test mode. CAD_SRC indicates TMDS mode when the DisplayPort sink is selected, depending on the value of CAD_OUTPUT_INVERT; CAD_SNK input is ignored. This mode allows execution of certain tests on SN75DP126 without a connected TMDS display sink. HDMI/DVI_PRE 00 – 0 dB Pre-emphasis applied to the HDMI/DVI sink TMDS output 18h 3:2 01 – Reserved RW 10 – Reserved 11 – 2 dB Pre-emphasis applied to the HDMI/DVI sink TMDS output 19h – 1Ah 7:0 TI_TEST. These registers shall not be modified. RW 7 I2C_SOFT_RESET. Writing a one to this register resets all I2C registers to default values. Writing a zero to this register has no effect. Reads from this register return zero. WO 6 DPCD_RESET. Writing a one to this register resets the DPCD register bits (corresponding to DPCD addresses 103h – 10Fh). Writing a zero to this register has no effect. Reads from this register return zero. WO 1Bh 1Ch 3:0 DPCD_ADDR_HIGH. This value maps to bits 19:16 of the 20-bit DPCD register address accessed through the DPCD_DATA register. RW 1Dh 7:0 DPCD_ADDR_MID. This value maps to bits 15:8 of the 20-bit DPCD register address accessed through the DPCD_DATA register. RW 1Eh 7:0 DPCD_ADDR_LOW. This value maps to bits 7:0 of the 20-bit DPCD register address accessed through the DPCD_DATA register. RW Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 33 SN75DP126 SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012 www.ti.com Table 6. SN75DP126 Local I2C Control and Status Registers (continued) ADDRESS BIT(S) 1Fh DESCRIPTION ACCESS DPCD_DATA. This register contains the data to write into or read from the DPCD register addressed by DPCD_ADDR_HIGH, DPCD_ADDR_MID, and DPCD_ADDR_LOW. 7:0 RW DEV_ID_REV. This field identifies the device and revision. 7:1 RO 0000000 – SN75DP126 Revision 0 20h BIT_INVERT. The value read from this field is the inverse of that written. 0 RW Default read value is ’1’. 21h 7:0 TI_TEST. These registers shall not be modified. RW 22h – 27h 7:0 TI_TEST_RESERVED. These read only registers are reserved for test; writes are ignored. RO DP-HDMI Adaptor ID Buffer The SN75DP126 includes the DP-HDMI adapter ID buffer for HDMI/DVI adaptor recognition, defined by the VESA DisplayPort Interoperability Guidelines Version 1.1a, accessible by standard I2C protocols through the DDC interface when the HDMI/DVI sink is selected. The DP-HDMI adapter buffer is accessed at target addresses 80h (Write) and 81h (Read). The DP-HDMI adapter buffer contains a read-only phrase DP-HDMI ADAPTOR<EOT> converted to ASCII characters as illustrated in Table 7, and supports the Write command procedures (accessed at target address 80h) to select the sub-address, as recommended in the VESA DisplayPort Interoperability Guideline Adaptor Checklist Version 1.0 section 2.3. Table 7. SN75DP126 DP-HDMI Adaptor ID Buffer Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 Data 44 50 2D 48 44 4D 49 20 41 44 41 50 54 4F 52 04 FF Spacer REVISION HISTORY Changes from Original (February 2012) to Revision A • 34 Page Changed the device From Product Preview To Production .................................................................................................. 1 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN75DP126 PACKAGE OPTION ADDENDUM www.ti.com 28-Mar-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) SN75DP126DSRHUR ACTIVE WQFN RHU 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN75DP126SSRHUR ACTIVE WQFN RHU 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Apr-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN75DP126SSRHUR Package Package Pins Type Drawing WQFN RHU 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 11.3 1.0 8.0 W Pin1 (mm) Quadrant 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Apr-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75DP126SSRHUR WQFN RHU 56 2000 346.0 346.0 41.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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