TI TPS61122

www.ti.com
TPS61120
TPS61122, TPS61121
SLVS427C – JUNE 2002 – REVISED APRIL 2004
SYNCHRONOUS BOOST CONVERTER WITH 1.1A SWITCH AND INTEGRATED LDO
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
Synchronous, 95% Efficient, Boost Converter
With 500-mA Output Current From 1.8-V Input
Integrated 200-mA Reverse Voltage Protected
LDO for DC/DC Output Voltage Post Regulation or Second Output Voltage
40-µA (Typical) Total Device Quiescent Current
Input Voltage Range: 1.8-V to 5.5-V
Fixed and Adjustable Output Voltage Options
up to 5.5-V
Power Save Mode for Improved Efficiency at
Low Output Power
Low Battery Comparator
Power Good Output
Low EMI-Converter (Integrated Antiringing
Switch)
Load Disconnect During Shutdown
Overtemperature Protection
Available in a Small 4mm x 4mm QFN-16 or in
a TSSOP-16 Package
APPLICATIONS
•
•
•
All Single Cell Li or Dual Cell Battery or USB
Powered Products as MP-3 Player, PDAs, and
Other Portable Equipment
Dual Input or Dual Output Mode
Simple Li-Ion to 3.3-V Conversion
The TPS6112x devices provide a complete power
supply solution for products powered by either a
one-cell Li-Ion or Li-Polymer or a two up to 4 cells
Alkaline, NiCd or NiMH batteries. The devices can
generate two stable output voltages that are either
adjusted by an external resistor divider or fixed
internally on the chip. It also provides a simple
solution for generating 3.3 V out of a one-cell Li-Ion
or Li-Polymer battery at a maximum output current of
at least 200 mA with supply voltages down to 1.8 V.
The implemented boost converter is based on a fixed
frequency, pulse-width-modulation (PWM) controller
using a synchronous rectifier to obtain maximum
efficiency. The maximum peak current in the boost
switch is limited to a value of 1600 mA.
The converter can be disabled to minimize battery
drain. During shutdown, the load is completely disconnected from the battery. A low-EMI mode is
implemented to reduce ringing and in effect lower
radiated electromagnetic energy when the converter
enters the discontinuous conduction mode. A power
good output at the boost stage simplifies control of
any connected circuits like cascaded power supply
stages or microprocessors.
The built-in LDO can be used for a second output
voltage derived either from the boost output or
directly from the battery. The LDO can be enabled
separately i.e., using the power good of the boost
stage. The device is packaged in a 16-pin QFN
package measuring 4 mm x 4 mm (RSA) or in a
16-pin TSSOP (PW) package.
10 H
SWN
VBAT
10 F
Battery
SWP
VOUT
LBI
TPS61120
Vout1
100 F
FB
Control
Inputs
OFF
ON
OFF
ON
OFF
ON
SKIPEN
PGOOD
LBO
EN
Control
Outputs
LDOIN
LDOEN
LDOOUT
Vout2
2.2 F
GND
PGND
LDOSENSE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2004, Texas Instruments Incorporated
TPS61120
TPS61122, TPS61121
www.ti.com
SLVS427C – JUNE 2002 – REVISED APRIL 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.This integrated circuit can be damaged by ESD.
Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper
handling and installation procedures can cause damage.
AVAILABLE OUTPUT VOLTAGE OPTIONS (1)
TA
40°C to 85°C
(1)
(2)
OUTPUT VOLTAGE
DC/DC
OUTPUT VOLTAGE
LDO
Adjustable
Adjustable
3.3 V
1.5 V
3.6 V
3.3 V
Adjustable
Adjustable
3.3 V
1.5 V
PART NUMBER (2)
PACKAGE
TPS61120PW
16-Pin TSSOP
TPS61121PW
TPS61122PW
TPS61120RSA
16-Pin QFN 4x4mm
TPS61121RSA
Contact the factory to check availability of other fixed output voltage versions.
The packages are available taped and reeled. Add R suffix to device type (e.g., TPS61120PWR or TPS61120RSAR) to order quantities
of 2000 devices per reel for the TSSOP (PW) package and 3000 devices per reel for the QFN (RSA) package.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
TPS6112x
Input voltage range on FB
-0.3 V to 3.6 V
Input voltage range on SWN, SWP
-0.3 V to 10 V
Input voltage range on VOUT, LDOIN, LDOOUT, LDOEN, LDOSENSE, PGOOD, LBO, VBAT, LBI,
SKIPEN, EN
-0.3 V to 7 V
Maximum junction temperature TJ
-40°C to 150°C
Storage temperature range Tstg
-65°C to 150°C
(1)
Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX UNIT
Supply voltage at VBAT, VI
1.8
5.5
V
Operating ambient temperature range, TA
-40
85
°C
Operating virtual junction temperature range, TJ
-40
125
°C
2
TPS61120
TPS61122, TPS61121
www.ti.com
SLVS427C – JUNE 2002 – REVISED APRIL 2004
ELECTRICAL CHARACTERISTICS
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
DC/DC STAGE
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI
Input voltage range
1.8
5.5
V
VO
Adjustable output voltage range
(TPS61120)
2.5
5.5
V
Vref
Reference
voltage
485
500
515
mV
f
Oscillator
frequency
400
500
600
kHz
ISW
Switch current limit
1100
1300
1600
mA
VOUT= 3.3 V
Startup current
limit
0.4 x ISW
mA
SWN switch on resistance
VOUT= 3.3 V
200
350
mΩ
SWP switch on resistance
VOUT= 3.3 V
250
500
mΩ
Total accuracy (including line and
load regulation)
DC/DC
quiescent
current
±3%
-3%
into VBAT
IO= 0 mA, VEN = VBAT = 1.8 V,
VOUT = 3.3 V, ENLDO = 0
10
25
µA
into VOUT
IO = 0 mA, VEN = VBAT = 1.8 V,
VOUT = 3.3 V, ENLDO = 0
10
25
µA
VEN= 0 V
0.2
1
µA
DC/DC shutdown current
LDO STAGE
VI(LDO)
Input voltage range
1.8
7
V
VO(LDO)
Adjustable output voltage range
(TPS61120)
0.9
5.5
V
IO(max)
Output current
200
320
LDO short circuit current limit
mA
500
mA
300
mV
Minimum voltage drop
IO= 200 mA
Total accuracy (including line and
load regulation)
IO≥ 1 mA
±3%
Line regulation
LDOIN change from 1.8 V to 2.6 V
at 100 mA, LDOOUT = 1.5 V
0.6%
Load regulation
Load change from 10% to 90%,
LDOIN = 3.3 V
0.6%
LDO quiescent current
LDOIN = 7 V, VBAT = 1.8 V, EN =
VBAT
20
30
µA
LDO shutdown current
LDOEN = 0 V, LDOIN = 7 V
0.1
1
µA
500
510
mV
CONTROL STAGE
VIL
LBI voltage threshold
VLBI voltage decreasing
490
LBI input hysteresis
10
EN = VBAT or GND
0.01
0.1
LBO output low voltage
VO = 3.3 V, IOI = 100 µA
0.04
0.4
LBO output low current
LBO output leakage current
VIL
EN, SKIPEN input low voltage
VIH
EN, SKIPEN input high voltage
VIL
LDOEN input low voltage
VIH
mV
LBI input current
100
VLBO = 7 V
0.1
µA
0.2 × VBAT
V
V
0.2 × VLDOIN
0.8 ×
V
V
VLDOIN
Clamped on GND or VBAT
V
µA
0.8 ×
VBAT
LDOEN input high voltage
EN, SKIPEN input current
0.01
µA
0.01
0.1
µA
3
TPS61120
TPS61122, TPS61121
www.ti.com
SLVS427C – JUNE 2002 – REVISED APRIL 2004
CONTROL STAGE
Power-Good threshold
VO = 3.3 V
0.9xVo
Power-Good delay
0.92xVo
0.95xVo
30
Power-Good output low voltage
VO = 3.3 V, IOI = 100 µA
0.04
Power-Good output low current
Power-Good output leakage
current
0.4
100
VPG = 7 V
0.01
V
µs
V
µA
0.1
µA
Over-Temperature protection
140
°C
Over-Temperature hysteresis
20
°C
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VOUT
FB
PGOOD
LBO
GND
LDOSENSE
LDOOUT
LDOIN
PGND
VBAT
LBI
SKIPEN
PGOOD
LBO
GND
LDOSENSE
EN
LDOEN
LDOIN
LDOOUT
SWP
SWN
PGND
VBAT
LBI
SKIPEN
EN
LDOEN
RSA PACKAGE
(TOP VIEW)
SWN
SWP
VOUT
FB
PW PACKAGE
(TOP VIEW)
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
RSA
EN
7
5
I
DC/DC-enable input. (1/VBAT enabled, 0/GND disabled)
FB
15
13
I
DC/DC voltage feedback of adjustable versions
GND
12
10
I/O
Control/logic ground
LBI
5
3
I
Low battery comparator input (comparator enabled with EN)
LBO
13
11
O
Low battery comparator output (open drain)
LDOEN
8
6
I
LDO-enable input (1/LDOIN enabled, 0/GND disabled)
LDOOUT
10
8
O
LDO output
LDOIN
9
7
I
LDO input
LDOSENSE
11
9
I
LDO feedback for voltage adjustment, must be connected to LDOOUT
at fixed output voltage versions
DC/DC rectifying switch input
SWP
1
15
I
PGND
3
1
I/O
Power ground
PGOOD
14
12
O
DC/DC output power good (1 : good, 0 : failure) (open drain)
SKIPEN
6
4
I
Enable/disable power save mode (1: VBAT enabled, 0: GND disabled)
SWN
2
16
I
DC/DC switch input
VBAT
4
2
I
Supply pin
VOUT
16
14
O
DC/DC output
PowerPADTM
4
NO.
PW
Must be soldered to achieve appropriate power dissipation. Should be
connected to PGND.
TPS61120
TPS61122, TPS61121
www.ti.com
SLVS427C – JUNE 2002 – REVISED APRIL 2004
FUNCTIONAL BLOCK DIAGRAM
SWN
SWP
Backgate
Control
AntiRinging
VBAT
VOUT
100 kΩ
VOUT
Vmax
Control
20 pF
Gate
Control
PGND
PGND
Regulator
PGND
Error
Amplifier _
FB
+
Vref = 0.5 V
Control Logic
+
_
GND
Oscillator
Temperature
Control
EN
PGOOD
ENLDO
SYNC
LDOIN
Backgate
Control
GND
LDOOUT
Error
Amplifier
LBO
Low Battery
Comparator
_
LBI
+
+
_
_
LDOFB
+
Vref = 0.5 V
+
_
GND
Vref = 0.5 V
GND
5
TPS61120
TPS61122, TPS61121
www.ti.com
SLVS427C – JUNE 2002 – REVISED APRIL 2004
PARAMETER MEASUREMENT INFORMATION
U1
L1
10 µH
Power
Supply
C3
10 µF
SWN
SWP
VBAT
VOUT
R3
R1
C6
2.2 µF
FB
LBI
LDOIN
R2
SKIPEN
R6
Vout2
LDO Output
LDOOUT
R5
List of Components:
U1 = TPS6112xPW
L1 = Sumida CDRH73−100
C3, C5, C6 = X7R/X5R Ceramic
C4 = Low ESR Tantalum
R4
LDOEN
GND
R7
R9
LBO
PGOOD
PGND
TPS6112xPW
6
C5
2.2 µF
LDOSENSE
EN
Vout1
Boost Output
C4
100 µF
Control
Outputs
TPS61120
TPS61122, TPS61121
www.ti.com
SLVS427C – JUNE 2002 – REVISED APRIL 2004
TYPICAL CHARACTERISTICS
Table of Graphs
BOOST CONVERTER
Maximum output current
FIGURE
vs Input voltage
1, 2
vs Output current (TPS61120) (VO = 2.5 V, VI = 1.8 V)
3
vs Output current (TPS61121) (VO = 3.3 V, VI = 1.8 V, 2.4 V)
4
vs Output current (TPS61120) (VO = 5.0 V, VI = 2.4 V, 3.3 V)
5
vs Input voltage (TPS61121)
6
Output voltage
vs Output current (TPS61121)
7
No-load supply current into VBAT
vs Input voltage (TPS61121)
8
No-load supply current into VOUT
vs Input voltage (TPS61121)
9
Output voltage in continuous mode (TPS61121)
10
Output voltage in power save mode (TPS61121)
11
Load transient response (TPS61121)
12
Line transient response (TPS61121)
13
Start-up after enable (TPS61121)
14
vs Input voltage (VO = 2.5 V, 3.3 V)
15
vs Input voltage (VO = 1.5 V, 1.8 V)
16
Output voltage
vs Output current (TPS61122)
17
Dropout voltage
vs Output current (TPS61121, TPS61122)
18
Supply current into LDOIN
vs LDOIN input voltage (TPS61121)
19
PSRR
vs Frequency (TPS61121)
20
Load transient response (TPS61121)
21
Line transient response (TPS61121)
22
Start-up after enable (TPS61121)
23
Efficiency
Waveforms
LDO
Maximum output current
Waveforms
7
TPS61120
TPS61122, TPS61121
www.ti.com
SLVS427C – JUNE 2002 – REVISED APRIL 2004
TPS61120
MAXIMUM BOOST CONVERTER OUTPUT CURRENT
vs
INPUT VOLTAGE
TPS61120
MAXIMUM BOOST CONVERTER OUTPUT CURRENT
vs
INPUT VOLTAGE
1
1.4
0.90
Maximum Output Current - A
Maximum Output Current - A
1.2
1
0.8
VO = 5 V
0.6
0.4
0.80
0.70
VO = 2.5 V
0.60
0.50
0.40
0.30
0.20
0.2
0.10
0
1.8
2.2
2.6
3
3.4
3.8
4.2
4.6
0
1.8
5
1.9
2
2.1
2.2
2.3
VI - Input Voltage - V
VI - Input Voltage - V
2.4
Figure 1.
Figure 2.
TPS61120
BOOST CONVERTER EFFICIENCY
vs
OUTPUT CURRENT
TPS61121
BOOST CONVERTER EFFICIENCY
vs
OUTPUT CURRENT
100
100
90
90
80
80
70
70
2.5
VI = 1.8 V
Efficiency - %
Efficiency - %
VI = 2.4 V
60
50
40
30
50
40
30
20
20
VO = 2.5 V,
VI = 1.8 V
10
0.1
1
10
100
IO - Output Current - mA
Figure 3.
VO = 3.3 V
10
0
8
60
1000
0
0.1
1
10
100
IO - Output Current - mA
Figure 4.
1000
TPS61120
TPS61122, TPS61121
www.ti.com
SLVS427C – JUNE 2002 – REVISED APRIL 2004
TPS61120
BOOST CONVERTER EFFICIENCY
vs
OUTPUT CURRENT
100
TPS61121
BOOST CONVERTER EFFICIENCY
vs
INPUT VOLTAGE
100
VI = 3.3 V
IO = 200 mA
IO = 10 mA
90
VI = 2.4 V
80
90
Efficiency - %
Efficiency - %
70
60
50
40
IO = 100 mA
80
30
70
20
VO = 5 V
10
0
0.1
1
10
100
60
1.8
1000
IO - Output Current - mA
2.2
2.4
2.6
2.8
VI - Input Voltage - V
Figure 5.
Figure 6.
TPS61121
BOOST CONVERTER OUTPUT VOLTAGE
vs
OUTPUT CURRENT
TPS61121
NO-LOAD SUPPLY CURRENT INTO VBAT
vs
INPUT VOLTAGE
No-Load Supply Current Into VBAT - µ A
VI = 2.4 V
3.38
3.36
VO - Output Voltage - V
3
3.2
14
3.40
3.34
3.32
3.30
3.28
3.26
3.24
3.22
3.20
2
0
200
400
600
IO - Output Current - mA
Figure 7.
800
85°C
12
25°C
10
-40°C
8
6
4
2
0
1.8
2
2.2
2.4
2.6
2.8
VI - Input Voltage - V
3
3.2
Figure 8.
9
TPS61120
TPS61122, TPS61121
www.ti.com
SLVS427C – JUNE 2002 – REVISED APRIL 2004
TPS61121
NO-LOAD SUPPLY CURRENT INTO VOUT
vs
INPUT VOLTAGE
TPS61121
BOOST CONVERTER OUTPUT VOLTAGE
IN CONTINUOUS MODE
No-Load Supply Current Into VOUT - µ A
14
VI = 2.4 V, RL = 33 85°C
12
Output Voltage
20 mV/Div, AC
25°C
-40°C
10
8
6
Inductor Current
200 mA/Div, DC
4
2
0
VO = 3.3 V
1.8
2
2.2
2.4
2.6
2.8
VI - Input Voltage - V
3
Timebase - 1 µs/Div
3.2
Figure 9.
Figure 10.
TPS61121
BOOST CONVERTER OUTPUT VOLTAGE IN POWER
SAVE MODE
TPS61121
BOOST CONVERTER LOAD TRANSIENT RESPONSE
VI = 2.4 V, RL = 330 Output Voltage
50 mV/Div, AC
VI = 2.4 V,
IL = 80 mA to 160 mA
Output Current
100 mA/Div, DC
Output Voltage
20 mV/Div, AC
Inductor Current
200 mA/Div, DC
VO = 3.3 V
VO = 3.3 V
Timebase - 200 µs/Div
Figure 11.
10
Timebase - 500 µs/Div
Figure 12.
TPS61120
TPS61122, TPS61121
www.ti.com
SLVS427C – JUNE 2002 – REVISED APRIL 2004
TPS61121
BOOST CONVERTER LINE TRANSIENT RESPONSE
VI = 2.0 V to 2.4 V
RL = 33 TPS61121
BOOST CONVERTER START-UP AFTER ENABLE
Input Voltage
500 mV/Div, DC
Enable
5 V/Div, DC
Output Voltage
2 V/Div, DC
Voltage at SW
2 V/Div, DC
Output Voltage
50 mV/Div, AC
Input Current
500 mV/Div, DC
VI = 2.4 V, RL = 33 VO = 3.3 V
VO = 3.3 V
Timebase - 200 µs/Div
Timebase - 400 µs/Div
Figure 13.
Figure 14.
TPS61120
MAXIMUM LDO OUTPUT CURRENT
vs
LDO INPUT VOLTAGE
TPS61120
MAXIMUM LDO OUTPUT CURRENT
vs
LDO INPUT VOLTAGE
400
400
VO = 1.5 V
350
350
Maximum LDO Output Current - mA
Maximum LDO Output Current - mA
VO = 3.3 V
300
250
VO = 2.5 V
200
150
100
50
300
250
VO = 1.8 V
200
150
100
50
0
0
2.5
3
3.5
4
4.5
5
5.5
LDO Input Voltage - V
Figure 15.
6
6.5
7
1.5 2
2.5
3 3.5 4 4.5 5 5.5 6
LDO Input Voltage - V
6.5 7
Figure 16.
11
TPS61120
TPS61122, TPS61121
www.ti.com
SLVS427C – JUNE 2002 – REVISED APRIL 2004
TPS61122
LDO OUTPUT VOLTAGE
vs
LDO OUTPUT CURRENT
LDO DROPOUT VOLTAGE
vs
LDO OUTPUT CURRENT
3.5
3.4
3.38
3
LDO Dropout Voltage - V
LDO Output Voltage - V
3.36
3.34
3.32
3.3
3.28
3.26
TPS61121
(LDO OUTPUT
VOLTAGE 1.5 V)
2.5
2
TPS61122
(LDO OUTPUT
VOLTAGE 3.3 V)
1.5
1
3.24
0.5
3.22
0
3.2
0
50
100 150 200 250 300
LDO Output Current - mA
350
10
400
60
110
160
210
260
LDO Output Current - mA
Figure 17.
Figure 18.
TPS61121
SUPPLY CURRENT INTO LDOIN
vs
LDO INPUT VOLTAGE
TPS61121
PSRR
vs
FREQUENCY
310
20
LDOIN = 3.3 V
70
25°C
60
LDO Output Current 10 mA
15
PSRR - dB
Supply Current Into LDOIN - µ A
80
85°C
-40°C
10
50
40
30
LDO Output Current 200 mA
20
5
10
0
1.8
2
2.2
2.4
2.6
2.8
LDOIN Input Voltage - V
Figure 19.
12
3
3.2
0
1k
10k
100k
f - Frequency - Hz
Figure 20.
1M
10M
TPS61120
TPS61122, TPS61121
www.ti.com
SLVS427C – JUNE 2002 – REVISED APRIL 2004
TPS61121
LDO LOAD TRANSIENT RESPONSE
VI = 3.3 V
IL = 20 mA to 180 mA
Output Current
100 mA/Div, DC
TPS61121
LDO LINE TRANSIENT RESPONSE
VI = 1.8 V to 2.6 V
RL = 15 Input Voltage
1 V/Div, DC
Output Voltage
10 mV/Div, AC
Output Voltage
20 mV/Div, AC
VO = 1.5 V
VO = 1.5 V
Timebase - 500 µs/Div
Timebase - 2 ms/Div
Figure 21.
Figure 22.
TPS61121
LDO START-UP AFTER ENABLE
VI = 3.3 V
RL = 15 LDO-Enable
5 V/Div, DC
LDO-Output Voltage
1 V/Div, DC
Input Current
200 mA/Div, DC
VO = 1.5 V
Timebase - 20 µs/Div
Figure 23.
13
TPS61120
TPS61122, TPS61121
www.ti.com
SLVS427C – JUNE 2002 – REVISED APRIL 2004
APPLICATION INFORMATION
DESIGN PROCEDURE
The TPS6112x dc/dc converters are intended for systems powered by a dual or triple cell NiCd or NiMH battery
with a typical terminal voltage between 1.8 V and 5.5 V. They can also be used in systems powered by one-cell
Li-Ion with a typical stack voltage between 2.5 V and 4.2 V. Additionally, two or three primary and secondary
alkaline battery cells can be the power source in systems where the TPS6112x is used.
Programming the Output Voltage
DC/DC Converter
The output voltage of the TPS61120 dc/dc converter section can be adjusted with an external resistor divider.
The typical value of the voltage on the FB pin is 500 mV. The maximum allowed value for the output voltage is
5.5 V. The current through the resistive divider should be about 100 times greater than the current into the FB
pin. The typical current into the FB pin is 0.01 µA and the voltage across R6 is typically 500 mV. Based on those
two values, the recommended value for R6 should be lower than 500 kΩ, in order to set the divider current at 1
µA or higher. Because of internal compensation circuitry the value for this resistor should be in the range of 200
kΩ. From that, the value of resistor R3, depending on the needed output voltage (VO), can be calculated using
Equation 1:
V
V
O –1 180 k O –1
R3 R6 V
500 mV
FB
(1)
If as an example, an output voltage of 3.3 V is needed, a 1-MΩ resistor should be chosen for R3. If for any
reason the value for R6 is chosen significantly lower than 200 kΩ additional capacitance in parallel to R3 is
recommended. The required capacitance value can be easily calculated using Equation 2.
C
parR3
20 pF 200 k 1
R6
(2)
U1
L1
10 µH
Power
Supply
C3
10 µF
SWN
SWP
VBAT
R3
C6
2.2 µF
FB
LBI
R2
LDOIN
SKIPEN
R6
LDOOUT
C5
2.2 µF
R5
LDOSENSE
EN
R4
LDOEN
GND
VCC1
Boost Output
C4
100 µF
VOUT
R1
R7
VCC2
LDO Output
R9
LBO
PGOOD
PGND
Control
Outputs
TPS6112xPW
Figure 24. Typical Application Circuit for Adjustable Output Voltage Option
14
TPS61120
TPS61122, TPS61121
www.ti.com
SLVS427C – JUNE 2002 – REVISED APRIL 2004
LDO
Programming the output voltage at the LDO follows almost the same rules as in the dc/dc converter section. The
maximum programmable output voltage at the LDO is 5.5 V. Since reference and internal feedback circuitry are
similar, as they are at the boost converter section, R4 also should be in the 200-kΩ range. The calculation of the
value of R5 can be done using the following Equation 3:
V
V
O –1 180 k O –1
R5 R4 V
500 mV
FB
(3)
If as an example, an output voltage of 1.5 V is needed, a 360 kΩ-resistor should be chosen for R5.
Programming the LBI/LBO Threshold Voltage
The current through the resistive divider should be about 100 times greater than the current into the LBI pin. The
typical current into the LBI pin is 0.01 µA, and the voltage across R2 is equal to the LBI voltage threshold that is
generated on-chip, which has a value of 500 mV. The recommended value for R2is therefore in the range of 500
kΩ. From that, the value of resistor R1, depending on the desired minimum battery voltage VBAT, can be
calculated using Equation 4.
R1 R2 V
V
BAT
LBIthreshold
1
390 k V
BAT 1
500 mV
(4)
The output of the low battery supervisor is a simple open-drain output that goes active low if the dedicated
battery voltage drops below the programmed threshold voltage on LBI. The output requires a pullup resistor with
a recommended value of 1 MΩ. The maximum voltage which is used to pull up the LBO outputs should not
exceed the output voltage of the dc/dc converter. If not used, the LBO pin can be left floating or tied to GND.
Inductor Selection
A boost converter normally requires two main passive components for storing energy during the conversion. A
boost inductor and a storage capacitor at the output are required. To select the boost inductor, it is
recommended to keep the possible peak inductor current below the current limit threshold of the power switch in
the chosen configuration. For example, the current limit threshold of the TPS6112x's switch is 1600 mA at an
output voltage of 3.3 V. The highest peak current through the inductor and the switch depends on the output
load, the input (VBAT), and the output voltage (VOUT). Estimation of the maximum average inductor current can be
done using Equation 5:
V
OUT
I I
L
OUT V
0.8
BAT
(5)
For example, for an output current of 250 mA at 3.3 V, at least 575 mA of current flows through the inductor at a
minimum input voltage of 1.8 V.
The second parameter for choosing the inductor is the desired current ripple in the inductor. Normally, it is
advisable to work with a ripple in the range of 20% of the average inductor current. A smaller ripple reduces the
magnetic hysteresis losses in the inductor, as well as output voltage ripple and EMI. But in the same way,
regulation time at load changes rises. In addition, a larger inductor increases the total system costs. With those
parameters, it is possible to calculate the value for the inductor by using Equation 6:
V
L
V
–V
BAT
OUT BAT
I ƒ V
L
OUT
(6)
Parameter f is the switching frequency and ∆ IL is the ripple current in the inductor, i.e., 20% × IL. In this example,
the desired inductor value is in the range of 14 µH. In typical applications a 10 µH inductor is recommended. The
minimum possible inductor value is 4.7 µH. With the calculated inductance value and current, it is possible to
choose a suitable inductor. Care has to be taken that load transients and losses in the circuit can lead to higher
currents as estimated in Equation 5. Also, the losses in the inductor caused by magnetic hysteresis losses and
copper losses are a major parameter for total circuit efficiency.
The following inductor series from different suppliers have been used with the TPS6112x converters:
15
TPS61120
TPS61122, TPS61121
www.ti.com
SLVS427C – JUNE 2002 – REVISED APRIL 2004
List of Inductors
VENDOR
RECOMMENDED INDUCTOR SERIES
CDRH5D18
Sumida
CDRH6D28
Wurth Electronik
7447789___
7447779___
DR73
Coiltronics
DR74
TDK
SLF 7032
EPCOS
B82462G
Capacitor Selection
Input Capacitor
At least a 10-µF input capacitor is recommended to improve transient behavior of the regulator and EMI behavior
of the total power supply circuit. A ceramic capacitor or a tantalum capacitor with a 100-nF ceramic capacitor in
parallel, placed close to the IC, is recommended.
Output Capacitor DC/DC Converter
The major parameter necessary to define the output capacitor is the maximum allowed output voltage ripple of
the converter. This ripple is determined by two parameters of the capacitor, the capacitance and the ESR. It is
possible to calculate the minimum capacitance needed for the defined ripple, supposing that the ESR is zero, by
using Equation 7:
I
C
min
V
V
OUT
OUT
BAT
ƒ V V
OUT
(7)
Parameter f is the switching frequency and ∆V is the maximum allowed ripple.
With a chosen ripple voltage of 10 mV, a minimum capacitance of 22 µF is needed. The total ripple is larger due
to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 8:
V
I
R
ESR
OUT
ESR
(8)
An additional ripple of 20 mV is the result of using a tantalum capacitor with a low ESR of 80 mΩ. The total ripple
is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the capacitor. In this
example, the total ripple is 30 mV. Additional ripple is caused by load transients. This means that the output
capacitance needs to be larger than calculated above to meet the total ripple requirements. The output capacitor
has to completely supply the load during the charging phase of the inductor. A reasonable value of the output
capacitance depends on the speed of the load transients and the load current during the load change. In typical
applications a 100 µF capacitance is recommended. For economical reasons this usually is a tantalum capacitor.
Because of this the control loop has been optimized for using output capacitors with an ESR of above 30 mΩ.
The minimum value for the output capacitor is 22 µF.
Small Signal Stability
When using output capacitors with lower ESR, like ceramics, it is recommended to use the adjustable voltage
version. The missing ESR can be easily compensated there in the feedback divider. Typically a capacitor in the
range of 10 pF in parallel with R3 helps to obtain small signal stability, with the lowest ESR output capacitors.
For more detailed analysis the small signal transfer function of the error amplifier and regulator, which is given in
Equation 9, can be used.
10 (R3 R6)
A
d REG
V
R6 (1 i 1.6 s)
FB
(9)
16
TPS61120
TPS61122, TPS61121
www.ti.com
SLVS427C – JUNE 2002 – REVISED APRIL 2004
Output Capacitor LDO
To ensure stable output regulation, it is required to use an output capacitor at the LDO output. Ceramic
capacitors in the range from 1 µF up to 4.7 µF is recommended. At 4.7 µF and above it is recommended to use
standard ESR tantalum. There is no maximum capacitance value.
DETAILED DESCRIPTION
Controller Circuit
The controller circuit of the device is based on a fixed frequency multiple feedforward controller topology. Input
voltage, output voltage, and voltage drop on the NMOS switch are monitored and forwarded to the regulator. So
changes in the operating conditions of the converter directly affect the duty cycle and must not take the indirect
and slow way through the control loop and the error amplifier. The control loop, determined by the error amplifier,
only has to handle small signal errors. The input for it is the feedback voltage on the FB pin or, at fixed output
voltage versions, the voltage on the internal resistor divider. It is compared with the internal reference voltage to
generate an accurate and stable output voltage.
The peak current of the NMOS switch is also sensed to limit the maximum current flowing through the switch and
the inductor. The typical peak current limit is set to 1300 mA. An internal temperature sensor prevents the device
from getting overheated in case of excessive power dissipation.
Synchronous Rectifier
The device integrates an N-channel and a P-channel MOSFET transistor to realize a synchronous rectifier.
Because the commonly used discrete Schottky rectifier is replaced with a low RDS(ON) PMOS switch, the power
conversion efficiency reaches 95%. To avoid ground shift due to the high currents in the NMOS switch, two
separate ground pins are used. The reference for all control functions is the GND pin. The source of the NMOS
switch is connected to PGND. Both grounds must be connected on the PCB at only one point close to the GND
pin. A special circuit is applied to disconnect the load from the input during shutdown of the converter. In
conventional synchronous rectifier circuits, the backgate diode of the high-side PMOS is forward biased in
shutdown and allows current flowing from the battery to the output. This device however uses a special circuit
which takes the cathode of the backgate diode of the high-side PMOS and disconnects it from the source when
the regulator is not enabled (EN = low).
The benefit of this feature for the system design engineer is that the battery is not depleted during shutdown of
the converter. No additional components have to be added to the design to make sure that the battery is
disconnected from the output of the converter.
Power Save Mode
The SKIPEN pin can be used to select different operation modes. To enable the Power save mode, SKIPEN
must be set high. Power save mode is used to improve efficiency at light loads. In power save mode, the
converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output
voltage with several pulses, and goes again into power save mode once the output voltage exceeds the set
threshold voltage. The skip mode can be disabled by setting the SKIPEN to GND.
LDO
The built-in LDO can be used to generate a second output voltage derived from the dc/dc converter output, from
the battery, or from another power source like an ac adapter or a USB power rail. The LDO is capable of being
back biased. This allows the user to just connect the outputs of dc/dc converter and LDO. So the device is able
to supply the load via dc/dc converter when the energy comes from the battery and efficiency is most important
and from another external power source via the LDO when lower efficiency is not critical. The LDO must be
disabled if the LDOIN voltage drops below LDOOUT to block reverse current flowing. The status of the dc/dc
stage (enabled or disabled) does not matter.
Device Enable
The device is put into operation when EN is set high. It is put into a shutdown mode when EN is set to GND. In
shutdown mode, the regulator stops switching, all internal control circuitry including the low-battery comparator is
switched off, and the load is isolated from the input (as described in the Synchronous Rectifier Section). This
also means that the output voltage can drop below the input voltage during shutdown.
17
TPS61120
TPS61122, TPS61121
SLVS427C – JUNE 2002 – REVISED APRIL 2004
www.ti.com
DETAILED DESCRIPTION (continued)
Undervoltage Lockout
An undervoltage lockout function prevents device start-up if the supply voltage on VBAT is lower than
approximately 1.6 V. When in operation and the battery is being discharged, the device automatically enters the
shutdown mode if the voltage on VBAT drops below approximately 1.6 V. This undervoltage lockout function is
implemented in order to prevent the malfunctioning of the converter.
Softstart
During start-up of the converter, the duty cycle and the peak current are limited in order to avoid high peak
currents drawn from the battery. When the boost section is enabled, the internal startup cycle starts with the first
step, the precharge phase. During precharge, the rectifying switch is turned on until the output capacitor is
charged to a value close to the input voltage. The rectifying switch current is limited in that phase. This also limits
the output current under short-circuit conditions at the output. After charging the output capacitor to the input
voltage the device starts switching. Until the output voltage is reached, the boost switch current limit is set to
40% of its nominal value to avoid high peak currents at the battery during startup. When the output voltage is
reached, the regulator takes control and the switch current limit is set back to 100%.
LDO Enable
The LDO can be separately enabled and disabled by using the LDOEN pin in the same way as the EN pin at the
dc/dc converter stage described above. This is completely independent of the status of the EN pin. The voltage
levels of the logic signals which need to be applied at LDOEN are related to LDOIN.
Power Good
The PGOOD pin stays high impedance when the dc/dc converter delivers an output voltage within a defined
voltage window. So it can be used to enable any connected circuitry such as cascaded converters (LDO) or to
reset microprocessor circuits.
Low Battery Detector Circuit—LBI/LBO
The low-battery detector circuit is typically used to supervise the battery voltage and to generate an error flag
when the battery voltage drops below a user-set threshold voltage. The function is active only when the device is
enabled. When the device is disabled, the LBO pin is high-impedance. The switching threshold is 500 mV at LBI.
During normal operation, LBO stays at high impedance when the voltage, applied at LBI, is above the threshold.
It is active low when the voltage at LBI goes below 500 mV.
The battery voltage, at which the detection circuit switches, can be programmed with a resistive divider
connected to the LBI pin. The resistive divider scales down the battery voltage to a voltage level of 500 mV,
which is then compared to the LBI threshold voltage. The LBI pin has a built-in hysteresis of 10 mV. See the
application section for more details about the programming of the LBI threshold. If the low-battery detection
circuit is not used, the LBI pin should be connected to GND (or to VBAT) and the LBO pin can be left
unconnected. Do not let the LBI pin float.
Low-EMI Switch
The device integrates a circuit that removes the ringing that typically appears on the SW node when the
converter enters discontinuous current mode. In this case, the current through the inductor ramps to zero and the
rectifying PMOS switch is turned off to prevent a reverse current flowing from the output capacitors back to the
battery. Due to the remaining energy that is stored in parasitic components of the semiconductor and the
inductor, a ringing on the SW pin is induced. The integrated antiringing switch clamps this voltage to VBAT and
therefore dampens ringing.
18
TPS61120
TPS61122, TPS61121
www.ti.com
SLVS427C – JUNE 2002 – REVISED APRIL 2004
LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.
The feedback divider should be placed as close as possible to the control ground pin of the IC. To lay out the
control ground, it is recommended to use short traces as well, separated from the power ground traces. This
avoids ground shift problems, which can occur due to superimposition of power ground current and control
ground current.
APPLICATION EXAMPLES
U1
L1
10 µH
SWN
SWP
VBAT
VOUT
C6
2.2 µF
R1
C3
10 µF
LBI
R2
3.3 V,
>250 mA
LDOIN
SKIPEN
LDOOUT
C5
2.2 µF
LDOSENSE
EN
R7
List of Components:
U1 = TPS61121PW
L1 = Sumida CDRH73–100
C3, C5, C6 = X7R/X5R Ceramic
C4 = Low ESR Tantalum
C4
100 µF
LDOEN
GND
LBO
PGOOD
PGND
1.5 V,
>120 mA
R9
LBO
PGOOD
TPS61121PW
Figure 25. Solution for Maximum Output Power
19
TPS61120
TPS61122, TPS61121
www.ti.com
SLVS427C – JUNE 2002 – REVISED APRIL 2004
APPLICATION INFORMATION
U1
L1
SWN
SWP
VBAT
10 µH
3.3 V
VOUT
C6
2.2 µF
R1
C3
10 µF
LBI
R2
C4
100 µF
LDOIN
SKIPEN
1.5 V
LDOOUT
C5
2.2 µF
LDOSENSE
EN
R7
List of Components:
U1 = TPS61121PW
L1 = Sumida 5D18−100
C3, C5, C6 = X7R/X5R Ceramic
C4 = Low ESR, Low Profile Tantalum
LDOEN
GND
R9
LBO
LBO
PGOOD
PGND
PGOOD
TPS61121PW
Figure 26. Low Profile Solution, Maximum Height 1,8 mm
6V
C7
U1
0.1 µF
L1
10 µH
C3
10 µF
SWN
SWP
VBAT
C8
1 µF
VOUT
3.3 V
C6
2.2 µF
R1
LBI
R2
C4
100 µF
LDOIN
SKIPEN
1.5 V
LDOOUT
C5
2.2 µF
LDOSENSE
EN
List of Components:
U1 = TPS61121PW
L1 = Sumida CDRH73−100
C3, C5, C6,
C7, C8 = X7R/X5R Ceramic
C4 = Low ESR Tantalum
DS1 = BAT54S
DS1
R7
LDOEN
GND
R9
LBO
PGOOD
PGND
TPS61121PW
Figure 27. Dual Power Supply With Auxiliary Positive Output Voltage
20
LBO
PGOOD
TPS61120
TPS61122, TPS61121
www.ti.com
SLVS427C – JUNE 2002 – REVISED APRIL 2004
APPLICATION INFORMATION (continued)
−3 V
C7
U1
C8
1 µF
0.1 µF
L1
10 µH
DS1
SWN
SWP
VBAT
VOUT
3.3 V
C6
2.2 µF
R1
C3
10 µF
LBI
R2
LDOIN
SKIPEN
1.5 V
LDOOUT
C5
2.2 µF
LDOSENSE
EN
R7
List of Components:
U1 = TPS61121PW
L1 = Sumida CDRH73−100
C3, C5, C6,
C7, C8 = X7R/X5R Ceramic
C4 = Low ESR Tantalum
DS1 = BAT54S
C4
100 µF
LDOEN
GND
R9
LBO
LBO
PGOOD
PGND
PGOOD
TPS61121PW
Figure 28. Dual Power Supply With Auxiliary Negative Output Voltage
U1
L1
10 µH
C3
10 µF
SWN
SWP
VBAT
VOUT
R3
R1
C6
22 µF
FB
LBI
R6
R2
SKIPEN
LDOIN
LDOOUT
3.3 V
R5
C5
2.2 µF
LDOSENSE
EN
R4
List of Components:
U1 = TPS61121PW
L1 = Sumida CDRH73−100
C3, C5 = X7R/X5R Ceramic
C6 = X7R/X5R Ceramic or Low
ESR Tantalum
LDOEN
GND
LBO
PGOOD
PGND
R7
R9
LBO
PGOOD
TPS61121PW
Figure 29. Single Output Using LDO as Filter
21
TPS61120
TPS61122, TPS61121
www.ti.com
SLVS427C – JUNE 2002 – REVISED APRIL 2004
APPLICATION INFORMATION (continued)
USB Input
4.2 V...5.5 V
D1
U1
L1
10 µH
C3
10 µF
SWN
SWP
VBAT
R3
1 MΩ
R1
FB
LBI
LDOIN
R2
SYNC
LDOOUT
LDOSENSE
EN
List of Components:
U1 = TPS61120PW
L1 = Sumida CDRH73–100
C3, C5, C6 = X7R/X5R Ceramic
C4 = Low ESR Tantalum
D1 = On-Semiconductor MBR0520
VOUT
R5
1.022 MΩ
R7
LBO
GND
C4
100 µF
R6
180 kΩ
R4
180 kΩ
LDOEN
C6
2.2 µF
VCC
3.3 V System Supply
PGOOD
PGND
R8
Control
Outputs
TPS61120PW
Figure 30. Dual Input Power Supply Solution
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the
power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below.
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow in the system
The maximum junction temperature (TJ) of the TPS6112x devices is 150 °C. The thermal resistance of the 16-pin
TSSOP package (PW) is RΘJA = 155 °C/W. The 16-pin QFN PowerPAD package (RSA) has a thermal resistance
of RΘJA = 38.1 °C/W, if the PowerPAD is soldered and the board layout is optimized. Specified regulator
operation is assured to a maximum ambient temperature TA of 85°C. Therefore, the maximum power dissipation
is about 420 mW for the TSSOP (PW) package and 1700 mW for the QFN (RSA) package; See Equation 10.
More power can be dissipated if the maximum ambient temperature of the application is lower.
T
T
J(MAX)
A
P
150 °C 85°C 420 mW
D(MAX)
R
155 °CW
JA
(10)
If designing for a lower junction temperature of 125°C, which is recommended, maximum heat dissipation is
lower. Using the above Equation 10 results in 1050 mW power dissipation for the RSA package and 260mW for
the PW package.
22
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2004, Texas Instruments Incorporated