TI UCD8220PWPR

UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
DIGITALLY MANAGED PUSH-PULL ANALOG PWM CONTROLLERS
FEATURES
•
•
•
•
•
•
•
•
•
•
For Digitally Managed Power Supplies Using
µCs or the TMS320 ™ DSP Family
Voltage or Peak Current Mode Control with
Cycle-by-Cycle Current Limiting
Clock input from Digital Controller to set
Operating Frequency and Max Duty Cycle
Analog PWM Comparator
2-MHz Switching Frequency
110-V Input Startup Circuit and Thermal
Shutdown (UCD8620)
Internal Programmable Slope Compensation
3.3-V, 10-mA Linear Regulator
DSP/µC Compatible Inputs
Dual ±4-A TrueDrive™ High Current Drivers
•
•
•
•
•
•
•
10-ns Typical Rise and Fall Times with 2.2-nF
25-ns Input-to-Output Propagation Delay
25-ns Current Sense-to-Output Propagation
Delay
Programmable Current Limit Threshold
Digital Output Current Limit Flag
4.5-V to 15.5-V Supply Voltage Range
Rated from -40°C to 105°C
APPLICATIONS
•
•
•
Digitally Managed Switch Mode Power
Supplies
Push-Pull, Half-Bridge, or Full-Bridge
Converters
Battery Chargers
DESCRIPTION
The UCD8220 and UCD8620 are members of the UCD8K family of analog pulse-width modulator devices to be
used in digitally managed power supplies using a microcontroller or the TMS320™ DSP family.
UCD8220 and UCD8620 are double-ended PWM controllers configured with push-pull drive logic. The UCD8620
has a 110-V high-voltage startup circuit which can directly start up the controller from a 48-V telecom input line.
Systems using UCD8K devices close the PWM feedback loop with traditional analog methods, but the UCD8K
controllers include circuitry to interpret a time-domain digital pulse train. The pulse train contains the operating
frequency and maximum duty cycle limit which are used to control the power supply operation. This eases
implementation of a converter with high level control features without the added complexity or possible PWM
resolution limitations of closing the control loop in the discrete time domain.
Figure 1. UCD8220 Typical Simplified Push-Pull Converter Application Schematic
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320, TrueDrive, PowerPAD are trademarks of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
DESCRIPTION (continued)
The UCD8220 and UCD8620 can be configured for either peak current mode or voltage mode control. They
provide a programmable current limit function and a digital output current limit flag which can be monitored by the
host controller to set the current limit operation. For fast switching speeds, the output stages use the TrueDrive™
architecture, which delivers rated current of ±4 A into the gate of a MOSFET. Finally they also include a 3.3-V,
10-mA linear regulator to provide power to the digital controller or act as a reference in the system.
The UCD8K controller family is compatible with the standard 3.3-V I/O ports of UCD9K digital power controllers,
DSPs, Microcontrollers, or ASICs and is offered in PowerPAD™ HTSSOP and QFN packages.
SIMPLIFIED APPLICATION DIAGRAMS
Figure 2. UCD8220 Typical Simplified Half-Bridge Converter Application Schematic
2
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
SIMPLIFIED APPLICATION DIAGRAMS (continued)
Figure 3. UCD8620 Typical Simplified Push-Pull Converter Application Schematic
Figure 4. UCD8620 Typical Simplified Half-Bridge Converter Application Schematic
3
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
CONNECTION DIAGRAMS
HTSSOP PACKAGE (PWP −16)
UCD8220 (TOP VIEW)
HTSSOP PACKAGE (PWP −16)
UCD8620 (TOP VIEW)
VIN
NC
VDD
PVDD
OUT1
OUT2
PGND
CS
16
15
14
13
12
11
10
9
NC
CLK
3V3
ISET
AGND
CTRL
CLF
ILIM
QFN PACKAGE (RGW−20)
UCD8620 (BOTTOM VIEW)
19
7
18
8
17
9
CLK
1
16
NC
NC
VDD
VDD
PVDD
OUT1
OUT2
PGND
16
10
15 14 13 12 11
NC
ILIM
NC
CS
NC
2
3
4
5
CLF
15
6
ILIM
14
7
NC
8
CS
13
12
11
10
9
PGND
6
CTRL
3V3
5
AGND
4
OUT2
3
20
ISET
2
NC
NC
VDD
PVDD
OUT1
OUT2
PGND
CS
QFN PACKAGE (RSA−16)
UCD8220 (BOTTOM VIEW)
3V3
ISET
AGND
CTRL
CLF
1
16
15
14
13
12
11
10
9
NC − No internal connection
NC − No internal connection
CLK
NC
NC
VIN
NC
1
2
3
4
5
6
7
8
OUT1
1
2
3
4
5
6
7
8
PVDD
NC
CLK
3V3
ISET
AGND
CTRL
CLF
ILIM
ORDERING INFORMATION
TEMPERATURE RANGE
-40°C to 105°C
(1)
(2)
(3)
(4)
(5)
4
110-V HV STARTUP
CIRCUIT
PACKAGED DEVICES (1) (2) (3)
PowerPAD™
HTSSOP-16 (PWP)
QFN-16 (RSA) (4)
No
UCD8220PWP
UCD8220RSA
-
Yes
UCD8620PWP (5)
-
UCD8620RGW
QFN-20 (RGW)
HTSSOP-16 (PWP), QFN-16 (RSA), and QFN-20 (RGW) packages are available taped and reeled. Add R suffix to device type (e.g.
UCD8620PWPR) to order quantities of 2,000 devices per reel for the PWP package and 1,000 devices per reel for the RSA and RGW
packages.
These products are packaged in Pb-Free and Green lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C
peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
Contact factory for availability of QFN packaging.
Product preview stage of development.
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
PACKAGING INFORMATION
(1)
PACKAGE
SUFFIX
θJC(°C/W)
θJA(°C/W)
POWER RATING TA
= 70°C, TJ = 125°C
(mW)
RATING FACTOR
ABOVE 70°C
(mW/°C)
PowerPad™
MSSOP-16
PWP
2.07
37.47 (1)
1470
27
QFN-16
RSA
-
-
-
-
QFN-20
RGW
-
-
-
-
PowerPad™ soldered to the PWB with TI recommended PWB as defined in TI's Application Report ( TI Literature Number SLMA002)
with OLFM.
ABSOLUTE MAXIMUM RATINGS (1) (2)
SYMBOL
PARAMETER
UCD8x20
UCD8620 only
110
VI
Input Line Voltage
VDD
Supply Voltage
IDD
Supply Current
VO
Output Gate Drive Voltage
OUT
Output Gate Drive Current
OUT
Analog Input
ISET, CS, CTRL, ILIM
-0.3 to 3.6
Digital I/O’s
CLK, CLF
-0.3 to 3.6
IO(sink)
IO(source)
Power Dissipation
16
Quiescent
20
Switching, TA = 25°C, TJ = 125°C, VDD = 12 V
200
TJ
Tstg
Storage Temperature
HBM
CDM
ESD Rating (3)
2.67
TA = 25°C (QFN-16 package)
-
(2)
(3)
V
mA
V
A
V
W
-
UCD8220
-55 to 150
UCD8620
-55 to 130
°C
-65 to 150
Human body model
2000
Change device model
500
Lead Temperature (Soldering, 10 sec)
(1)
4.0
-4.0
TA = 25°C (PWP-16 package)
TA = 25°C (QFN-20 package)
Junction Operating
Temperature
-1 to PVDD
UNIT
300
V
°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.
Tested to JEDEC standard EIA/JESD22 - A114-B.
5
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS
VDD = 12 V, 4.7-µF capacitor from VDD to AGND, 1 µF from PVDD to PGND, 0.22-µF capacitor from 3V3 to AGND,
TA = TJ = -40°C to 105°C, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UCD8620
500
800
UCD8220
300
500
UNIT
SUPPLY SECTION
Supply current, OFF
VDD = 4.2 V
Supply current, ON
(UCD8620), outputs not switching, CLK = low
2
3
(UCD8220), outputs not switching, CLK = low
2
3
µA
mA
LOW VOLTAGE UNDERVOLTAGE LOCKOUT (UCD8220 only)
VDD UVLO ON
4.25
4.5
4.75
VDD UVLO OFF
4.05
4.25
4.45
VDD UVLO hysteresis
150
250
350
12.5
13
13.5
7
7.5
8
JFET turn-off threshold (VSTART_JFET) No switching, JFET on at startup
12.5
13
13.5
JFET turn-on threshold
11.5
12
12.5
V
mV
110-V HIGH VOLTAGE UNDERVOLTAGE LOCKOUT AND JFET CONTROL (UCD8620 ONLY)
VDD UVLO ON
VDD UVLO OFF
No switching
JFET on/off hysteresis
1
VDD < 5 V, VIN = 18 V to 76 V
High voltage JFET current
Thermal shutdown, OFF
Thermal shutdown, ON
V
3
VDD = 12 V, VIN = 18 V to 76 V
(1)
(1)
5
8
10
VDD = 5 V to 12 V
130
145
160
VDD > 5 V
110
125
140
3.267
3.3
3.333
3.234
3.3
3.366
mA
°C
REFERENCE / EXTERNAL BIAS SUPPLY
3V3 initial set point
TA = 25°C, ILOAD = 0
3V3 set point over temperature
3V3 load regulation
ILOAD = 1 mA to 10 mA, VDD = 5 V
-
1
6.6
3V3 line regulation
VDD = 4.75 V to 12 V, ILOAD = 10 mA
-
1
6.6
Short circuit current
VDD = 4.75 to 12 V
11
20
35
3V3 OK threshold, ON
3.3 V rising
2.9
3.0
3.1
3V3 OK threshold, OFF
3.3 V falling
2.7
2.8
2.9
HIGH, positive-going input threshold
voltage (VIT+)
1.65
-
2.08
LOW negative-going input threshold
voltage (VIT-)
1.16
-
1.5
0.6
-
0.8
-
-
V
mV
mA
V
CLOCK INPUT (CLK)
Input voltage hysteresis,
(VIT+ - VIT-)
Frequency
Minimum allowable off time
OUTx = 1 MHz
(1)
V
2
MHz
20
ns
V
SLOPE COMPENSATION (ISET)
ISET Voltage
m, VSLOPE (I-Mode)
m, VSLOPE (V-Mode)
(1)
6
VISET , 3V3 = 3.3 V, +/-2%
1.78
1.84
1.90
RISET = 6.19 kΩ to AGND, CS = 0.25 V, CTRL = 2.5 V
1.48
2.12
2.76
RISET = 100 kΩ to AGND, CS = 0.25 V, CTRL = 2.5 V
0.099
0.142
0.185
RISET = 499 kΩ to AGND, CS = 0.25 V, CTRL = 2.5 V
0.019
0.028
0.037
RISET = 4.99 kΩ to 3V3, CTRL = 2.5 V
1.44
2.06
2.68
RISET = 100 kΩ to 3V3, CTRL = 2.5 V
0.079
0.114
0.148
RISET = 402 kΩ to 3v3, CTRL = 2.5 V
0.019
0.027
0.035
Ensured by design. Not 100% tested in production.
V/µs
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)
VDD = 12 V, 4.7-µF capacitor from VDD to AGND, 1 µF from PVDD to PGND, 0.22-µF capacitor from 3V3 to AGND,
TA = TJ = -40°C to 105°C, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISET resistor range
Current mode control; RISET connected to AGND
6.19
499
ISET resistor range
Voltage mode control; RISET connected to 3V3
4.99
402
ISET current range
Voltage mode control with Feed-Forward; RISET connected to
VIN
3.7
300
µA
0.6
V
kΩ
PWM
PWM offset at CTRL input
CTRL buffer
gain (1)
3V3 = 3.3 V +/-2%
0.45
Gain from CTRL to PWM comparator input
0.51
0.5
V/V
CURRENT LIMIT (ILIM)
ILIM internal current limit threshold
0.466
0.5
0.536
ILIM maximum current limit threshold ILIM = 3.3 V
ILIM = OPEN
0.975
1.025
1.075
V
ILIM current limit threshold
ILIM = 0.75 V
0.700
0.725
0.750
ILIM minimum current limit threshold
ILIM = 0.25 V
0.21
0.23
0.25
CLF output high level
CS > ILIM , ILOAD = -7 mA
2.64
-
-
CLF output low level
CS ≤ ILIM, ILOAD = 7 mA
-
-
0.66
Propagation delay from CLK to CLF
CLK rising to CLF falling after a current limit event
-
15
25
ns
Includes CS comp offset
5
25
50
mV
-
–1
-
µA
V
V
V
CURRENT SENSE COMPARATOR
Bias voltage
Input bias current
Propagation delay from CS to OUTx
ILIM = 0.5 V, measured on OUTx, CS = threshold + 60 mV
-
25
40
Propagation delay from CS to CLF
ILIM = 0.5 V, measured on CLF, CS = threshold + 60 mV
-
25
50
10
35
75
VDD = 12 V, CLK = high, OUTx = 5 V
-
4
-
VDD = 12 V, CLK = low, OUTx = 5 V
-
4
-
VDD = 4.75 V, CLK = high, OUTx = 0
-
2
-
ns
CURRENT SENSE DISCHARGE TRANSISTOR
Discharge resistance
CLK = low, resistance from CS to AGND
Ω
OUTPUT DRIVERS
Source current
Sink current
(2)
(2)
Source current (2)
Sink current
(2)
VDD = 4.75 V, CLK = low, OUTx = 4.75 V
-
3
-
Rise time, tR
CLOAD = 2.2 nF, VDD = 12 V
-
10
20
Fall time, tF
CLOAD = 2.2 nF, VDD = 12 V
-
10
15
Output with VDD < UVLO
VDD = 1.0 V, ISINK = 10 mA
-
0.8
1.2
CLOAD = open, VDD = 12 V, CLK rising, tD1
-
25
35
25
35
Propagation delay from CLK to OUTx
(2)
CLOAD = open, VDD = 12 V, CLK falling, tD2
A
ns
V
ns
Ensured by design. Not 100% tested in production.
VIT+
INPUT
VIT−
tF
tF
t D1
90%
t D2
OUTPUT
10%
Figure 5. Timing Diagram
7
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
FUNCTIONAL BLOCK DIAGRAMS
16 NC
NC 1
15 NC
CLK 2
3V3 3
14 VDD
3V3 Regulator
and
Reference
UVLO
13 PVDD
12 OUT1
DRIVE
LOGIC
11 OUT2
ISET 4
PWM
PWM
CTRL 6
10 PGND
AGND 5
CLF 7
ILIM 8
CURRENT
LIMIT
CURRENT
SENSE
9 CS
Figure 6. UCD8220
NC
1
110−V HV
Start−up
and
JFET Control
CLK 2
16 VIN
15 NC
14 VDD
3V3 3
3V3 Regulator
and
Reference
13 PVDD
UVLO
12 OUT1
DRIVE
LOGIC
ISET 4
PWM
11 OUT2
PWM
CTRL 6
10 PGND
AGND 5
CLF 7
ILIM 8
CURRENT
LIMIT
CURRENT
SENSE
Figure 7. UCD8620
8
9 CS
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
TERMINAL FUNCTIONS
PIN NUMBER
UCD8220
PIN NAME
HTSSOP-16
(PWP)
CLK
2
UCD8620
QFN-16
(RSA)
16
HTSSOP-16
(PWP)
2
I/O
FUNCTION
QFN-20
(RGW)
20
I
Clock. Input pulse train contains operating frequency and maximum duty
cycle limit. This pin is a high impedance digital input capable of accepting
3.3-V logic level signals up to 2 MHz. There is an internal Schmitt trigger
comparator which isolates the internal circuitry CLK 2 16 2 20 I from any
external noise.
CLF
7
5
7
5
O
Current limit flag. When the CS level is greater than the ILIM voltage minus
25 mV, the output driver is forced low and the current limit flag (CLF) is set
high. The CLF signal is latched high until the device receives the next rising
edge on the CLK pin. This signal is also used for the start-up handshaking
between the Digital controller and the analog controller
ISET
4
2
4
2
I
Pin for programming the current used to set the amount of slope compensation in Peak-Current Mode control or to set the frequency in voltage mode
control.
3V3
3
1
3
1
O
Regulated 3.3-V rail. The onboard linear voltage regulator is capable of
sourcing up to 10 mA of current. Place 0.22 µF of ceramic capacitance from
this pin to analog ground.
AGND
5
3
5
3
-
Analog ground return
ILIM
8
6
8
7
I
Current limit threshold set pin. The current limit threshold can be set to any
value between 0.25 V and 1.0 V. The default value while open is 0.5 V.
CTRL
6
4
6
4
I
Input for the error feedback voltage from the external error amplifier. This
input is multiplied by 0.5 and routed to the negative input of the PWM
comparator
NC
1, 15, 16
7, 14, 15
1, 15
6, 8, 10,
16, 18, 19
-
No connection.
CS
9
8
9
9
I
Current sense pin. Fast current limit comparator connected to the CS pin is
used to protect the power stage by implementing cycle-by-cycle current
limiting.
10
9
10
11
-
Power ground return. This pin should be connected close to the source of the
power MOSFET.
OUT2
11
10
11
12
O
The high-current TrueDrive™ driver output.
OUT1
12
11
12
13
O
The high-current TrueDrive™ driver output.
PVDD
13
12
13
14
VDD
14
13
14
15
I
-
-
16
17
I
PGND
VIN
Supply pin provides power for the output drivers. It is not connected internally
to the VDD supply rail. The bypass capacitor for this pin should be returned to
PGND.
Supply input pin to power the control circuitry. Bypass the pin with at least
4.7 µF of capacitance, returned to AGND.
Input to the internal start-up circuitry rated to 110 V. This pin connects directly
to the input power rail.
9
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS
UCD8220
UVLO THRESHOLD
vs
TEMPERATURE
UCD8620
UVLO THRESHOLD
vs
TEMPERATURE
5.0
5.0
UVLO on
UVLO on
4.5
4.5
4.0
UVLO off
VUVLO − UVLO Thresholds − V
VUVLO − UVLO Thresholds − V
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
−50
UVLO hysteresis
−25
0
3.0
50
75
100
2.0
1.5
1.0
0.0
−50
125
TBD
2.5
0.5
25
UVLO off
3.5
UVLO hysteresis
0
−25
t − Temperature − °C
Figure 9.
3V3 REFERENCE VOLTAGE
vs
TEMPERATURE
3V3 SHORT-CIRCUIT CURRENT
vs
TEMPERATURE
100
125
23.0
ISHORT_CKT − Short Circuit Current − mA
3V3 − Reference Voltage − V
75
Figure 8.
3.34
3.32
3.30
3.28
3.26
22.5
22.0
VDD = 4.75 V
21.5
VDD = 12 V
21.0
20.5
20.0
3.24
−25
0
25
50
75
t − Temperature − °C
Figure 10.
10
50
t − Temperature − °C
3.36
−50
25
100
125
−50
−25
0
25
50
75
t − Temperature − °C
Figure 11.
100
125
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
vs
FREQUENCY (VDD = 5 V)
SUPPLY CURRENT
vs
FREQUENCY (VDD = 8 V)
160
280
240
IDD − Supply Current − mA
IDD − Supply Current − mA
140
CLOAD = 10 nF
120
100
80
CLOAD = 4.7 nF
60
40
CLOAD = 2.2 nF
CLOAD = 10 nF
200
160
CLOAD = 4.7 nF
120
80
CLOAD = 2.2 nF
40
20
CLOAD = 1 nF
0
0
500
1000
CLOAD = 1 nF
0
1500
0
500
1000
Figure 12.
Figure 13.
SUPPLY CURRENT
vs
FREQUENCY (VDD = 10 V)
SUPPLY CURRENT
vs
FREQUENCY (VDD = 12 V)
320
400
280
350
240
CLOAD = 10 nF
200
160
CLOAD = 4.7 nF
120
80
1500
f − Frequency − kHz
IDD − Supply Current − mA
IDD − Supply Current − mA
f − Frequency − kHz
CLOAD = 2.2 nF
300
CLOAD = 10 nF
250
CLOAD = 4.7 nF
200
150
100
CLOAD = 2.2 nF
50
40
CLOAD = 1 nF
0
0
500
1000
f − Frequency − kHz
Figure 14.
CLOAD = 1 nF
0
1500
0
500
1000
1500
f − Frequency − kHz
Figure 15.
11
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
vs
FREQUENCY (VDD = 15 V)
CLK INPUT THRESHOLD
vs
TEMPERATURE
500
2.5
450
2.0
CLOAD = 10 nF
350
300
CLOAD = 4.7 nF
250
200
150
CLOAD = 2.2 nF
100
VI − CLK Input Voltage − V
IDD − Supply Current − mA
CLK Input Rising
400
1.5
CLK Input Falling
1.0
0.5
50
CLOAD = 1 nF
0
0.0
0
1500
1000
500
−50
−25
0
f − Frequency − kHz
25
50
75
100
125
TJ − Temperature − °C
Figure 16.
Figure 17.
OUTPUT RISE TIME AND FALL TIME
vs
TEMPERATURE (VDD = 12 V)
OUTPUT RISE TIME
vs
SUPPLY VOLTAGE
65
18
CLOAD = 2.2 nF
tR = Rise Time
55
14
tR − Output Rise Time − ns
tR, tF − Rise and Fall Times − ns
16
12
10
tF = Fall Time
8
6
4
CLOAD = 10 nF
45
35
CLOAD = 4.7 nF
25
CLOAD = 2.2 nF
15
2
CLOAD = 1 nF
0
−50
12
5
−25
0
25
50
75
100
125
5
7.5
10
12.5
TJ − Temperature − °C
VDD − Supply Voltage − V
Figure 18.
Figure 19.
15
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
OUTPUT FALL TIME
vs
SUPPLY VOLTAGE
CLK to OUTx PROPAGATION DELAY RISING
vs
SUPPLY VOLTAGE
20
45
35
tPD − Propagation Delay, Rising − ns
tF − Output Fall Time − ns
40
CLOAD = 10 nF
30
25
CLOAD = 4.7 nF
20
CLOAD = 2.2 nF
15
CLOAD = 1 nF
10
10
CLOAD = 4.7 nF
5
CLOAD = 2.2 nF
CLOAD = 1 nF
0
5
5
7.5
10
12.5
5
15
7.5
10
12.5
15
VDD − Supply Voltage − V
VDD − Supply Voltage − V
Figure 20.
Figure 21.
CLK TO OUTx PROPAGATION DELAY FALLING
vs
SUPPLY CURRENT
DEFAULT CURRENT LIMIT THRESHOLD
vs
TEMPERATURE
25
0.59
0.58
VCS − Current Limit Threshold − V
tPD − Propagation Delay, Falling − ns
CLOAD = 10 nF
15
CLOAD = 10 nF
20
15
CLOAD = 4.7 nF
10
CLOAD = 2.2 nF
0.57
0.56
0.55
0.54
0.53
0.52
CLOAD = 1 nF
5
0.51
5
7.5
10
12.5
VDD − Supply Voltage − V
Figure 22.
15
−50
−25
0
25
50
75
100
125
TJ − Temperature − °C
Figure 23.
13
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
CS TO OUTx PROPAGATION DELAY
vs
TEMPERATURE
CS TO CLF PROPAGATION DELAY
vs
TEMPERATURE
50
45
35
tPD − CS to CLF Propagation Delay − ns
tPD − CS to OUTx Propagation Delay − ns
40
30
25
20
15
10
5
40
35
30
25
20
15
10
5
0
0
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
TJ − Temperature − °C
Figure 24.
Figure 25.
CLK TO OUT PROPAGATION DELAY
vs
TEMPERATURE
UCD8220
START-UP BEHAVIOR AT VDD = 12 V
35
CLK = CTRL = 3V3
30
tPD − Propagation Delay − ns
VDD (2 V/div)
25
20
15
3V3 (2 V/div)
10
OUTx (2 V/div)
5
0
−50
−25
0
25
50
75
100
125
t − Time − 40 ms/div
TJ − Temperature − °C
Figure 26.
14
100
TJ − Temperature − °C
Figure 27.
125
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
UCD8620
START-UP BEHAVIOR AT VDD = 12 V
UCD8220
SHUT-DOWN BEHAVIOR AT VDD = 12 V
CLK = CTRL = 3V3
CLK = CTRL = 3V3
VDD (2 V/div)
TBD
3V3 (2 V/div)
OUTx (2 V/div)
t − Time − 40 ms/div
t − Time − 40 ms/div
Figure 28.
Figure 29.
UCD8620
SHUT-DOWN BEHAVIOR AT VDD = 12 V
UCD8220
START-UP BEHAVIOR AT VDD = 12 V
CLK = CTRL = 3V3
CLK = AGND
CTRL = 3V3
VDD (2 V/div)
TBD
3V3 (2 V/div)
OUTx (2 V/div)
t − Time − 40 ms/div
Figure 30.
t − Time − 40 ms/div
Figure 31.
15
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
UCD8620
START-UP BEHAVIOR AT VDD = 12 V
UCD8220
SHUT-DOWN BEHAVIOR AT VDD = 12 V
CLK = AGND
CTRL = 3V3
CLK = AGND
CTRL = 3V3
VDD (2 V/div)
TBD
3V3 (2 V/div)
OUTx (2 V/div)
t − Time − 40 ms/div
t − Time − 40 ms/div
Figure 32.
Figure 33.
UCD8620
SHUT-DOWN BEHAVIOR AT VDD = 12 V
OUTPUT RISE AND FALL TIME
(VDD = 12 V, CLOAD = 10 nF)
TBD
t − Time − 40 ms/div
Figure 34.
16
Output Voltage − 2 V/div
CLK = AGND
CTRL = 3V3
t − Time − 40 ns/div
Figure 35.
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
INTERNAL SLOPE COMPENSATION IN CMC
vs
TEMPERATURE
PWM OFFSET AT CTRL INPUT
vs
TEMPERATURE
0.532
Current Mode Slope,
RISET = 100 k
0.530
PWM Offset at CTRL Input − V
0.144
0.142
0.140
0.138
0.136
0.528
0.526
0.524
0.522
0.520
0.134
0.518
−50
−25
0
25
50
75
100
125
−50
−25
TJ − Temperature − °C
0
25
50
75
100
125
TJ − Temperature − °C
Figure 36.
Figure 37.
HIGH VOLTAGE JFET CURRENT
vs
TEMPERATURE
VDD = 12 V
VI = 76 V
Source Current - mA
Internal Slope Compensation in CMC - V/ms
0.146
TBD
VI = 18 V
−50
−25
0
25
50
75
100
125
TJ − Temperature − °C
Figure 38.
17
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
APPLICATION INFORMATION
Introduction
The UCD8220 and UCD8620 are digitally managed
analog PWM controllers configured with push-pull
drive logic. The UCD8620 has a 110-V high-voltage
startup circuit which can directly start up the controller
from a 48-V telecom input line.
In systems using UCD8K devices, the PWM feedback
loop is closed using the traditional analog methods,
but the UCD8K controllers include circuitry to interpret
a time-domain digital pulse train from a digital controller. The pulse train contains the operating frequency
and maximum duty cycle limit and hence controls the
power supply operation. This eases implementing a
converter with high-level control features without the
added complexity or digital PWM resolution limitations encountered when closing the voltage control
loop in the discrete time domain.
The UCD8220 and UCD8620 can be configured for
either peak current mode or voltage mode control.
They provide a programmable current limit function
and a digital output current limit flag which can be
monitored by the host controller. For fast switching
speeds, the output stages use the TrueDrive™ output
architecture, which delivers rated current of ±4 A into
the gate of a MOSFET during the Miller plateau
region of the switching transition. Finally they also
include a 3.3-V, 10-mA linear regulator to provide
power for the digital controller.
The UCD8620 includes circuitry and features to ease
implementing a converter that is managed by a
microcontroller or a digital signal processor. Digitally
managed
power
supplies
provide
software
programmability and monitoring capability of the
power supply operation including:
• Switching frequency
• Synchronization
• DMAX
• V x S clamp
• Input UVLO start/stop voltage
• Input OVP start/stop voltage
• Soft-start profile
• Current limit operation
• Shutdown
• Temperature shutdown
CLK Input Time-Domain Digital Pulse Train
While the loop is closed in the analog domain, the
UCD8K devices are managed by a time-domain
digital pulse train from a digital controller. The pulse
train, shown as CLK in Figure 39, contains the
18
operating frequency and maximum duty cycle limit
and hence controls the power supply operation as
listed above. The pulse train uses a Texas Instruments communication protocol which is a proprietary
communication system that provides handles for
control of the power supply operation through
software programming. The rising edge of the CLK
signal represents the switching frequency. Figure 39
depicts the operation of the UCD8K device in one of
5 modes. At the time when the internal signal REF
OK is low, the UCD8K device is not ready to accept
CLK inputs. Once the REF OK signal goes high, then
the device is ready to process inputs. While the CLK
input is low, the outputs are disabled and the CLK
signal is used as an enable input. Once the Digital
controller completes its initialization routine and verifies that all voltages are within their operating range,
then it starts the soft-start procedure by slowly
ramping up the duty cycle of the CLK signal, while
maintaining the desired switching frequency. The duty
cycle continues to increase until it reaches
steady-state where the analog control loop takes over
and regulates the output voltage to the desire set
point. During steady state, the maximum duty cycle
can be set using a volt second product calculation in
order to protect the primary of the power transformer
from saturation during transients. When the power
supply enters current limit, the outputs are quickly
turned off, and the CLF signal is set high in order to
notify the digital controller that the last power pulse
was truncated because of an overcurrent event. The
benefit of this technique is in the flexibility it offers.
The software is now in charge of the response to
overcurrent events. In typical analog designs, the
power supply response to overcurrent is hardwired in
the silicon. With this method, the user can configure
the response differently for different applications. For
example, the software can be configured to latch-off
the power supply in response the first overcurrent
event, or to allow a fixed number of current limit
events, so that the supply is capable of starting up
into a capacitive load. The user can also configure
the supply to enter into hiccup mode immediately or
after a certain number of current limit events. As
described later in this data sheet, the current limit
threshold can be varied in time to create unique
current limit profiles. For example, the current limit set
point can be set high for a predefined number of
cycles to blow a manual fuse, and can be reduced
down to protect the system in the event of a faulty
fuse.
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
Start up
Steady State
Current Limit
UVLO and
REF OK*
CLK
CTRL
RAMP*
PWM*
OUT
CS
CLF
* - Internal signals
Figure 39. UCD8220 and UCD8620 Timing and Circuit Operation Diagram
JFET Operation (UCD8620 Only)
The UCD8620 digitally managed push-pull analog
PWM Controller contains a 110-V start-up JFET to
simplify the start-up and standby power requirements
for systems with digital controllers. The JFET circuit
has two operating modes. When the VDD voltage is
less than 5 V, the circuit is limited to 5 mA of source
current into VDD. The VDD reaches 5 V, the circuit
switches into temperature protection mode and provides 10 mA until the temperature of the die exceeds
145°C. Figure 40 shows the operation of the JET
circuitry during various operating conditions. At
start-up, the JFET is on and charges up the VDD
capacitor. Once the VDD voltage reaches its UVLO of
13 V, the JFET turns off and the outputs are allowed
to switch. The JFET remains off provided the outputs
are switching and the VDD voltage stays above 7.5
V. If the VDD voltage drops below 7.5 V while the
outputs are switching, the outputs are immediately
disabled, and the JFET is switched back on. It then
attempts to charge the VDD voltage back up to 13 V.
Once the VDD voltage reaches 13 V, the outputs are
enabled again and allowed to switch. If the CLK input
is not switched by the digital controller, then the VDD
voltage decays to 12 V, and the JFET turns on again.
This charges the VDD capacitor back to 13 V where
the cycle repeats until the input voltage drops to a
point where the VDD voltage can no longer be
maintained. Figure 41 shows the graph of available
source current as a function of input and VDD
voltage.
19
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
(1)
For VDD to go below 12 V, the input supply must be dropping out.
Figure 40. UCD8620 JFET Operation Waveforms
Reference / External Bias Supply
30
All devices in the UCD8K family are capable of
supplying a regulated 3.3-V rail to power various
types of external loads such as a microcontroller or
an ASIC. The onboard linear voltage regulator is
capable of sourcing up to 10 mA of current. For
normal operation, place 0.22-µF of ceramic capacitance between the 3V3 pin and the AGND pin.
IDD − Supp;y Current − mA
20
10
0
TBD
−10
Current Sensing and Protection
−20
−30
−40
−50
0
2
4
6
8
10
12
14
16
VDD - Supply Voltage - V
Figure 41. UCD8620 Supply Current vs Supply
Voltage
Supply
The UCD8K devices accept an input range of 4.5 V
to 15.5 V. The device has an internal precision linear
regulator that produces the 3V3 output from this VDD
input. A separate pin, PVDD, not connected internally
to the VDD supply rail provides power for the output
drivers. In all applications the same bus voltage must
supply the two pins. It is recommended that a low
value of resistance be placed between the two pins
so that the local capacitance on each pin forms low
pass filters to attenuate any switching noise that may
be on the bus.
20
Figure 42. Current Sense Filter
A fast current limit comparator connected to the CS
pin is used to protect the power stage by implementing cycle-by-cycle current limiting.Figure 43
shows various methods for setting the ILIM threshold.
The current limit threshold may be set to any value
between 0.25 V and 1 V by applying the desired
threshold voltage to the current limit (ILIM) pin. If the
ILIM pin is left floating, the internal current limit
threshold is 0.5 V. When the CS level is greater than
the ILIM voltage minus 25 mV, the output of the
driver is forced low and the current limit flag (CLF) is
set high. The CLF signal is latched high until the
UCD8K device receives the next rising edge on the
CLK pin.
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
When the CS voltage is below ILIM, the driver output
follows the PWM command. The CLF digital output
flag is monitored by the host controller to determine
when a current limit event occurs, and to then apply
the appropriate algorithm to obtain the desired current
limit profile (i.e. straight line, fold back, hickup, or
latch-off).
A benefit of this local protection feature is that the
UCD8620 devices protects the power stage if the
software code in the digital controller becomes corrupted. If the controller’s PWM output stays high, the
local current sense circuit turns off the driver output
when an overcurrent event occurs. The system then
goes into retry mode because most DSP and
microcontrollers have an on-board watchdog,
brown-out, and other supervisory peripherals to
restart the device in the event that it is not operating
properly. But these peripherals typically do not react
fast enough to save the power stage. The UCD87K’s
local current limit comparator provides the required
fast protection for the power stage.
The CS threshold is 25 mV below the ILIM voltage. If
the user attempts to command zero current while the
CS pin is at ground, the CLF flag latches high until
the CLK pin receives a pulse. At start-up, it is
necessary to ensure that the ILIM pin is always
greater than the CS pin for the handshaking to work.
If for any reason the CS pin comes to within 25 mV of
the ILIM pin during start-up, then the CLF flag is
latched high and the digital controller must poll the
UCD8620 device, by sending it a narrow CLK pulse.
If a fault condition is not present, the CLK pulse
resets the CLF signal to low indicating that the
UCD8620 device is ready to process power pulses.
21
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
40 kW
20 kW
10 kW
2.5 kW
Figure 43. ILIM Settings
22
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
Selecting the ISET Resistor for Voltage Mode
Control
3V3
3V3
(3)
R_ISET
ISET
(4)
I_SC = (3.3 - 1.85) / (11 x R_ISET)
R
PWM
+
Selecting the ISET Resistor for Voltage Mode
Control with Voltage Feed forward
CTRL
(6)
3V3
VIN
R
+
TO CLEAR
of
PWM LATCH
Figure 45 shows the nominal value of resistance to
use for a desired clock frequency. Note that for the
UCD8220 and the UCD8620 controllers, which have
two outputs controlled by Push-Pull logic, the output
ripple frequency is equal to the clock frequency; and
each output switches at half the clock frequency.
0.25 V
R_ISET
S1
OUT
ISET
(4)
I_SC = (3.3 - 1.85) / (11 x R_ISET)
OFF
Figure 44. UCD8x20 Configured in Voltage Mode
Control with an Internal Timing Capacitor
When the ISET resistor is configured as shown in
Figure 44 with the ISET resistor connected between
the ISET pin and the 3V3 pin, the device is set-up for
voltage mode control. For purposes of voltage loop
compensation the, voltage ramp is 1.4 V from the
valley to the peak. See Equation 1 for selecting the
proper resistance for a desired clock frequency.
12
R_ISET =
(3.3 - 1.85) x 10
11 x 1.4 x fclk x 1000 x 9.4
W
(1)
Where:
fclk = Desired Clock Frequency in Hz.
1M
TO CLEAR
of
PWM LATCH
OUT
ON
PWM
+
R
CTRL
(6)
R
+
ON
Cint
9.4 pF
0.25 V
S1
Cint
9.4 pF
OFF
Figure 46. UCD8x20 Configured in Voltage Mode
Control with Voltage Feed Forward
When the ISET resistor is configured as shown in
Figure 46 with the ISET resistor connected between
the ISET pin and the input voltage, VIN, the device is
configured for voltage mode control with voltage feed
forward. For the purposes of voltage loop compensation, the voltage ramp is 1.4 x Vin/Vin_max Volts
from the valley to the peak. See Equation 2 for
selecting the proper resistance for a desired clock
frequency and input voltage range.
12
R_ISET Resistance − W
R_ISET =
(Vin_max - 1.85) x 10
11 x 1.4 x fclk x 9.4
W
(2)
Where:
fclk = Desired Clock Frequency in Hz.
100 k
For a general discussion of the benefits of Voltage
Mode Control with Voltage feed forward, see Reference [5].
10 k
1k
10
100
1000
10000
Clock Frequency − kHz
Figure 45. ISET Resistance vs Clock Frequency
23
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
Selecting the ISET Resistor for Peak Current
Mode Control with Internal Slope Compensation
3V3
ISET
(4)
I_SC = 1.85 / (11 x R_ISET)
Handshaking
R_ISET
CTRL
(6)
-
+
+
R
0.25 V
Cint
12 pF
S1
OUT
ON
The UCD8K family of devices have a built-in handshaking feature to facilitate efficient start-up of the
digitally managed power supply. At start-up the CLF
flag is held high until all the internal and external
supply voltages of the UCD8K device are within their
operating range. Once the supply voltages are within
acceptable limits, the CLF goes low and the device
processes the CLK signals. The digital controller
should monitor the CFL flag at start-up and wait for
the CLF flag to go LOW before sending CLK pulses
to the UCD8K device.
R
PWM
TO CLEAR
of
PWM LATCH
The amount of slope compensation required depends
on the design of the power stage and the output
specifications. A general rule is to add an up-slope
equal to the down slope of the output inductor.
OFF
CS
(9)
S2
Driver Output
Figure 47. UCCD8x20 Configured in Peak Current
Control with Internal Slope Compensation
When the ISET resistor is configured as shown in
Figure 47 with the ISET resistor connected between
the ISET pin and AGND, the device is configured for
peak current mode control with internal slope compensation. The voltage at the ISET pin is 1.85 volts
so the internal slope compensation current, I_SC,
being fed into the internal slope compensation capacitor is equal to 1.85 / (11x R_ISET). The voltage
slope at the PWM comparator input which is generated by this current is equal to:
6
SLOPE =
1.85 x 10
V/ms
11 x R_ISET x 12
(3)
TrueDrive™ consists of pull-up/pull-down circuits with
bipolar and MOSFET transistors in parallel. The peak
output current rating is the combined current from the
bipolar and MOSFET transistors. This hybrid output
stage also allows efficient current sourcing at low
supply voltages.
Large power MOSFETs present a large load to the
control circuitry. Proper drive is required for efficient,
reliable operation. The UCD8K drivers have been
optimized to provide maximum drive to a power
MOSFET during the Miller plateau region of the
switching transition. This interval occurs while the
drain voltage is swinging between the voltage levels
dictated by the power topology, requiring the charging/discharging of the drain-gate capacitance with
current supplied or removed by the driver device. See
Reference [2].
1k
100
Slope - V/ms
The drive output uses the Texas Instruments
TrueDrive™ architecture, which delivers rated current
into the gate of a MOSFET when it is most needed,
during the Miller plateau region of the switching
transition providing efficiency gains.
Source/Sink Capabilities During Miller Plateau
10 k
10
1
Drive Current and Power Requirements
0.1
0.01
1
10
100
1k
10 k
100 k
R_ISET Resistance - W
Figure 48. Slope vs RISET Resistance
24
The high-current output stage of the UCD8K device
family is capable of supplying ±4-A peak current
pulses and swings to both PVDD and PGND.
1M
The UCD8620 family of controllers contains drivers
which can deliver high current into a MOSFET gate
for a period of several hundred nanoseconds.
High-peak current is required to turn on a MOSFET.
Then, to turn off a MOSFET, the driver is required to
sink a similar amount of current to ground. This
repeats at the operating frequency of the power
device.
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
Reference [2] discusses the current required to drive
a power MOSFET and other capacitive-input
switching devices.
When a driver device is tested with a discrete,
capacitive load it is a fairly simple matter to calculate
the power that is required from the bias supply. The
energy that must be transferred from the bias supply
to charge the capacitor is given by:
E = 1 x CV 2
2
(4)
where C is the load capacitor and V is the bias
voltage feeding the driver.
There is an equal amount of energy transferred to
ground when the capacitor is discharged. This leads
to a power loss given by the following:
P = CV 2 x 1
(5)
where f is the switching frequency.
This power is dissipated in the resistive elements of
the circuit. Thus, with no external resistor between
the driver and gate, this power is dissipated inside the
driver. Half of the total power is dissipated when the
capacitor is charged, and the other half is dissipated
when the capacitor is discharged.
With VDD = 12 V, CLOAD = 2.2 nF, and f = 300 kHz,
the power loss can be calculated as:
P = 2.2 nF x 122 x 300 kHz = 0.095 W
(6)
With a 12-V supply, this would equate to a current of:
0.095 W = 7.9 mA
P
=
I =
V
12 V
(7)
Thermal Information
The useful range of a driver is greatly affected by the
drive power requirements of the load and the thermal
characteristics of the device package. In order for a
power driver to be useful over a particular tempera-
ture range the package must allow for the efficient
removal of the heat produced while keeping the
junction temperature within rated limits. The UCD8K
family of drivers is available in PowerPAD™ TSSOP
and QFN/DFN packages to cover a range of application requirements. Both have an exposed pad to
enhance thermal conductivity from the semiconductor
junction.
As illustrated in Reference [3], the PowerPAD™
packages offer a leadframe die pad that is exposed at
the base of the package. This pad is soldered to the
copper on the PC board (PCB) directly underneath
the device package, reducing the θJA down to
37.47°C/W. The PC board must be designed with
thermal lands and thermal vias to complete the heat
removal subsystem, as summarized in Reference [4].
Note that the PowerPAD™ is not directly connected
to any leads of the package. However, it is electrically
and thermally connected to the substrate which is the
ground of the device. The PowerPAD™ should be
connected to the quiet ground of the circuit.
Circuit Layout Recommendations
In a MOSFET driver operating at high frequency, it is
critical to minimize stray inductance to minimize
overshoot/undershoot and ringing. The low output
impedance of the drivers produces waveforms with
high di/dt. This tends to induce ringing in the parasitic
inductances. It is advantageous to connect the driver
device close to the MOSFETs. It is recommended
that the PGND and the AGND pins be connected to
the PowerPAD™ of the package with a thin trace. It
is critical to ensure that the voltage potential between
these two pins does not exceed 0.3 V. The use of
schottky diodes on the outputs to PGND and PVDD is
recommended when driving gate transformers.
25
UCD8220, UCD8620
www.ti.com
SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005
REFERENCES
1. Power Supply Seminar SEM-1600 Topic 6: A Practical Introduction to Digital Power Supply Control, by
Laszlo Balogh, Texas Instruments Literature No. SLUP224
2. Power Supply Seminar SEM–1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate
Drive Circuits, by Laszlo Balogh, Texas Instruments Literature No. SLUP133.
3. Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA002
4. Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004
5. Power Supply Seminar SEM-300 Topic 2, "Closing the Feedback Loop", by Lloyd Dixon Jr., Texas
Instruments, (Literature Number SLUP068)
RELATED PRODUCTS
PRODUCT
DESCRIPTION
UCD9501
Digital Power Controller for High Performance Multi-loop Applications
MSP430F1232
Microcontroller
REVISION HISTORY
DATE
26
REVISION
CHANGE DESCRIPTION
03/05
SLUS652
08/05
SLUS652A
Initial release.
Extensive changes throughout
09/05
SLUS652B
Extensive changes throughout
FEATURES
PACKAGE OPTION ADDENDUM
www.ti.com
23-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
UCD8220PWP
PREVIEW
HTSSOP
PWP
16
90
TBD
Call TI
Call TI
UCD8220PWPR
PREVIEW
HTSSOP
PWP
16
2000
TBD
Call TI
Call TI
UCD8220RSA
PREVIEW
QFN
RSA
16
250
TBD
Call TI
Call TI
UCD8220RSAR
PREVIEW
QFN
RSA
16
3000
TBD
Call TI
Call TI
UCD8620PWP
PREVIEW
HTSSOP
PWP
16
90
TBD
Call TI
Call TI
UCD8620PWPR
PREVIEW
HTSSOP
PWP
16
2000
TBD
Call TI
Call TI
UCD8620RGWR
PREVIEW
QFN
RGW
20
3000
TBD
Call TI
Call TI
UCD8620RGWT
PREVIEW
QFN
RGW
20
250
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
UCD8220PWP
ACTIVE
HTSSOP
PWP
16
UCD8220PWPR
ACTIVE
HTSSOP
PWP
UCD8220RSA
PREVIEW
QFN
UCD8220RSAR
PREVIEW
UCD8620PWP
PREVIEW
UCD8620PWPR
PREVIEW
UCD8620RGWR
UCD8620RGWT
90
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
RSA
16
250
TBD
Call TI
Call TI
QFN
RSA
16
3000
TBD
Call TI
Call TI
HTSSOP
PWP
16
90
TBD
Call TI
Call TI
HTSSOP
PWP
16
2000
TBD
Call TI
Call TI
PREVIEW
QFN
RGW
20
3000
TBD
Call TI
Call TI
PREVIEW
QFN
RGW
20
250
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2005, Texas Instruments Incorporated