SLUS600 − APRIL 2004 FEATURES D Input Voltage Range: 4.75 V to 5.25 V D VLDOIN Voltage Range: 1.2 V to 3.6 V D 3-A Sink/Source Termination Regulator D D D D D D D D D D DESCRIPTION The TPS51100 is a 3-A sink/source tracking termination regulator. It is specifically designed for low-cost/low-external component count systems, where space is a premium. Includes Droop Compensation Requires Only 20-µF Ceramic Output Capacitance Supports High-Z in S3 and Soft-Off in S5 1.2-V Input (VLDOIN) Helps Reduce Total Power Dissipation Integrated Divider Tracks !/2VDDQSNS for VTT and VTTREF Remote Sensing (VTTSNS) ± 20-mV Accuracy for VTT and VTTREF 10-mA Buffered Reference (VTTREF) Built-In Soft-Start, UVLO and OCL Thermal Shutdown Supports JEDEC Specifications The TPS51100 maintains fast transient response only requiring 20-µF (2 × 10µF) of ceramic output capacitance. The TPS51100 supports remote sensing functions and all features required to power the DDR/DDR II VTT bus termination according to the JEDEC specification. In addition, the TPS51100 includes integrated sleep-state controls placing VTT in High-Z in S3 (suspend to RAM) and soft-off for VTT and VTTREF in S5 (suspend to disk). The TPS51100 is available in the thermally efficient 10-pin MSOP PowerPAD and is specified from −40°C to 85°C. ORDERING INFORMATION APPLICATIONS D DDR I/II Memory Termination D SSTL−2, SSTL−18 and HSTL Termination TA −40°C to 85°C TPS51100DGQ (1) The DGQ package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS51100DGQR). See the application section of the data sheet for PowerPAD drawing and layout information. TPS51100DGQ C1 2 y 10 µF 1 VDDQSNS 2 VLDOIN 3 VTT 4 PGND 5 VTTSNS VIN 10 S5 9 GND 8 S3 7 VTTREF 6 PLASTIC MSOP POWER PAD (DGQ)(1) 5V_IN S5 C2 0.1 µF S3 VTTREF Cap Manuf Part Number C1 TDK C2012JB0J106K C2 TDK C1608JB1H104K UDG−04015 !"# $"%&! '#( '"! ! $#!! $# )# # #* "# '' +,( '"! $!#- '# #!#&, !&"'# #- && $##( Copyright 2004, Texas Instruments Incorporated www.ti.com 1 SLUS600 − APRIL 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) TPS51100 VIN, VLDOIN, VTTSNS, VDDQSNS, S3, S5 Input voltage range(2) −0.3 to 6 PGND Output voltage range(2) UNIT −0.3 to 0.3 VTT, VTTREF V −0.3 to 6 Operating ambient temperature range, TA −40 to 85 Storage temperature, Tstg −55 to 150 °C C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds TBD (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the network ground terminal unless otherwise noted. DISSIPATION RATING TABLE PACKAGE TA < 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 85°C POWER RATING 10-pin DGQ 1.73 W 17.3 mW/°C 0.694 W RECOMMENDED OPERATING CONDITIONS MIN Supply voltage, VIN 4.75 5.25 −0.10 5.25 VLDOIN, VDDQSNS, VTT, VTTSNS −0.1 3.6 VTTREF −0.1 1.8 PGND −0.1 0.1 −40 85 S3, S5 Voltage range Operating free-air temperature, TA (TOP VIEW) DGQ Package VDDQSNS VLDOIN VTT PGND VTTSNS 1 10 2 9 3 8 4 7 5 6 VIN S5 GND S3 VTTREF ACTUAL SIZE 3,05mm x 4,98mm (4) For more information on the DGQ package, refer to TI Technical Brief, Literature No. SLMA002. (5) PowerPADt heat slug must be connected to GND (pin 8) or electrically isolated from all other pins. 2 MAX www.ti.com UNIT V °C SLUS600 − APRIL 2004 ELECTRICAL CHARACTERISTICS TA = −40°C to 85°C, VVIN = 5 V, VLDOIN and VDDQSNS are connected to 2.5 V (unless otherwise noted) TEST CONDITIONS PARAMETER MIN TYP MAX UNIT 0.25 0.50 1.00 mA 25 50 80 0.3 1.0 1.2 2.0 6 10 0.3 1.0 1 3 5 −1.00 −0.25 1.00 SUPPLY CURRENT IVIN Supply current, VIN TA = 25°C, VS3 = VS5 = 5 V VVIN = 5 V, no load IVINSTB Standby currrent, VIN TA = 25°C, VS3 = 0 V, VVIN = 5 V, VS5 = 5 V no load IVINSDN Shutdown current, VIN TA = 25°C, VS3 = VS5 = 0 V, VVIN = 5 V, no load VVLDOIN = VVDDQSNS = 0 V IVLDOIN Supply current, VLDOIN TA = 25°C, VS3 = VS5 = 5 V VVIN = 5 V, no load IVLDOINSTB Standby currrent, VLDOIN TA = 25°C, VS3 = 0 V, VVIN = 5 V, VS5 = 5 V no load IVLDOINSDN Shutdown current, VLDOIN TA = 25°C, VS3 = VS5 = 0 V VVIN = 5 V, no load VVIN = 5 V, VVIN = 5 V, VS3 = VS5 = 5 V VS3 = VS5 = 5 V µA A 0.7 mA A µA INPUT CURRENT IVDDQSNS IVTTSNS Input current, VDDQSNS Input current, VTTSNS µA A VTT OUTPUT VVTTSNS Output voltage, VTT VVTTTOL25 Output voltage tolerance to VTTREF, VTT VVTTTOL18 Output voltage tolerance to VTTREF, VTT IVTTOCLSRC Source current limit, VTT VVLDOIN = VVDDQSNS = 2.5 V VVLDOIN = VVDDQSNS = 1.8 V −20 20 −30 30 VVLDOIN = VVDDQSNS = 2.5 |IVVTT| = 3 A VVLDOIN = VVDDQSNS = 1.8 |IVVTT| = 0 A −40 40 −20 20 VVLDOIN = VVDDQSNS = 1.8 |IVVTT| = 1 A VVLDOIN = VVDDQSNS = 1.8 |IVVTT| = 2 A −30 30 −40 40 ǒ V VDDQSNS V TT + 2 Ǔ V TT + ǒ V VDDQSNS 2 PGOOD + High 0.95, Ǔ PGOOD + High 1.05, VVTT = VVDDQ IVTTLK Leakage current, VTT V 0.9 VVLDOIN = VVDDQSNS = 2.5,|IVVTT| = 0 A VVLDOIN = VVDDQSNS = 2.5 |IVVTT| = 1.5 A VVTT = 0 V IVTTOCLSNK Sink current limit, VTT 1.25 V TT + ǒ V VDDQSNS 2 VS3 = 0 V, ǒ V VDDQSNS Ǔ IVTTSNSLK Leakage current, VTTSNS V TT + IDSCHRG Discharge current, VTT TA = 25°C, VVDDQSNS = 0 V, 2 Ǔ + 1.25 V, T A + 25 oC 3.0 3.8 6.0 1.5 2.2 3.0 3.0 3.6 6.0 1.5 2.2 3.0 −1.0 0.5 1.0 www.ti.com A µA VS5 = 5 V + 1.25 V, mV T A + 25 oC VS3 = VS5 = 0 V, VVTT = 0.5 V −1.00 0.01 10 17 1.00 mA 3 SLUS600 − APRIL 2004 ELECTRICAL CHARACTERISTICS(continued) TA = −40°C to 85°C, VVIN = 5 V, VLDOIN and VDDQSNS are connected to 2.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP VTTREF OUTPUT VVTTREF V TTREF + Output voltage, VTTREF Output voltage tolerance to VVTTREFTOL VDDQSNS/2 IVTTREFOCL Source current limit, VTTREF UVLO/LOGIC THRESHOLD VVLDOIN = VVDDQSNS, IVTTREF < 10 mA VVVTTREF = 0 V UVLO threshold voltage, VIN VIH VIL High-level input voltage S3, S5 Low-level input voltage S3, S5 VIHYST IILEAK Hysteresis voltage S3, S5 Logic input leakage current S2, S5, Hysteresis 20 2 UNIT Ǔ V 20 mV 30 mA V VDDQSNS −20 10 Wake up VVINUV ǒ MAX 3.4 3.7 4.0 0.15 0.25 0.35 1.6 V 0.3 0.2 TA = 25°C −1 1 µA THERMAL SHUTDOWN TSDN Thermal shutdown threshold voltage Shutdown temperature TBD Hysteresis 160 10 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION GND 8 − Signal ground. Connect to negative terminal of the output capacitor PGND 4 − Power ground output for the VTT LDO S3 7 I S3 signal input S5 9 I S5 signal input VDDQSNS 1 I VDDQ sense input VIN 10 I 5-V power supply VLDOIN 2 I Power supply for the VTT LDO and VTTREF output stage VTT 3 O Power output for the VTT LDO VTTREF 6 O VTT reference output. Connect to GND through 0.1-µF ceramic capacitor. VTTSNS 5 I Voltage sense input for the VTT LDO. Connect to plus terminal of the output capacitor. 4 www.ti.com TBD °C SLUS600 − APRIL 2004 SIMPLIFIED BLOCK DIAGRAM VDDQSNS 1 + GND 2 VLDOIN 6 VTTREF HalfDDQ + 8 VIN 10 + VinOK DchgREF 3.7 V/3.5 V VTTSNS 5 S3 7 + 4 PGND DchgVTT + 5%/10% + ENREF PGOOD DchgREF + + 9 VTT ENVTT DchgVTT S5 3 −5%/−10% www.ti.com UDG−04016 5 SLUS600 − APRIL 2004 DETAILED DESCRIPTION VTT SINK/SOURCE REGULATOR The TPS51100 is a 3-A sink/source tracking termination regulator designed specially for low-cost, low external components system where space is at premium such as notebook PC applications. TPS51100 integrates highperformance low−dropout linear regulator that is capable of sourcing and sinking current up to 3 A. This VTT linear regulator employs ultimate fast response feedback loop so that small ceramic capacitors are enough to keep tracking to the VTTREF within ±40 mV at all conditions including fast load transient. To achieve tight regulation with minimum effect of trace resistance, a remote sensing terminal, VTTSNS, should be connected to the positive node of VTT output capacitor(s) as a separate trace from the high current line from VTT. VTTREF REGULATOR The VTTREF block consists of an on-chip 1/2 divider, LPF and buffer. This regulator can source current up to 10 mA. Bypass VTTREF to GND using a 0.1-µF ceramic capacitor to ensure stable operation. Soft-Start The soft-start function of the VTT is achieved via a current clamp, allowing the output capacitors to be charged with low and constant current that gives linear ramp up of the output voltage. The current limit threshold is changed in two stages using an internal powergood signal. When VTT is outside the powergood threshold, the current limit level is 2.2 A. When VTT rises above (VTTREF − 5%) or falls below (VTTREF + 5%) the current limit level switches to 3.8 A. The thresholds are typically VTTREF ±5% (from outside regulation to inside) and ±10% (when it falls outside). The soft-start function is completely symmetrical and it works not only from GND to VTTREF voltage, but also from VDDQ to VTTREF voltage. Note that the VTT output is in a high impedance state during the S3 state (S3 = low, S5 = high) and its voltage can be up to VDDQ voltage depending on the external condition. Note that VTT does not start under a full load condition. S3, S5 Control and Soft-Off The S3 and S5 terminals should be connected to SLP_S3 and SLP_S5 signals respectively. Both VTTREF and VTT are turned on at S0 state (S3 = high, S5 = high). VTTREF is kept alive while VTT is turned off and left high impedance in S3 state (S3 = low, S5 = high). Both VTT and VTTREF outputs are turned off and discharged to the ground through internal MOSFETs during S4/S5 state (both S3 and S5 are low). Table 1. S3 and S5 Control Table STATE S3 S5 VTTREF VTT S0 H H 1 1 S3 L H 1 0 (high−Z) S4/S5 L L 0 (discharge) 0 (discharge) (In case S3 is forced H and S5 to L, VTTREF is discharged and VTT is at High−Z state. This condition is NOT recommended.) VTT Current Protection The LDO has a constant overcurrent limit (OCL) at 3.8 A. This trip point is reduced to 2.2 A before the output voltage comes within ±5% of the target voltage or goes outside of ±10% of the target voltage. 6 www.ti.com SLUS600 − APRIL 2004 DETAILED DESCRIPTION VIN UVLO Protection For VIN undervoltage lockout (UVLO) protection, the TPS51100 monitors VIN voltage. When the VIN voltage is lower than UVLO threshold voltage, the VTT regulator is shut off. This is a non-latch protection. Thermal Shutdown TPS51100 monitors its temperature. If the temperature exceeds threshold value, typically 160°C, the VTT and VTTREF regulators are shut off. This is also a non-latch protection. Output Capacitor For stable operation, total capacitance of the VTT output terminal can be equal or greater than 20-µF. Attach two 10-µF ceramic capacitors in parallel to minimize the effect of ESR and ESL. If the ESR is greater than 2 mΩ, insert an R-C filter between the output and the VTTSNS input to achieve loop stability. The R-C filter time constant should be almost the same or slightly lower than the time constant of the output capacitor and its ESR. Soft-start duration, TSS, is also a function of this output capacitance. Where ITTOCL = 2.2 A (typ), TSS can be calculated as, T SS + ǒ Ǔ C OUT V VTT I VTTOCL (1) Input Capacitor Depending on the trace impedance between the VLDOIN bulk power supply to the part, transient increase of source current is supplied mostly by the charge from the VLDOIN input capacitor. Use a 10-µF (or more) ceramic capacitor to supply this transient charge. Provide more input capacitance as more output capacitance is used at VTT. In general, use 1/2 COUT for input. VIN Capacitor Add a ceramic capacitor with a value between 1.0-µF and 4.7-µF placed close to the VIN pin, to stabilize 5-V from any parasitic impedance from the supply. Thermal design As the TPS51100 is a linear regulator, the VTT current flow in both source and sink directions generate power dissipation from the device. In the source phase, the potential difference between VVLDOIN and VVTT times VTT current becomes the power dissipation, WDSRC. W DSRC + ǒV VLDOIN * V VTTǓ I VTT (2) In this case, if VLDOIN is connected to an alternative power supply lower than VDDQ voltage, power loss can be decreased. For the sink phase, VTT voltage is applied across the internal LDO regulator, and the power dissipation, and WDSNK, is calculated by: W DSNK + V VTT I VTT (3) Since the device does not sink and source the current at the same time and IVTT varies rapidly with time, actual power dissipation need to be considered for thermal design is an average of above value over thermal relaxation duration of the system. Another power consumption is the current used for internal control circuitry from VIN supply and VLDOIN supply. This can be estimated as 20 mW or less at normal operational conditions. This power needs to be effectively dissipated from the package. Maximum power dissipation allowed to the package is calculated by, www.ti.com 7 SLUS600 − APRIL 2004 DETAILED DESCRIPTION W PKG + ǒTJ(max) * TA(max)Ǔ q JA (4) where D TJ(max) is 125°C D TA(max) is the maximum ambient temperature in the system D θJA is the thermal resistance from the silicon junction to the ambient This thermal resistance strongly depends on the board layout. TPS51100 is assembled in a thermally enhanced PowerPAD package that has exposed die pad underneath the body. For improved thermal performance, this die pad needs to be attached to ground trace via thermal land on the PCB. This ground trace acts as a heat sink/spread. The typical thermal resistance, 57.7°C/W, is achieved based on a 3 mm × 2 mm thermal land with 2 vias without air flow. It can be improved by using larger thermal land and/or increasing vias number. For example, assuming 3 mm × 3 mm thermal land with 4 vias without air flow, it is 45.4°C/W. Further information about PowerPAD and its recommended board layout is described in the application note (SLMA002). This document is available at www.ti.com. LAYOUT CONSIDERATIONS Consider the following points before the layout of TPS51100 design begins. D The input bypass capacitor for VLDOIN should be placed to the pin as close as possible with short and wide connection. D The output capacitor for VTT should be placed close to the pin with short and wide connection in order to avoid additional ESR and/or ESL of the trace. D VTTSNS should be connected to the positive node of VTT output capacitor(s) as a separate trace from the high current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed to sense the voltage of the point of the load, it is recommended to attach the output capacitor(s) at that point. Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and the output capacitor(s). D Consider adding LPF at VTTSNS in case ESR of the VTT output capacitor(s) is larger than 2 mΩ. D VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the reference voltage of VTTREF. Avoid any noise generative lines. D Negative node of VTT output capacitor(s) and VTTREF capacitor should be tied together by avoiding common impedance to the high current path of the VTT source/sink current. D GND (Signal GND) pin node represents the reference potential for VTTREF and VTT outputs. Connect GND to negative nodes of VTT capacitor(s), VTTREF capacitor and VDDQ capacitor(s) with care to avoid additional ESR and/or ESL. GND and PGND (Power GND) should be isolated, with a single point connection between them. D In order to effectively remove heat from the package, prepare thermal land and solder to the package’s thermal pad. Wide trace of the component−side copper, connected to this thermal land, will help heat spreading. Numerous vias 0.33 mm in diameter connected from the thermal land to the internal/solder−side ground plane(s) should be used to help dissipation. 8 www.ti.com SLUS600 − APRIL 2004 TYPICAL CHARACTERISTICS VIN SHUTDOWN CURRENT vs TEMPERATURE VIN SUPPLY CURRENT vs TEMPERATURE 2.0 0.9 1.8 IVINSDN − VIN Supply Current − µA 1.0 IVIN − VIN Supply Current − mA 0.8 0.7 0.6 0.5 0.4 0.3 0.2 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.1 0 0 −50 0 50 100 −50 150 TJ − Junction Temperature − °C Figure 1 Figure 2 VIN SUPPLY CURRENT vs VTT LOAD CURRENT VLDOIN SUPPLY CURRENT vs TEMPERATURE 10 150 2.0 DDR II VVTT = 1.8 V 1.9 IVLDOIN − VLDOIN Supply Current − mA 9 1.8 8 IVIN − VIN Supply Current − mA 0 50 100 TJ − Junction Temperature − °C 1.7 7 1.6 6 1.5 1.4 5 1.3 4 1.2 3 1.1 1.0 2 0.9 1 0.8 0 −2.0 −1.5 −1.0 −0.5 0 0.5 1.0 1.5 2.0 0.7 −50 IVTT − VTT Load Current − A 0 50 100 TJ − Junction Temperature − °C 150 Figure 4 Figure 3 www.ti.com 9 SLUS600 − APRIL 2004 TYPICAL CHARACTERISTICS VLDOIN SHUTDOWN CURRENT vs TEMPERATURE DISCHARGE CURRENT vs TEMPERATURE 2.0 30 IDSCHRG − VTT Discharge Current − mA IVLDOIN − VLDOIN Supply Current − µA 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 −50 0 50 100 25 20 15 10 −50 150 0 TJ − Junction Temperature − °C 50 VTT VOLTAGE LOAD REGULATION vs VTT LOAD CURRENT (DDR I) 0.93 1.27 0.92 VVTT − VTT Voltage − V VVTT − VTT Voltage − V VTT VOLTAGE LOAD REGULATION vs VTT LOAD CURRENT (DDR II) 0.94 1.28 1.26 1.25 150 Figure 6 Figure 5 1.29 100 TJ − Junction Temperature − °C VVLDOIN = 2.5 V 1.24 1.23 0.91 0.90 VVLDOIN = 1.8 V 0.89 0.88 VVLDOIN = 1.2 V VVLDOIN = 1.8 V 1.22 0.87 VVLDOIN = 1.5 V 1.21 0.86 −4 −3 −1 1 −2 0 2 IVTT − VTT Load Current − A 3 4 −3 −2 −1 0 1 2 IVTT − VTT Load Current − A Figure 8 Figure 7 10 −4 www.ti.com 3 4 SLUS600 − APRIL 2004 TYPICAL CHARACTERISTICS VTTREF VOLTAGE LOAD REGULATION vs VTTREF LOAD CURRENT (DDR I) VTTREF VOLTAGE LOAD REGULATION vs VTTREF LOAD CURRENT (DDR II) 902 VVTTREF − VTTREF Voltage − V VVTTREF − VTTREF Voltage − V 1.252 901 1.251 1.250 900 1.249 899 1.248 0 2 4 6 8 IVTTREF − VTTREF Load Current − A 10 898 Figure 9 0 2 4 6 8 IVTTREF − VTTREF Load Current − A 10 Figure 10 VTT VOLTAGE LOAD TRANSIENT RESPONSE VVLDOIN (50 mV/div) Offset: 1.8 V VVTT (20 mV/div) Offset 0.9 V VVTTREF (20 mV/div) Offset 0.9 V IVTT (2 A/div) t − Time − 20 µs/div Figure 11 www.ti.com 11 SLUS600 − APRIL 2004 TYPICAL CHARACTERISTICS STARTUP WAVEFORMS S3 LOW−TO-HIGH STARTUP WAVEFORMS S5 LOW−TO-HIGH VS3 = 0 V IVTT = IVTTREF = 0A VS5 (5 V/div) VS5 (5 V/div) VS3 (5 V/div) VS3 (5 V/div) VTTREF VVTTREF (0.5 V/div) VVTT (0.5 V/div) VVTT (0.5 V/div) VS5 = 5 V IVTT = IVTTREF = 0A t − Time − 10 µs/div t − Time − 10 µs/div Figure 12 Figure 13 SHUTDOWN WAVEFORMS S3 AND S5 HIGH-TO-LOW SHUTDOWN WAVEFORMS S3 HIGH-TO-LOW VS5 (5 V/div) VS5 (5 V/div) VS3 (5 V/div) VS3 (5 V/div) VTTREF (0.5 V/div) VVTTREF (0.5 V/div) VVTT (0.5 V/div) VS5 = 5 V IVTT = IVTTREF = 0A 12 VVTT (0.5 V/div) IVTT = IVTTREF = 0A t − Time − 1 ms/div t − Time − 1 ms/div Figure 14 Figure 15 www.ti.com SLUS600 − APRIL 2004 TYPICAL CHARACTERISTICS BODE PLOT DDR I SINK 80 135 60 135 40 90 40 90 20 45 20 45 Phase (−1 A) Gain − dB 60 Phase (−0.1 A) Gain (−0.1 A) 0 Phase − ° Gain − dB 180 80 −45 −20 C1 = 2 y 10 µF −40 10 k 100 k 1M f − Frequency − Hz Phase (0.1 A) Gain (0.1 A) 0 0 −45 C1 = 2 y 10 µF −40 10 k 100 k −90 10 M Gain (1 A) 1M −90 10 M f − Frequency − Hz Figure 17 BODE PLOT DDR II SOURCE BODE PLOT DDR II SINK 80 180 Phase (−1 A) 180 Phase (1 A) 60 135 40 90 40 90 20 45 20 45 Phase (−0.1 A) Gain (−0.1 A) 0 Gain (−1 A) 1M −90 10 M −40 10 k f − Frequency − Hz Figure 18 0 −45 −20 C1 = 2 y 10 µF C1 = 2 y 10 µF 100 k −45 Phase (0.1 A) Gain (0.1 A) 0 0 −20 −40 10 k Phase − ° 135 60 Gain − dB 0 −20 Gain (−1 A) Figure 16 80 180 Phase (1 A) Phase − ° BODE PLOT DDR I SOURCE Gain (1 A) 100 k 1M f − Frequency − Hz −90 10 M Figure 19 www.ti.com 13 SLUS600 − APRIL 2004 THERMAL PAD MECHANICAL DATA PowerPADt PLASTIC SMALL-OUTLINE DGQ (S−PDSO−G10) 14 www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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