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TSL201CL
64 × 1 Linear Sensor Array
General Description
The TSL201CL linear sensor array consists of a 64 × 1 array of
photodiodes and associated charge amplifier circuitry. The
pixels measure 120μm (H) by 68μm (W) with 125μm
center-to-center spacing and 57μm spacing between pixels.
Operation is simplified by internal control logic that requires
only a serial-input (SI) signal and a clock.
The TSL201CL is intended for use in a wide variety of
applications including mark detection and code reading,
optical character recognition (OCR) and contact imaging, edge
detection and positioning as well as optical linear and rotary
encoding.
Ordering Information and Content Guide appear at end of
datasheet.
Key Benefits & Features
The benefits and features of the TSL201CL, 64 × 1 Linear Sensor
Array are listed below:
Figure 1:
Added Value of Using TSL201CL
Benefits
Features
• Provides high density pixel count
• 64 x 1 sensor-element organization
• Enables high resolution scanning
• 200 Dots-Per-Inch (DPI) sensor pitch
• Enables capacitive threshold sensing
• High linearity and uniformity
• Provides full dynamic range
• Rail-to-rail output swing
• Wide dynamic range: 2000:1 (66dB)
• Output referenced to ground
• Low image lag: 0.5% Typ
• Operation to 5MHz
• Single 5V supply
• Replacement for TSL201, TSL201R, and TSL201R-LF
ams Datasheet
[v1-00] 2016-May-20
Page 1
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TSL201CL − General Description
Block Diagram
The functional blocks of this device are shown below:
Figure 2:
TSL201CL Block Diagram
Pixel 1
S1
_
+
Pixel
2
1 Integrator
Reset
2
Pixel
3
4
V DD
Pixel
64
Output
Amplifier
Analog
Bus
2
1
3
3
AO
S2
Sample/
Output
6, 7
GND
Gain
Trim
Switch Control Logic
Q1
CLK
SI
2
Q2
RL
(External
330
Load)
Q3
Q64
6 4 -B i t S h i f t R e g i s te r
1
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ams Datasheet
[v1-00] 2016-May-20
TSL201CL − Pin Assignment
The TSL201CL pin assignment is described below:
Pin Assignment
Figure 3:
Pin Diagram (Top View)
CL Package:
NC - No internal connection
SI 1
8 NC
CLK 2
7 GND
AO 3
6 GND
V DD 4
5 NC
Figure 4:
Terminal Functions
Terminal
Description
Name
No.
SI
1
Serial input. SI defines the start of the data-out sequence.
CLK
2
Clock. The clock controls charge transfer, pixel output, and reset.
AO
3
Analog output.
VDD
4
Supply voltage. Supply voltage for both analog and digital circuits.
GND
6, 7
ams Datasheet
[v1-00] 2016-May-20
Ground (substrate). All voltages are referenced to the substrate.
Page 3
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TSL201CL − Detailed Description
The sensor consists of 64 photodiodes arranged in a linear array.
Light energy impinging on a photodiode generates
photocurrent, which is integrated by the active integration
circuitry associated with that pixel. During the integration
period, a sampling capacitor connects to the output of the
integrator through an analog switch. The amount of charge
accumulated at each pixel is directly proportional to the light
intensity and the integration time. The integration time is the
interval between two consecutive output periods.
Detailed Description
The output and reset of the integrators is controlled by a 64-bit
shift register and reset logic. An output cycle is initiated by
clocking in a logic 1 on SI for one positive going clock edge (see
Figure 10 and Figure 11)1. As the SI pulse is clocked through the
64-bit shift register, the charge on the sampling capacitor of
each pixel is sequentially connected to a charge-coupled
output amplifier that generates a voltage output, AO. When the
bit position goes low, the pixel integrator is reset. On the 65th
clock rising edge, the SI pulse is clocked out of the shift register
and the output assumes a high-impedance state. Note that this
65th clock pulse is required to terminate the output of the 64th
pixel and return the internal logic to a known state. A
subsequent SI pulse can be presented as early as the 66th clock
pulse, thereby initiating another pixel output cycle.
The voltage developed at analog output (AO) is given by:
(EQ1)
Vout = Vdrk + (Re) (Ee) (t int)
where:
• V out is the analog output voltage for white condition
• V drk is the analog output voltage for dark condition
• R e is the device responsivity for a given wavelength of
light given in V/(μJ/cm2)
• E e is the incident irradiance in μW/cm 2
• t int is integration time in seconds
AO is driven by a source follower that requires an external
pulldown resistor (330Ω typical). The output is nominally 0V for
no light input, 2V for normal white-level, and 3.4V for saturation
light level. When the device is not in the output phase, AO is in
a high impedance state.
A 0.1μF bypass capacitor should be connected between VDD
and ground as close as possible to the device.
1. For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock.
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ams Datasheet
[v1-00] 2016-May-20
TSL201CL − Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. These are
stress ratings only. Functional operation of the device at these
or any other conditions beyond those indicated under
Recommended Operating Conditions is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect device reliability.
Absolute Maximum Ratings
Figure 5:
Absolute Maximum Ratings
Symbol
Min
Max
Unit
Supply voltage range
-0.3
6
V
VI
Input voltage range
-0.3
VDD + 0.3V
V
IIK
Input clamp current, (VI < 0) or (VI > VDD)
-20
20
mA
IOK
Output clamp current, (VO < 0) or (VO > VDD)
-25
25
mA
VO
Voltage range applied to any output in the high impedance or
power-off state
-0.3
VDD + 0.3V
V
IO
Continuous output current, (VO = 0 to VDD)
-25
25
mA
Continuous current through VDD or GND
-40
40
mA
IO
Analog output current range
-25
25
mA
TA
Operating free-air temperature range
-25
85
°C
Storage temperature range
-25
85
°C
260
°C
VDD
Tstrg
Parameter
Lead temperature 1.6 mm (1/16 inch) from case for
10 seconds (1)
ESDHBM
ESD tolerance, human body model
±2000
V
Note(s):
1. Not recommended for solder reflow.
ams Datasheet
[v1-00] 2016-May-20
Page 5
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TSL201CL − Electrical Characteristics
All limits are guaranteed. The parameters with min and max
values are guaranteed with production tests or
SQC (Statistical Quality Control) methods.
Electrical Characteristics
Figure 6:
Recommended Operating Conditions (see Figure 10 and Figure 11)
Symbol
VDD
Parameter
Supply voltage
Min
Nom
Max
Unit
4.5
5
5.5
V
VI
Input voltage
0
VDD
V
VIH
High-level input voltage
2
VDD
V
VIL
Low-level input voltage
0
0.8
V
400
1000
nm
5
5000
kHz
0.013
100
ms
0
70
°C
300
4700
Ω
470
pF
λ
fclock
Wavelength of light source
Clock frequency
tint
Sensor integration time
TA
Operating free-air temperature
RL
Load resistance
CL
Load capacitance
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ams Datasheet
[v1-00] 2016-May-20
TSL201CL − Electrical Characteristics
Figure 7:
Electrical Characteristics at fclock = 1MHz, VDD = 5V, TA = 25°C, λp = 640nm, tint = 5ms, RL = 330Ω,
Ee = 16.5μW/cm 2 (unless otherwise noted)
Symbol
Parameter
Test
Conditions
Min
Typ
Max
Unit
1.6
2
2.4
V
0
50
120
mV
±4%
±7.5%
Vout
Analog output voltage
(white, average over 64 pixels)
See note (1)
Vdrk
Analog output voltage
(dark, average over 64pixels)
Ee = 0
PRNU
Pixel response nonuniformity
See note (2) and
See note (3)
Nonlinearity of analog output
voltage
See note (3)
±0.4%
FS
Output noise voltage
See note (4)
1
mVrms
Re
Responsivity
See note (5)
23
V/
(μJ/cm2)
SE
Saturation exposure
See note (6)
142
nJ/cm2
Vsat
Analog output saturation voltage
3.4
V
DSNU
IL
18
2.5
Dark signal nonuniformity
All pixels, Ee = 0 (7)
Image lag
See note (8)
25
120
mV
5
mA
0.5%
IDD
Supply current, output idle
IIH
High-level input current
VI = VDD
1
μA
IIL
Low-level input current
VI = 0
1
μA
Ci(SI)
Ci(CLK)
3.4
Input capacitance, SI
5
pF
Input capacitance, CLK
5
pF
Note(s):
1. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640nm.
2. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.
3. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
4. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
5. R e(min) = [Vout(min) - Vdrk(max)] ÷ (Ee × tint)
6. Minimum saturation exposure is calculated using the minimum Vsat, the maximum Vdrk , and the maximum R e.
7. DSNU is the difference between the maximum and minimum output voltage in the absence of illumination.
8. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
V out ( IL ) – V drk
IL = -------------------------------------------- × 100
V out ( white ) – V drk
ams Datasheet
[v1-00] 2016-May-20
Page 7
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TSL201CL − Electrical Characteristics
Figure 8:
Timing Requirements (see Figure 10 and Figure 11)
Symbol
Parameter
Min
Nom
Max
Unit
tsu(SI)
Setup time, serial input (1)
20
ns
th(SI)
Hold time, serial input (1), (2)
0
ns
tw
Pulse duration, clock high or low
50
ns
tr , tf
Input transition (rise and fall) time
0
500
ns
Note(s):
1. Input pulses have the following characteristics: tr = 6ns, t f = 6ns.
2. SI must go low before the rising edge of the next clock pulse.
Figure 9:
Dynamic Characteristics Over Recommended Ranges of Supply Voltage and Operating Free-Air
Temperature (see Figure 11)
Symbol
Parameter
ts
Analog output settling time to ±1%
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Test Conditions
RL = 330Ω, CL = 10pF
Min
Typ
185
Max
Unit
ns
ams Datasheet
[v1-00] 2016-May-20
TSL201CL − Typical Operating Characteristics
Typical Operating
Characteristics
Figure 10:
Timing Waveforms
CLK
SI
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
65 Clock Cycles
AO
Hi-Z
Hi-Z
Figure 11:
Operational Waveforms
tw
1
2
64
65
5V
CLK
2.5 V
2.5 V
2.5 V
0V
tsu(SI)
5V
SI
2.5 V
2.5 V
0V
th(SI)
ts
ts
AO
Pixel 1
ams Datasheet
[v1-00] 2016-May-20
Pixel 64
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TSL201CL − Typical Operating Characteristics
Figure 12:
Photodiode Spectral Responsivity
1
TA = 25°C
Relative Responsivity
0.8
0.6
0.4
0.2
0
300
400
500
600
700
800
900
1000 1100
λ − Wavelength − nm
Figure 13:
Analog Output Settling Tine vs. Load Capacitance and
Resistance
600
470 pF
VDD = 5 V
Vout = 1 V
ts — Settling Time to 1% — ns
500
220 pF
400
100 pF
300
10 pF
200
100
0
0
200
400
600
1000
800
1200
RL − Load Resistance − Ω
Page 10
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ams Datasheet
[v1-00] 2016-May-20
TSL201CL − Application Information
Application Information
Power Supply Considerations
For optimum device performance, power-supply lines should
be decoupled by a 0.01μF to 0.1μF capacitor with short leads
mounted close to the device package.
Integration Time
The integration time of the linear array is the period during
which light is sampled and charge accumulates on each pixel’s
integrating capacitor. The flexibility to adjust the integration
period is a powerful and useful feature of the ams TSL2xx linear
array family. By changing the integration time, a desired output
voltage can be obtained on the output pin while avoiding
saturation for a wide range of light levels.
Each pixel of the linear array consists of a light-sensitive
photodiode. The photodiode converts light intensity to a
voltage. The voltage is sampled on the Sampling Capacitor by
closing switch S2 (position 1) (see Figure 2). Logic controls the
resetting of the Integrating Capacitor to zero by closing switch
S1 (position 2).
At SI input (Start Integration), pixel 1 is accessed. During this
event, S2 moves from position 1 (sampling) to position 3
(holding). This holds the sampled voltage for pixel 1. Switch S1
for pixel 1 is then moved to position 2. This resets (clears) the
voltage previously integrated for that pixel so that pixel 1 is now
ready to start a new integration cycle. When the next clock
period starts, the S1 switch is returned to position 1 to be ready
to start integrating again. S2 is returned to position 1 to start
sampling the next light integration. Then the next pixel starts
the same procedure. The integration time is the time from a
specific pixel read to the next time that pixel is read again. If
either the clock speed or the time between successive SI pulses
is changed, the integration time will vary. After the final (nth)
pixel in the array is read on the output, the output goes into a
high-impedance mode. A new SI pulse can occur on the (n+1)
clock causing a new cycle of integration/output to begin. Note
that the time between successive SI pulses must not exceed the
maximum integration time of 100ms.
The minimum integration time for any given array is determined
by time required to clock out all the pixels in the array and the
time to discharge the pixels. The time required to discharge the
pixels is a constant. Therefore, the minimum integration period
is simply a function of the clock frequency and the number of
pixels in the array. A slower clock speed increases the minimum
integration time and reduces the maximum light level for
saturation on the output. The minimum integration time shown
in this data sheet is based on the maximum clock frequency of
5 MHz.
ams Datasheet
[v1-00] 2016-May-20
Page 11
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TSL201CL − Application Information
The minimum integration time can be calculated from the
equation:
(EQ2)
T
int ( min )
1
=  -------------------------------------------------------------------------- × n
 maximum clock frequency
where:
n is the number of pixels
In the case of the TSL201CL, the minimum integration time
would be:
T int(min) = 200ns × 64 = 12.8 μ s
It is important to note that not all pixels will have the same
integration time if the clock frequency is varied while data is
being output.
It is good practice on initial power up to run the clock (n+1)
times after the first SI pulse to clock out indeterminate data
from power up. After that, the SI pulse is valid from the time
following (n+1) clocks. The output will go into a
high-impedance state after the n+1 high clock edge. It is good
practice to leave the clock in a low state when inactive because
the SI pulse required to start a new cycle is a low-to-high
transition.
The integration time chosen is valid as long as it falls in the
range between the minimum and maximum limits for
integration time. If the amount of light incident on the array
during a given integration period produces a saturated output
(Max Voltage output), then the data is not accurate. If this
occurs, the integration period should be reduced until the
analog output voltage for each pixel falls below the saturation
level. The goal of reducing the period of time the light sampling
window is active is to lower the output voltage level to prevent
saturation. However, the integration time must still be greater
than or equal to the minimum integration period.
If the light intensity produces an output below desired signal
levels, the output voltage level can be increased by increasing
the integration period provided that the maximum integration
time is not exceeded. The maximum integration time is limited
by the length of time the integrating capacitors on the pixels
can hold their accumulated charge. The maximum integration
time should not exceed 100 ms for accurate measurements.
Although the linear array is capable of running over a wide
range of operating frequencies up to a maximum of 5 MHz, the
speed of the A/D converter used in the application is likely to
be the limiter for the maximum clock frequency. The voltage
output is available for the whole period of the clock, so the
setup and hold times required for the analog-to-digital
conversion must be less than the clock period.
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ams Datasheet
[v1-00] 2016-May-20
TSL201CL − Application Information: Hardware
Suggested PCB pad layout guidelines for the CL package are
shown in Figure 14.
Application Information:
Hardware
Figure 14:
Suggested CL Package PCB Layout
Pin 1
1.3
1.4
2.5
0.8
0.8
Note(s):
1. All linear dimensions are in millimeters.
2. This drawing is subject to change without notice.
ams Datasheet
[v1-00] 2016-May-20
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TSL201CL − Package Drawings & Markings
Package Drawings & Markings
Figure 15:
Package CL Configuration
TOP VIEW
0.120
(Note 2)
3.0 0.2
Pin 1
7.943 (Note 2)
Photodiode Array
(Not to Scale)
9.4 0.2
SIDE VIEW
END VIEW
0.22
1.2 0.2
BOTTOM
VIEW
CL of Solder Contact
CL of Pixel 1 (Note 3)
Photodiode Array
(Not to Scale)
0.026 Nominal
Pin 1
0.95
0.8
0.95
0.6
0.274
Nominal
CL of Package
1.8
CL of Photodiode Array Area (Note 3)
0.6
1.0
2.5
Pb
7.5 0.08
RoHS
Green
Note(s):
1. All linear dimensions are in millimeters. Dimension tolerance is ± 0.05mm unless otherwise noted.
2. Nominal photodiode array dimension. The array is made up of 64 pixels with pixel #1 closer to Pin 1. Each pixel is 68μm wide by
120μm high, spaced on 125μm centers.
3. The die is centered within the package within a tolerance of ± 0.05mm.
4. Package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.56.
5. Contact finish is soft gold plated.
6. This package contains no lead (Pb).
7. This drawing is subject to change without notice.
Page 14
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ams Datasheet
[v1-00] 2016-May-20
TSL201CL − Carrier Tape & Reel Information
Carrier Tape & Reel Information
Figure 16:
Package CL Carrier Tape
TOP VIEW
2.00
4.00
8.00
1.50
+ 0.10
− 0.00
1.75
B
16.00
+ 0.30
− 0.10
7.50
1.50
+ 0.25
− 0.00
A
A
DETAIL B
DETAIL A
8 Max
3.45
B
0.30
0.02
Ao
7 Max
9.85
1.53
Bo
Ko
Note(s):
1. All linear dimensions are in millimeters. Dimension tolerance is ± 0.10 mm unless otherwise noted.
2. The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly.
3. Symbols on drawing Ao, Bo, and Ko are defined in ANSI EIA Standard 481−B 2001.
4. Each reel is 178 millimeters in diameter and contains 1000 parts.
5. ams packaging tape and reel conform to the requirements of EIA Standard 481−B.
6. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape.
7. This drawing is subject to change without notice.
ams Datasheet
[v1-00] 2016-May-20
Page 15
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TSL201CL − Soldering & Storage Information
The CL package has been tested and has demonstrated an
ability to be reflow soldered to a PCB substrate. The solder
reflow profile describes the expected maximum heat exposure
of components during the solder reflow process of product on
a PCB. Temperature is measured on top of component. The
components should be limited to a maximum of three passes
through this solder reflow profile.
Soldering & Storage
Information
Figure 17:
Solder Reflow Profile
Parameter
Reference
Average temperature gradient in preheating
Device
2.5 ºC/s
tsoak
2 to 3 minutes
Time above 217 ºC (T1)
t1
Max 60 s
Time above 230 ºC (T2)
t2
Max 50 s
Time above Tpeak - 10 ºC (T3)
t3
Max 10 s
Peak temperature in reflow
Tpeak
260 ºC
Soak time
Temperature gradient in cooling
Max -5 ºC/s
Figure 18:
Solder Reflow Profile Graph
Tpeak
Not to scale — for reference only
T3
T2
Temperature (C)
T1
Time (s)
t3
t2
tsoak
t1
Figure 8. Solder Reflow Profile Graph
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ams Datasheet
[v1-00] 2016-May-20
TSL201CL − Soldering & Storage Information
Moisture Sensitivity
Optical characteristics of the device can be adversely affected
during the soldering process by the release and vaporization of
moisture that has been previously absorbed into the package.
To ensure the package contains the smallest amount of
absorbed moisture possible, each device is dry-baked prior to
being packed for shipping. Devices are packed in a sealed
aluminized envelope called a moisture barrier bag with silica
gel to protect them from ambient moisture during shipping,
handling, and storage before use.
The CL package has been assigned a moisture sensitivity level
of MSL 5a and the devices should be stored under the following
conditions:
• Temperature Range: 5°C to 50°C
• Relative Humidity: 60% maximum
• Total Time: 6 months from the date code on the
aluminized envelope - if unopened
• Opened Time: 24 hours or fewer
Rebaking will be required if the devices have been stored
unopened for more than 6 months or if the aluminized envelope
has been open for more than 24 hours. If rebaking is required,
it should be done at 60°C for 24 hours.
ams Datasheet
[v1-00] 2016-May-20
Page 17
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TSL201CL − Ordering & Contact Information
Ordering & Contact Information
Figure 19:
Ordering Information
Ordering Code
Type
Delivery Form
Delivery Quantity
TSL201CL
64 x 1 Array
Tape & Reel
1000 pcs/reel
Buy our products or get free samples online at:
www.ams.com/ICdirect
Technical Support is available at:
www.ams.com/Technical-Support
Provide feedback about this document at:
www.ams.com/Document-Feedback
For further information and requests, e-mail us at:
[email protected]
For sales offices, distributors and representatives, please visit:
www.ams.com/contact
Headquarters
ams AG
Tobelbaderstrasse 30
8141 Premstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
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ams Datasheet
[v1-00] 2016-May-20
TSL201CL − RoHS Compliant & ams Green Statement
RoHS Compliant & ams Green
Statement
RoHS: The term RoHS compliant means that ams AG products
fully comply with current RoHS directives. Our semiconductor
products do not contain any chemicals for all 6 substance
categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to
be soldered at high temperatures, RoHS compliant products are
suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br): ams Green
defines that in addition to RoHS compliance, our products are
free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous
material).
Important Information: The information provided in this
statement represents ams AG knowledge and belief as of the
date that it is provided. ams AG bases its knowledge and belief
on information provided by third parties, and makes no
representation or warranty as to the accuracy of such
information. Efforts are underway to better integrate
information from third parties. ams AG has taken and continues
to take reasonable steps to provide representative and accurate
information but may not have conducted destructive testing or
chemical analysis on incoming materials and chemicals. ams AG
and ams AG suppliers consider certain information to be
proprietary, and thus CAS numbers and other limited
information may not be available for release.
ams Datasheet
[v1-00] 2016-May-20
Page 19
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TSL201CL − Copyrights & Disclaimer
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten,
Austria-Europe. Trademarks Registered. All rights reserved. The
material herein may not be reproduced, adapted, merged,
translated, stored, or used without the prior written consent of
the copyright owner.
Devices sold by ams AG are covered by the warranty and patent
indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied,
or by description regarding the information set forth herein.
ams AG reserves the right to change specifications and prices
at any time and without notice. Therefore, prior to designing
this product into a system, it is necessary to check with ams AG
for current information. This product is intended for use in
commercial applications. Applications requiring extended
temperature range, unusual environmental requirements, or
high reliability applications, such as military, medical
life-support or life-sustaining equipment are specifically not
recommended without additional processing by ams AG for
each application. This product is provided by ams AG “AS IS”
and any express or implied warranties, including, but not
limited to the implied warranties of merchantability and fitness
for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any
damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interruption of business or
indirect, special, incidental or consequential damages, of any
kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation
or liability to recipient or any third party shall arise or flow out
of ams AG rendering of technical or other services.
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ams Datasheet
[v1-00] 2016-May-20
TSL201CL − Document Status
Document Status
Document Status
Product Preview
Preliminary Datasheet
Datasheet
Datasheet (discontinued)
ams Datasheet
[v1-00] 2016-May-20
Product Status
Definition
Pre-Development
Information in this datasheet is based on product ideas in
the planning phase of development. All specifications are
design goals without any warranty and are subject to
change without notice
Pre-Production
Information in this datasheet is based on products in the
design, validation or qualification phase of development.
The performance and parameters shown in this document
are preliminary without any warranty and are subject to
change without notice
Production
Information in this datasheet is based on products in
ramp-up to full production or full production which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade
Discontinued
Information in this datasheet is based on products which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade, but these products have been superseded and
should not be used for new designs
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TSL201CL − Revision Information
Revision Information
Changes from TAOS146 (2012-Apr) to current revision 1-00 (2016-May-20)
Page
Content of TAOS datasheet was converted to the latest ams design
Added Figure 1
1
Added Figure 19
18
Note(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
2. Correction of typographical errors is not explicitly mentioned.
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ams Datasheet
[v1-00] 2016-May-20
TSL201CL − Content Guide
Content Guide
ams Datasheet
[v1-00] 2016-May-20
1
1
2
General Description
Key Benefits & Features
Block Diagram
3
4
5
6
9
Pin Assignment
Detailed Description
Absolute Maximum Ratings
Electrical Characteristics
Typical Operating Characteristics
11
11
11
Application Information
Power Supply Considerations
Integration Time
13
14
15
Application Information: Hardware
Package Drawings & Markings
Carrier Tape & Reel Information
16
17
Soldering & Storage Information
Moisture Sensitivity
18
19
20
21
22
Ordering & Contact Information
RoHS Compliant & ams Green Statement
Copyrights & Disclaimer
Document Status
Revision Information
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