ICS85322I Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR GENERAL DESCRIPTION FEATURES The ICS85322I is a Dual LVCMOS / LVTTL-toDifferential 2.5V / 3.3V LVPECL translator and a HiPerClockS™ member of the HiPerClocks™family of High Perfor mance Clocks Solutions from ICS. The ICS85322I has selectable single ended clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels and translate them to 2.5V / 3.3V LVPECL levels. The small outline 8-pin SOIC package makes this device ideal for applications where space, high performance and low power are important. • 2 differential 2.5V/3.3V LVPECL outputs ICS • Selectable CLK0, CLK1 LVCMOS/LVTTL clock inputs • CLK0 and CLK1 can accepts the following input levels: LVCMOS or LVTTL • Maximum output frequency: 267MHz • Part-to-part skew: 250ps (maximum) • 3.3V operating supply voltage (operating range 3.135V to 3.465V) • 2.5V operating supply voltage (operating range 2.375V to 2.625V) • -40°C to 85°C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT CLK0 Q0 nQ0 CLK1 Q1 nQ1 Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 VCC CLK0 CLK1 VEE ICS85322I 8-Lead SOIC 3.90mm x 4.92mm x 1.37mm body package M Package Top View 85322AMI www.icst.com/products/hiperclocks.html 1 REV. B OCTOBER 7, 2003 ICS85322I Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 Q0, nQ0 Output Type Differential output pair. LVPECL interface levels. Description 3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 5 VEE Power Negative supply pin. 6 CLK1 Input Pullup 7 CLK0 Input Pullup 8 VCC Power LVCMOS / LVTTL clock input. LVCMOS / LVTTL clock input. Positive supply pin. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ 85322AMI Test Conditions Minimum www.icst.com/products/hiperclocks.html 2 Typical Maximum Units REV. B OCTOBER 7, 2003 ICS85322I Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 112.7°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions VCC Positive Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 25 mA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage CLK0, CLK1 Test Conditions VIL Input Low Voltage CLK0, CLK1 IIH Input High Current CLK0, CLK1 VCC = VIN = 3.465V IIL Input Low Current CLK0, CLK1 VCC = VIN = 3.465V Minimum Maximum Units 2 Typical VCC + 0.3 V -0.3 1.3 V 5 µA -150 µA TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum VOH Output High Voltage; NOTE 1 VCC = VIN = 3.465V VOL Output Low Voltage; NOTE 1 VCC = VIN = 3.465V VSWING Peak-to-Peak Output Voltage Swing Typical Maximum Units VCC - 1.4 VCC - 1.0 V VCC - 2.0 VCC - 1.7 V 0.65 0.9 V Maximum Units 267 MHz NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 4A. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 t sk(pp) Par t-to-Par t Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time Test Conditions ƒ ≤ 267MHz 20% to 80% @ 50MHz Minimum 0.5 300 Typical 1.9 ns 250 ps 700 ps odc Output Duty Cycle 40 60 % All parameters measured at 133MHz unless noted otherwise. NOTE 1: Measured from VCC/2 point of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 85322AMI www.icst.com/products/hiperclocks.html 3 REV. B OCTOBER 7, 2003 ICS85322I Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR TABLE 3D. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions VCC Positive Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 2.375 2.5 2.625 V 25 mA Maximum Units TABLE 3E. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage CLK0, CLK1 1.6 VCC + 0.3 V VIL Input Low Voltage CLK0, CLK1 -0.3 0.9 V IIH Input High Current CLK0, CLK1 VCC = VIN = 2.625 5 µA IIL Input Low Current CLK0, CLK1 VCC = VIN = 2.625 -150 µA TABLE 3F. LVPECL DC CHARACTERISTICS, VCC = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCC - 1.4 Typical VCC - 1.0 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.65 0.9 V Maximum Units 215 MHz NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 4B. AC CHARACTERISTICS, VCC = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 tsk(pp) Par t-to-Par t Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time Test Conditions ƒ ≤ 215MHz 20% to 80% @ 50MHz Minimum 0.7 300 Typical 2.1 ns 250 ps 700 ps odc Output Duty Cycle 40 60 % All parameters measured at 133MHz unless noted otherwise. NOTE 1: Measured from VCC/2 point of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.. 85322AMI www.icst.com/products/hiperclocks.html 4 REV. B OCTOBER 7, 2003 ICS85322I Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR PARAMETER MEASUREMENT INFORMATION 2V 2V V CC Qx SCOPE VCC Qx SCOPE LVPECL LVPECL nQx nQx VEE VEE -0.5V ± 0.125V -1.3V ± 0.165V 2.5V OUTPUT LOAD AC TEST CIRCUIT 3.3V OUTPUT LOAD AC TEST CIRCUIT nQx CLK0, CLK1 PART 1 Qx nQ0, nQ1 nQy PART 2 Q0, Q1 Qy tPD t sk(o) PART-TO-PART SKEW PROPAGATION DELAY nQ0, nQ1 80% 80% Q0, Q1 VSW I N G Clock Outputs Pulse Width 20% 20% tR t PERIOD tF odc = t PW t PERIOD OUTPUT RISE/FALL TIME 85322AMI OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD www.icst.com/products/hiperclocks.html 5 REV. B OCTOBER 7, 2003 ICS85322I Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR APPLICATION INFORMATION TERMINATION FOR 3.3V LVPECL OUTPUTS 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 1A and 1B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω 50Ω RTT = 1 Zo (VOH + VOL / VCC – 2) – 2 FOUT 50Ω VCC - 2V Zo = 50Ω RTT 84Ω FIGURE 1A. LVPECL OUTPUT TERMINATION 85322AMI FIN 84Ω FIGURE 1B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 6 REV. B OCTOBER 7, 2003 ICS85322I Integrated Circuit Systems, Inc. TERMINATION FOR DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR 2.5V LVPECL OUTPUT Figure 2A and Figure 2B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 2B can be eliminated and the termination is shown in Figure 2C. 2.5V 2.5V 2.5V VCCO=2.5V VCCO=2.5V R1 250 R3 250 Zo = 50 Ohm Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - - 2,5V LVPECL Driv er 2,5V LVPECL Driv er R2 62.5 R1 50 R4 62.5 R2 50 R3 18 FIGURE 2B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 2A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 2C. 2.5V LVPECL TERMINATION EXAMPLE 85322AMI www.icst.com/products/hiperclocks.html 7 REV. B OCTOBER 7, 2003 ICS85322I Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS85322I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85322I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 25mA = 86.6mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW Total Power_MAX (3.465V, with all outputs switching) = 86.6mW + 60.4mW = 147mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.147W * 103.3°C/W = 100.2°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 5. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 85322AMI www.icst.com/products/hiperclocks.html 8 REV. B OCTOBER 7, 2003 ICS85322I Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 3. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 3. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V OH_MAX (V CC_MAX • -V OH_MAX OL_MAX CC_MAX -V OL_MAX CC_MAX – 1.0V ) = 1.0V For logic low, VOUT = V (V =V =V CC_MAX – 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V Pd_H = [(V – (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= OH_MAX CC_MAX CC_MAX OH_MAX CC_MAX OH_MAX CC_MAX OH_MAX L L [(2V - 1V)/50Ω] * 1V = 20.0mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW 85322AMI www.icst.com/products/hiperclocks.html 9 REV. B OCTOBER 7, 2003 ICS85322I Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS85322I is: 269 85322AMI www.icst.com/products/hiperclocks.html 10 REV. B OCTOBER 7, 2003 ICS85322I Integrated Circuit Systems, Inc. PACKAGE OUTLINE - M SUFFIX DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR FOR 8 LEAD SOIC TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters MINIMUN N A MAXIMUM 8 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BASIC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-012 85322AMI www.icst.com/products/hiperclocks.html 11 REV. B OCTOBER 7, 2003 ICS85322I Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS85322AMI 5322AMI 8 lead SOIC 96 per tube -40°C to 85°C ICS85322AMIT 5322AMI 8 lead SOIC on Tape and Reel 2500 -40°C to 85°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85322AMI www.icst.com/products/hiperclocks.html 12 REV. B OCTOBER 7, 2003 ICS85322I Integrated Circuit Systems, Inc. DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR REVISION HISTORY SHEET Rev Table A Page 8 6 Added Termination for LVPECL Outputs section. 3.3V Output Load Test Circuit Diagram, corrected VEE = -1.3V ± 0.135V to read VEE = -1.3V ± 0.165V. 7 2 3 6 7 Updated Output Rise/Fall Time Diagram. Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. Absolute Maximum Ratings, updated Inputs ratings. Updated 3.3V LVPECL Output Termination Diagrams. A T2 B 85322AMI Description of Change Date 5/30/02 8/23/02 10/7/03 Added Termination for 2.5V LVPECL Outputs. Updated format throughout data sheet. www.icst.com/products/hiperclocks.html 13 REV. B OCTOBER 7, 2003