ISC 2N5955

Inchange Semiconductor
Product Specification
2N5954 2N5955 2N5956
Silicon PNP Power Transistors
DESCRIPTION
・With TO-66 package
・Low collector saturation voltage
・Excellent safe operating area
・Complement to type 2N6372/6373/6374
APPLICATIONS
・Designed for driver circuits,switching
and amplifier applications
PINNING
PIN
DESCRIPTION
1
Base
2
Emitter
3
Collector
Fig.1 simplified outline (TO-66) and symbol
Absolute maximum ratings(Ta=℃)
SYMBOL
PARAMETER
CONDITIONS
2N5954
VCBO
VCEO
Collector-base voltage
Collector-emitter voltage
2N5955
Open emitter
-70
2N5956
-50
2N5954
-80
2N5955
Emitter-base voltage
UNIT
-90
Open base
2N5956
VEBO
VALUE
-60
V
V
-40
Open collector
-5
V
IC
Collector current
-6
A
IB
Base current
-2
A
PD
Total Power Dissipation
40
W
Tj
Junction temperature
150
℃
Tstg
Storage temperature
-65~200
℃
VALUE
UNIT
4.3
℃/W
TC=25℃
THERMAL CHARACTERISTICS
SYMBOL
Rth j-c
PARAMETER
Thermal resistance junction to case
Inchange Semiconductor
Product Specification
2N5954 2N5955 2N5956
Silicon PNP Power Transistors
CHARACTERISTICS
Tj=25℃ unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
2N5954
VCEO(SUS)
Collector-emitter
sustaining voltage
2N5955
VBE-1
VBE-2
ICEO
Collector-emitter
saturation voltage
Base-emitter on voltage
IC=-0.1A ;IB=0
Collector cut-off current
MAX
UNIT
V
-60
-40
2N5954
IC=-2A; IB=-0.2A
2N5955
IC=-2.5A; IB=-0.25A
2N5956
IC=-3A; IB=-0.3A
2N5954
IC=-2A ; VCE=-4V
2N5955
IC=-2.5A ; VCE=-4V
2N5956
IC=-3A ; VCE=-4V
Base-emitter on voltage
TYP.
-80
2N5956
VCEsat
MIN
IC=-6A ; VCE=-4V
2N5954
VCE=-65V; IB=0
2N5955
VCE=-45V; IB=0
2N5956
VCE=-25V; IB=0
-1.0
V
-2.0
V
-3.0
V
-1.0
mA
ICEV
Collector cut-off current(RBE=100Ω)
VCE=Rated VCE; VBE(off)=1.5V
TC=150℃
-0.1
-2.0
mA
IEBO
Emitter cut-off current
VEB=-5V; IC=0
-0.1
mA
hFE-1
hFE-2
fT
DC current gain
2N5954
IC=-2A ; VCE=-4V
2N5955
IC=-2.5A ; VCE=-4V
2N5956
IC=-3A ; VCE=-4V
20
DC current gain
IC=-6A ; VCE=-4V
5
Transition frequency
IC=-1A;VCE=-4V;f=1.0MHz
5
2
100
MHz
Inchange Semiconductor
Product Specification
2N5954 2N5955 2N5956
Silicon PNP Power Transistors
PACKAGE OUTLINE
Fig.2 outline dimensions
3