CSD17312Q5 www.ti.com SLPS256A – MARCH 2010 – REVISED OCTOBER 2010 30V N-Channel NexFET™ Power MOSFET Check for Samples: CSD17312Q5 PRODUCT SUMMARY FEATURES 1 • • • • • • • • 2 Optimized for 5V Gate Drive Ultra Low Qg and Qgd Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free SON 5-mm × 6-mm Plastic Package The NexFET™ power MOSFET has been designed to minimize losses in power conversion applications and optimized for 5V gate drive applications. Top View 8 V Gate Charge Total (4.5V) 28 nC Qgd Gate Charge Gate to Drain Drain to Source On Resistance 6 nC VGS = 3V 1.8 mΩ VGS = 4.5V 1.4 mΩ VGS = 8V 1.2 mΩ Threshold Voltage 1.1 V ORDERING INFORMATION DESCRIPTION 1 30 Qg VGS(th) Notebook Point-of-Load Point-of-Load Synchronous Buck in Networking, Telecom and Computing Systems S Drain to Source Voltage RDS(on) APPLICATIONS • • VDS Device Package Media CSD17312Q5 SON 5-mm × 6-mm Plastic Package 13-Inch Reel Qty Ship 2500 Tape and Reel ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise stated VALUE UNIT VDS Drain to Source Voltage 30 V VGS Gate to Source Voltage +10 / –8 V Continuous Drain Current, TC = 25°C 100 A Continuous Drain Current(1) 38 A IDM Pulsed Drain Current, TA = 25°C(2) 200 A PD Power Dissipation(1) 3.2 W TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, Single Pulse ID = 130A, L = 0.1mH, RG = 25Ω 845 mJ ID D S 2 7 D S 3 6 D G 4 5 D (1) Typical RqJA = 39°C/W when mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB. (2) Pulse duration ≤300ms, duty cycle ≤2% TextAddedForSpacing Text_added_for_spacing_Text_added_for_spacing D P0094-01 RDS(on) vs VGS GATE CHARGE 8 ID = 35A 3.5 VGS - Gate-to-Source Voltage - V RDS(on) - On-State Resistance - mΩ 4 3 T C = 125°C 2.5 2 1.5 1 T C = 25°C 0.5 ID = 35A VDS = 15V 7 6 5 4 3 2 1 0 0 0 1 2 3 4 5 6 7 8 VGS - Gate-to-Source Voltage - V 9 10 G006 0 10 20 30 Qg - Gate Charge - nC 40 50 G003 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated CSD17312Q5 SLPS256A – MARCH 2010 – REVISED OCTOBER 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, ID = 250mA IDSS Drain to Source Leakage Current VGS = 0V, VDS = 24V IGSS Gate to Source Leakage Current VDS = 0V, VGS = +10/–8V VGS(th) Gate to Source Threshold Voltage VDS = VGS, ID = 250mA RDS(on) Drain to Source On Resistance gfs Transconductance 30 0.9 V 1 mA 100 nA 1.1 1.5 V VGS = 3V, ID = 35A 1.8 2.4 mΩ VGS = 4.5V, ID = 35A 1.4 1.7 mΩ VGS = 8V, ID = 35A 1.2 1.5 mΩ VDS = 15V, ID = 35A 200 S Dynamic Characteristics Ciss Input Capacitance VGS = 0V, VDS = 15V, f = 1MHz 4030 5240 pF 2220 2890 pF Coss Output Capacitance Crss Reverse Transfer Capacitance 93 120 pF RG Series Gate Resistance 1.1 2.2 Ω Qg Gate Charge Total (4.5V) 28 36 nC Qgd Gate Charge Gate to Drain Qgs Gate Charge Gate to Source Qg(th) Gate Charge at Vth Qoss Output Charge td(on) 6 nC 8.4 nC 4.4 nC 57 nC Turn On Delay Time 9.5 ns tr Rise Time 27 ns td(off) Turn Off Delay Time 35 ns tf Fall Time 23 ns VDS = 15V, IDS = 35A VDS = 14.8V, VGS = 0V VDS = 15V, VGS = 4.5V, IDS = 35A, RG = 2Ω Diode Characteristics VSD Diode Forward Voltage ISD = 35A, VGS = 0V 0.8 Qrr Reverse Recovery Charge 88 nC trr Reverse Recovery Time VDD = 14.8V, IF = 35A, di/dt = 300A/ms 1 V 43 ns THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER RqJC Thermal Resistance Junction to Case (1) RqJA Thermal Resistance Junction to Ambient (1) (2) (1) (2) 2 MIN TYP MAX UNIT 1 °C/W 49 °C/W RqJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RqJC is specified by design, whereas RqJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17312Q5 CSD17312Q5 www.ti.com SLPS256A – MARCH 2010 – REVISED OCTOBER 2010 GATE GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RqJA = 49°C/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Source Max RqJA = 119°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 Text Added For Spacing Text Added For Spacing Text Added For Spacing Text Added For Spacing TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unless otherwise stated) ZqJA - Normalized Thermal Impedance 10 1 0.5 0.3 0.1 Duty Cycle = t1/t2 0.1 0.05 P 0.02 0.01 t1 0.01 t2 Typical RqJA = 95°C/W (min Cu) TJ = P ´ ZqJA ´ RqJA Single Pulse 0.001 0.001 0.01 0.1 1 tp - Pulse Duration - s 10 100 1k G012 Figure 1. Transient Thermal Impedance Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17312Q5 3 CSD17312Q5 SLPS256A – MARCH 2010 – REVISED OCTOBER 2010 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 90 VGS = 2.5V IDS - Drain-to-Source Current - A IDS - Drain-to-Source Current - A 100 80 VGS = 3V 70 60 VGS = 3.5V 50 40 VGS = 4.5V 30 VGS = 8V 20 0 0.1 0.2 0.3 0.4 VDS - Drain-to-Source Voltage - V T C = 125°C 60 50 T C = 25°C 40 T C = -55°C 30 20 0 0.5 0.5 G001 1 1.5 2 VGS - Gate-to-Source Voltage - V 2.5 3 G002 Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 12 8 ID = 35A VDS = 15V 7 f = 1MHz VGS = 0V 10 6 C - Capacitance - nF VGS - Gate-to-Source Voltage - V 70 0 0 5 4 3 2 8 Coss = Cds + Cgd 6 Ciss = Cgd + Cgsgs 4 Crss = CGgd 2 1 0 0 0 10 20 30 Qg - Gate Charge - nC 40 50 0 10 15 20 VDS - Drain-to-Source Voltage - V 25 Figure 4. Gate Charge Figure 5. Capacitance TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 30 G004 4 RDS(on) - On-State Resistance - mΩ ID = 250µA 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -75 5 G003 1.6 VGS(th) - Threshold Voltage - V 80 10 10 ID = 35A 3.5 3 T C = 125°C 2.5 2 1.5 1 T C = 25°C 0.5 0 -25 25 75 T C - Case Temperature - °C 125 175 0 1 G005 Figure 6. Threshold Voltage vs. Temperature 4 VDS = 5V 90 2 3 4 5 6 7 8 VGS - Gate-to-Source Voltage - V 9 10 G006 Figure 7. On-State Resistance vs. Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17312Q5 CSD17312Q5 www.ti.com SLPS256A – MARCH 2010 – REVISED OCTOBER 2010 TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 ID = 35A VGS = 8V 1.6 ISD - Source-to-Drain Current - A Normalized On-State Resistance 1.8 1.4 1.2 1 0.8 0.6 0.4 0.2 -75 1 T C = 125°C 0.1 T C = 25°C 0.01 0.001 0.0001 -25 25 75 T C - Case Temperature - °C 125 0 175 0.2 G007 0.4 0.6 0.8 VSD - Source-to-Drain Voltage - V Figure 8. Normalized On-State Resistance vs. Temperature Figure 9. Typical Diode Forward Voltage TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 1ms 10 10ms 11110 100ms 1 Area Limited by RDS(on) 0.1 0.01 0.01 1 G008 1k I(AV) - Peak Avalanche Current - A 1k IDS - Drain-to-Source Current - A 10 1s Single Pulse Typical R θJA = 95°C/W (min Cu) DC 0.1 1 10 VDS - Drain-to-Source Voltage - V 100 10 T C = 125°C 1 0.01 G009 Figure 10. Maximum Safe Operating Area T C = 25°C 100 0.1 1 10 t(AV) - Time in Avalanche - ms 100 G010 Figure 11. Single Pulse Unclamped Inductive Switching TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING IDS - Drain-to-Source Current - A 120 100 80 60 40 20 0 -50 -25 0 25 50 75 100 125 T C - Case Temperature - °C 150 175 G011 Figure 12. Maximum Drain Current vs. Temperature Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17312Q5 5 CSD17312Q5 SLPS256A – MARCH 2010 – REVISED OCTOBER 2010 www.ti.com MECHANICAL DATA Q5 Package Dimensions K L L c1 E1 E2 b D2 4 4 5 5 e 3 6 3 6 E D1 7 7 2 2 8 8 1 1 q Top View Bottom View Side View c E1 A q Front View M0140-01 DIM MILLIMETERS MAX MIN MAX A 0.950 1.050 0.037 0.039 b 0.360 0.460 0.014 0.018 c 0.150 0.250 0.006 0.010 c1 0.150 0.250 0.006 0.010 D1 4.900 5.100 0.193 0.201 D2 4.320 4.520 0.170 0.178 E 4.900 5.100 0.193 0.201 E1 5.900 6.100 0.232 0.240 E2 3.920 4.12 0.154 e 6 INCHES MIN 1.27 TYP K 0.760 L 0.510 q 0.00 0.162 0.050 0.030 0.710 Submit Documentation Feedback 0.020 0.028 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17312Q5 CSD17312Q5 www.ti.com SLPS256A – MARCH 2010 – REVISED OCTOBER 2010 Recommended PCB Pattern F1 F7 DIM F3 8 1 F2 F11 F5 F9 5 4 F6 F8 F4 F10 M0139-01 MILLIMETERS INCHES MIN MAX MIN MAX F1 6.205 6.305 0.244 0.248 F2 4.460 4.560 0.176 0.180 F3 4.460 4.560 0.176 0.180 F4 0.650 0.700 0.026 0.028 F5 0.620 0.670 0.024 0.026 F6 0.630 0.680 0.025 0.027 F7 0.700 0.800 0.028 0.031 F8 0.650 0.700 0.026 0.028 F9 0.620 0.670 0.024 0.026 F10 4.900 5.000 0.193 0.197 F11 4.460 4.560 0.176 0.180 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 Text added for spacing Text added for spacing Q5 Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 R 0.30 TYP M0138-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm, unless otherwise specified. 5. Thickness: 0.30 ±0.05mm 6. MSL1 260°C (IR and convection) PbF reflow compatible Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17312Q5 7 CSD17312Q5 SLPS256A – MARCH 2010 – REVISED OCTOBER 2010 www.ti.com REVISION HISTORY Changes from Original (March 2010) to Revision A • 8 Page Deleted the Package Marking Information section ............................................................................................................... 7 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17312Q5 PACKAGE MATERIALS INFORMATION www.ti.com 4-Feb-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device CSD17312Q5 Package Package Pins Type Drawing SON DQH 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.8 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 5.3 1.4 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Feb-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD17312Q5 SON DQH 8 2500 335.0 335.0 32.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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