SCAS046A − D3148, AUGUST 1988 − REVISED APRIL 1993
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54ACT11280 . . . J PACKAGE
74ACT11280 . . . D OR N PACKAGE
Inputs Are TTL-Voltage Compatible
Generates Either Odd or Even Parity for
Nine Data Lines
Cascadable for n-Bits Parity
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity
at 125°C
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
(TOP VIEW)
B
A
Σ ODD
GND
Σ EVEN
NC
I
1
14
2
13
3
12
4
11
5
10
6
9
7
8
C
D
E
VCC
F
G
H
54ACT11280 . . . FK PACKAGE
(TOP VIEW)
D
E
NC
V CC
F
•
•
C
NC
B
NC
A
description
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
G
NC
H
NC
I
Σ ODD
GND
NC
Σ EVEN
NC
These universal, monolithic, 9-bit parity
generators/checkers feature odd and even
outputs to facilitate operation of either an odd or
even parity application.
The word-length
capability is easily expanded by cascading.
4
The 54ACT11280 is characterized for operation
over the full military temperature range of − 55°C
to 125°C. The 74ACT11280 is characterized for
operation from − 40°C to 85°C.
NC − No internal connection
logic symbol†
FUNCTION TABLE
NUMBER OF INPUTS
A THRU I
THAT ARE HIGH
S EVEN
S ODD
0, 2, 4, 6, 8
H
L
1, 3, 5, 7, 9
L
H
OUTPUTS
A
B
C
D
E
F
G
H
I
2
2k
1
14
13
5
12
10
9
3
Σ EVEN
Σ ODD
8
7
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
!"#$%&'#! ( )*$$+!' &( #" ,*-.)&'#! /&'+0
$#/*)'( )#!"#$% '# (,+)")&'#!( ,+$ '1+ '+$%( #" +2&( !('$*%+!'(
('&!/&$/ 3&$$&!'40 $#/*)'#! ,$#)+((!5 /#+( !#' !+)+((&$.4 !).*/+
'+('!5 #" &.. ,&$&%+'+$(0
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
•
2−1
SCAS046A − D3148, AUGUST 1988 − REVISED APRIL 1993
logic diagram (positive logic)
2
A
B
C
D
E
F
G
H
I
1
14
5
Σ EVEN
3
Σ ODD
13
12
10
9
8
7
Pin numbers shown are for the D, J, and N packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 00 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2−2
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•
SCAS046A − D3148, AUGUST 1988 − REVISED APRIL 1993
recommended operating conditions
54ACT11280
74ACT11280
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level output current
IOL
Dt /Dv
Low-level output current
TA
Operating free-air temperature
High-level input voltage
2
V
2
V
0.8
Input transition rise or fall rate
UNIT
0.8
V
VCC
VCC
V
−24
−24
mA
24
24
mA
VCC
VCC
0
0
V
0
10
0
10
ns/ V
− 55
125
− 40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = − 50 mA
A
VOH
IOH = − 24 mA
IOH = − 50 mA{
IOH = − 75 mA{
54ACT11280
74ACT11280
MIN
4.5 V
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
4.5 V
3.94
3.7
3.8
5.5 V
4.94
4.7
4.8
5.5 V
MIN
MAX
IOL = 24 mA
IOL = 50 mA{
IOL = 75 mA{
MIN
MAX
V
3.85
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
5.5 V
VI = VCC or GND
VI = VCC or GND,
DICC}
One input at 3.4 V,
Other inputs at GND or VCC
IO = 0
V
1.60
5.5 V
II
ICC
UNIT
3.85
5.5 V
IOL = 50 mA
A
VOL
TA = 25°C
TYP
MAX
VCC
1.65
5.5 V
± 0.1
±1
±1
mA
5.5 V
8
160
80
mA
5.5 V
0.9
1
1
mA
Ci
VI = VCC or GND
5V
3.5
† Not more than one output should be tested at a time and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
pF
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
Any input
S EVEN
tPLH
tPHL
Any input
S ODD
MIN
•
TA = 25°C
TYP
MAX
74ACT11280
MIN
MAX
MIN
MAX
1.5
7.3
10.8
1.5
13.1
1.5
12.2
1.5
8.8
12.5
1.5
15.6
1.5
14.3
1.5
7.3
10.8
1.5
12.9
1.5
12.1
1.5
8.6
12.4
1.5
15.7
1.5
14.3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
•
54ACT11280
UNIT
ns
ns
2−3
SCAS046A − D3148, AUGUST 1988 − REVISED APRIL 1993
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
f = 1 MHz
TYP
UNIT
56
pF
PARAMETER MEASUREMENT INFORMATION
3V
Input
(see Note B)
1.5 V
1.5 V
0V
tPHL
tPLH
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
In-Phase
Output
50% VCC
tPLH
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
LOAD CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
2−4
•
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