TI LMV842QMA

LMV841, LMV842, LMV844
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SNOSAT1G – OCTOBER 2006 – REVISED FEBRUARY 2013
LMV841/LMV841Q/LMV842/LMV842Q/LMV844/LMV844Q CMOS Input, RRIO, Wide Supply
Range Operational Amplifiers
Check for Samples: LMV841, LMV842, LMV844
FEATURES
APPLICATIONS
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Unless otherwise noted, typical values at TA =
25°C, V+ = 5V.
Space saving 5-Pin SC70 package
Supply voltage range 2.7V to 12V
Guaranteed at 3.3V, 5V and ±5V
Low supply current 1mA per channel
Unity gain bandwidth 4.5MHz
Open loop gain 133dB
Input offset voltage 500μV max
Input bias current 0.3pA
CMRR 112dB
Input voltage noise 20nV/√Hz
Temperature range −40°C to 125°C
Rail-to-Rail input
Rail-to-Rail output
The LMV841Q, LMV842Q, and LMV844Q are
AEC-Q100 grade 1 qualified and are
manufactured on automotive grade flow.
High impedance sensor interface
Battery powered instrumentation
High gain amplifiers
DAC buffer
Instrumentation amplifiers
Active filters
DESCRIPTION
The LMV841/LMV842/LMV844 are low-voltage and
low-power operational amplifiers that operate with
supply voltages ranging from 2.7V to 12V and have
rail-to-rail input and output capability. Their low offset
voltage, low supply current, and MOS inputs make
them ideal for sensor interface and battery-powered
applications.
The single LMV841 is offered in the space-saving 5Pin SC70 package, the dual LMV842 in the 8-Pin
VSSOP and 8-Pin SOIC packages, and the quad
LMV844 in the 14-Pin TSSOP and 14-Pin SOIC
packages. These small packages are ideal solutions
for area-constrained PC boards and portable
electronics.
The LMV841Q, LMV842Q, and LMV844Q incorporate
enhanced manufacturing and support processes for
the automotive market , including defect detection
methodologies.
Reliability qualification is compliant with the
requirements and temperature grades defined in the
AEC-Q100 standard.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LMV841, LMV842, LMV844
SNOSAT1G – OCTOBER 2006 – REVISED FEBRUARY 2013
www.ti.com
Typical Applications
-
VIN
+
+
Active Band-Pass Filter
SENSOR
RS
+
+
-
VS
RS
+
-
LOAD
High Impedance Sensor Interface
CMOS Input Feature
High Side Current Sensing
Rail-to-Rail Input and Output Feature
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
ESD Tolerance
(1) (2)
(3)
Human Body Model
2 kV
Machine Model
200V
VIN Differential
±300 mV
+
−
Supply Voltage (V – V )
13.2V
V++0.3V, V− −0.3V
Voltage at Input/Output Pins
Input Current
10 mA
−65°C to +150°C
Storage Temperature Range
Junction Temperature
(4)
+150°C
Soldering Information
(1)
(2)
(3)
(4)
2
Infrared or Convection (20 sec)
235°C
Wave Soldering Lead Temp. (10 sec)
260°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics Tables.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for
availability and specifications.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA) / θJA . All numbers apply for packages soldered directly onto a PC board.
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SNOSAT1G – OCTOBER 2006 – REVISED FEBRUARY 2013
Operating Ratings
Temperature Range
(1)
(2)
−40°C to +125°C
Supply Voltage (V – V−)
+
2.7V to 12V
Package Thermal Resistance [θJA (2)]
5-Pin SC70
334 °C/W
8-Pin VSSOP
205 °C/W
8-Pin SOIC
126 °C/W
14-Pin TSSOP
110 °C/W
14-Pin SOIC
(1)
(2)
93 °C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics Tables.
The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA) / θJA . All numbers apply for packages soldered directly onto a PC board.
3.3V Electrical Characteristics
(1)
Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 3.3V, V− = 0V, VCM = V+/2, and RL > 10MΩ to V+/2.
Boldface limits apply at the temperature extremes.
Typ
Max
(2)
Units
±50
±500
±800
μV
0.5
±5
μV/°C
Input Bias Current
0.3
10
300
pA
Input Offset Current
40
Symbol
Parameter
VOS
Input Offset Voltage
TCVOS
Input Offset Voltage Drift
IB
Conditions
Min
(2)
(4)
(4) (5)
IOS
Common Mode Rejection Ratio LMV841
CMRR
(3)
0V ≤ VCM ≤ 3.3V
84
80
112
Common Mode Rejection Ratio LMV842
0V ≤ VCM ≤ 3.3V
and LMV844
77
75
106
86
82
108
PSRR
Power Supply Rejection Ratio
2.7V ≤ V+ ≤ 12V, VO = V+/2
CMVR
Input Common-Mode Voltage Range
CMRR ≥ 50 dB
–0.1
RL = 2 kΩ
VO = 0.3V to 3.0V
100
96
123
RL = 10 kΩ
VO = 0.2V to 3.1V
100
96
131
AVOL
Large Signal Voltage Gain
Output Swing High,
(measured from V+)
(1)
(2)
(3)
(4)
(5)
dB
dB
dB
3.4
V
dB
dB
RL = 2 kΩ to V+/2
52
80
120
mV
RL = 10 kΩ to V+/2
28
50
70
mV
RL = 2 kΩ to V+/2
65
100
120
mV
RL = 10 kΩ to V+/2
33
65
75
mV
VO
Output Swing Low,
(measured from V−)
fA
Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on
shipped production material.
This parameter is guaranteed by design and/or characterization and is not tested in production.
Positive current corresponds to current flowing into the device.
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMV841 LMV842 LMV844
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3.3V Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 3.3V, V− = 0V, VCM = V+/2, and RL > 10MΩ to V+/2.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Typ
20
15
32
20
15
27
(2)
Sourcing VO = V+/2
VIN = 100 mV
Output Short Circuit Current
IO
Min
(6) (7)
+
Sinking VO = V /2
VIN = −100 mV
(3)
0.93
(2)
Units
mA
mA
1.5
2
IS
Supply Current
SR
Slew Rate
GBW
Φm
en
Input-Referred Voltage Noise
f = 1 kHz
20
ROUT
Open Loop Output Impedance
f = 3 MHz
70
Ω
THD+N
Total Harmonic Distortion + Noise
f = 1 kHz , AV = 1
RL = 10 kΩ
0.005
%
CIN
Input Capacitance
7
pF
(6)
(7)
(8)
Per Channel
Max
AV = +1, VO = 2.3 VPP
10% to 90%
(8)
mA
2.5
V/μs
Gain Bandwidth Product
4.5
MHz
Phase Margin
67
Deg
nV/
The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA) / θJA . All numbers apply for packages soldered directly onto a PC board.
Short circuit test is a momentary test.
Number specified is the slower of positive and negative slew rates.
5V Electrical Characteristics
(1)
Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, and RL > 10MΩ to V+/2.
Boldface limits apply at the temperature extremes.
Symbol
VOS
Parameter
Conditions
Min
(2)
Input Offset Voltage
TCVOS
Input Offset Voltage Drift
(4)
Input Bias Current
IB
(4) (5)
IOS
Input Offset Current
Max
(2)
Units
±50
±500
±800
μV
0.35
±5
μV/°C
0.3
10
300
pA
(3)
40
0V ≤ VCM ≤ 5V
86
80
112
Common Mode Rejection Ratio
LMV842 and LMV844
0V ≤ VCM ≤ 5V
81
79
106
PSRR
Power Supply Rejection Ratio
2.7V ≤ V+ ≤ 12V, VO = V+/2
86
82
108
CMVR
Input Common-Mode Voltage Range
CMRR ≥ 50 dB
−0.2
RL = 2 kΩ
VO = 0.3V to 4.7V
100
96
125
RL = 10 kΩ
VO = 0.2V to 4.8V
100
96
133
CMRR
AVOL
(1)
(2)
(3)
(4)
(5)
4
Common Mode Rejection Ratio
LMV841
Typ
Large Signal Voltage Gain
fA
dB
dB
dB
5.2
V
dB
dB
Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on
shipped production material.
This parameter is guaranteed by design and/or characterization and is not tested in production.
Positive current corresponds to current flowing into the device.
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMV841 LMV842 LMV844
LMV841, LMV842, LMV844
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SNOSAT1G – OCTOBER 2006 – REVISED FEBRUARY 2013
5V Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, and RL > 10MΩ to V+/2.
Boldface limits apply at the temperature extremes.
Symbol
Typ
Max
(2)
Units
RL = 2 kΩ to V+/2
68
100
120
mV
RL = 10 kΩ to V+/2
32
50
70
mV
RL = 2 kΩ to V+/2
78
120
140
mV
RL = 10 kΩ to V+/2
38
70
80
mV
Parameter
Conditions
Output Swing High,
(measured from V+)
Min
(2)
VO
Output Swing Low,
(measured from V-)
Sourcing VO = V+/2
VIN = 100 mV
Output Short Circuit Current
IO
(6) (7)
+
Sinking VO = V /2
VIN = −100 mV
(3)
20
15
33
20
15
28
0.96
mA
1.5
2
IS
Supply Current
SR
Slew Rate
GBW
Φm
en
Input-Referred Voltage Noise
f = 1 kHz
20
ROUT
Open Loop Output Impedance
f = 3 MHz
70
Ω
THD+N
Total Harmonic Distortion + Noise
f = 1 kHz , AV = 1
RL = 10 kΩ
0.003
%
CIN
Input Capacitance
6
pF
(6)
(7)
(8)
Per Channel
mA
AV = +1, VO = 4 VPP
10% to 90%
(8)
mA
2.5
V/μs
Gain Bandwidth Product
4.5
MHz
Phase Margin
67
Deg
nV/
The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA) / θJA . All numbers apply for packages soldered directly onto a PC board.
Short circuit test is a momentary test.
Number specified is the slower of positive and negative slew rates.
±5V Electrical Characteristics
(1)
Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 5V, V− = –5V, VCM = 0V, and RL > 10MΩ to VCM.
Boldface limits apply at the temperature extremes.
Symbol
VOS
Input Offset Voltage Drift
(4)
Input Offset Current
CMRR
(4)
(5)
(2)
(4) (5)
IOS
(3)
Min
Input Bias Current
IB
(2)
Conditions
Input Offset Voltage
TCVOS
(1)
Parameter
Common Mode Rejection Ratio
LMV841
Common Mode Rejection Ratio
LMV842 and LMV844
Typ
Max
(2)
Units
±50
±500
±800
μV
0.25
±5
μV/°C
0.3
10
300
pA
(3)
40
–5V ≤ VCM ≤ 5V
86
80
112
–5V ≤ VCM ≤ 5V
86
80
106
fA
dB
dB
Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on
shipped production material.
This parameter is guaranteed by design and/or characterization and is not tested in production.
Positive current corresponds to current flowing into the device.
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMV841 LMV842 LMV844
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LMV841, LMV842, LMV844
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±5V Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 5V, V− = –5V, VCM = 0V, and RL > 10MΩ to VCM.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
86
82
108
(2)
(3)
PSRR
Power Supply Rejection Ratio
2.7V ≤ V+ ≤ 12V, VO = 0V
CMVR
Input Common-Mode Voltage Range
CMRR ≥ 50 dB
−5.2
RL = 2kΩ
VO = −4.7V to 4.7V
100
96
126
RL = 10kΩ
VO = −4.8V to 4.8V
100
96
136
AVOL
Large Signal Voltage Gain
RL = 2kΩ to 0V
Output Swing High,
(measured from V+)
RL = 10kΩ to 0V
VO
RL = 2kΩ to 0V
Output Swing Low,
(measured from V−)
RL = 10kΩ to 0V
Output Short Circuit Current
IO
(6) (7)
Units
(2)
dB
5.2
V
dB
dB
95
130
155
mV
44
75
95
mV
105
160
200
mV
52
80
100
mV
Sourcing VO = 0V
VIN = 100 mV
20
15
37
Sinking VO = 0V
VIN = −100 mV
20
15
29
1.03
mA
mA
1.7
2
IS
Supply Current
SR
Slew Rate
GBW
Φm
en
Input-Referred Voltage Noise
f = 1kHz
20
ROUT
Open Loop Output Impedance
f = 3MHz
70
Ω
THD+N
Total Harmonic Distortion + Noise
f = 1kHz , AV = 1
RL = 10kΩ
0.006
%
CIN
Input Capacitance
3
pF
(6)
(7)
(8)
6
Per Channel
Max
AV = +1, VO = 9VPP
10% to 90%
(8)
mA
2.5
V/μs
Gain Bandwidth Product
4.5
MHz
Phase Margin
67
Deg
nV/
The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA) / θJA . All numbers apply for packages soldered directly onto a PC board.
Short circuit test is a momentary test.
Number specified is the slower of positive and negative slew rates.
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMV841 LMV842 LMV844
LMV841, LMV842, LMV844
www.ti.com
SNOSAT1G – OCTOBER 2006 – REVISED FEBRUARY 2013
CONNECTION DIAGRAMS
Figure 1. 5-Pin SC70 Top View
Figure 2. 8-Pin SOIC and VSSOP Top View
Figure 3. 14-Pin SOIC and TSSOP Top View
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMV841 LMV842 LMV844
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TYPICAL PERFORMANCE CHARACTERISTICS
At TA = 25°C, RL = 10kΩ, VS = 5V. Unless otherwise specified.
VOS
vs.
VCM Over Temperature at 3.3V
VOS
vs.
VCM Over Temperature at 5.0V
200
200
VS = 3.3V
150
100
100
85°C
VOS (PV)
50
VOS (PV)
VS = 5.0V
150
125°C
0
-50
-100
50
125°C
0
85°C
-50
25°C
-100
25°C
-150
-150
-40°C
-200
-1
0
1
2
3
-200
-1
4
-40°C
0
1
2
3
4
VCM (V)
VCM (V)
Figure 4.
Figure 5.
VOS vs. VCM Over Temperature at ±5.0V
VOS
vs.
Supply Voltage
200
5
6
12
14
200
VS = ±5V
150
150
125°C
100
85°C
50
0
VOS (PV)
VOS (PV)
100
25°C
-50
125°C
50
0
85°C
-50
-40°C
-100
25°C
-100
-150
-150
-200
-6
-200
2
-40°C
-4
-2
0
2
4
6
4
VCM (V)
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8
10
VSUPPLY (V)
Figure 6.
8
6
Figure 7.
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SNOSAT1G – OCTOBER 2006 – REVISED FEBRUARY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
At TA = 25°C, RL = 10kΩ, VS = 5V. Unless otherwise specified.
VOS
vs.
Temperature
DC Gain
vs.
VOUT
140
200
RL = 10 k:
OPEN LOOP GAIN (dB)
150
VOS (PV)
100
50
0
3.3V
-50
±5V
-100
5V
130
RL = 2 k:
120
110
RL = 600Ö
100
-150
-200
-50
-25
0
25
50
75
100
100
200
300
400
500
TEMPERATURE (°C)
OUTPUT SWING FROM RAIL (mV)
Figure 8.
Figure 9.
Input Bias Current
vs.
VCM
Input Bias Current
vs.
VCM
0.20
20
TA = 25°C
0.15
15
0.10
10
0.05
5
IBIAS (pA)
IBIAS (pA)
90
0
125
0
-0.05
TA = 85°C
0
5.0V
-5
5V
-0.10
-10
±5V
-0.15
-0.20
-5
-4
-3
-2
-1
0
1
2
±5V
-15
3.3V
3
4
5
-20
-5
3.3V
-4
-3
VCM (V)
-2
-1
0
1
2
3
4
5
VCM (V)
Figure 10.
Figure 11.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
At TA = 25°C, RL = 10kΩ, VS = 5V. Unless otherwise specified.
Input Bias Current
vs.
VCM
Supply Current per Channel
vs.
Supply Voltage
200
1.4
TA = 125°C
125°C
150
SUPPLY CURRENT (mA)
1.3
IBIAS (pA)
100
50
0
5.0V
-50
-100
±5V
85°C
1.1
25°C
1.0
0.9
3.3V
-150
1.2
-40°C
-200
-5
-4
-3
-2
-1
0
1
2
3
4
0.8
2
5
4
6
8
10
12
VCM (V)
SUPPLY VOLTAGE (V)
Figure 12.
Figure 13.
Sinking Current
vs.
Supply Voltage
Sourcing Current
vs.
Supply Voltage
40
14
45
125°C
85°C
-40°C
30
25
20
2
10
40
25°C
ISOURCE (mA)
ISINK (mA)
35
4
6
85°C
125°C
8
10
35
25°C
-40°C
30
12
25
2
4
6
8
10
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 14.
Figure 15.
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SNOSAT1G – OCTOBER 2006 – REVISED FEBRUARY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
At TA = 25°C, RL = 10kΩ, VS = 5V. Unless otherwise specified.
Output Swing High
vs.
Supply Voltage
RL = 2kΩ
135
Output Swing High
vs.
Supply Voltage
RL = 10kΩ
65
RL = 2 k:
60
125°C
VOUT FROM RAIL HIGH (mV)
VOUT FROM RAIL HIGH (mV)
125
115
85°C
105
95
85
75
25°C
65
55
-40°C
55
125°C
50
85°C
45
40
35
25°C
30
-40°C
25
20
45
35
2
RL = 10 k:
4
6
8
10
12
15
2
14
4
Output Swing Low
vs.
Supply Voltage
RL = 2kΩ
Output Swing Low
vs.
Supply Voltage
RL = 10kΩ
14
75
70
125°C
VOUT FROM RAIL LOW (mV)
VOUT FROM RAIL LOW (mV)
12
Figure 17.
RL = 2 k:
130
85°C
120
110
100
90
25°C
80
70
-40°C
60
4
10
Figure 16.
140
50
2
8
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
150
6
6
8
RL = 10 k:
125°C
65
60
85°C
55
50
45
25°C
40
-40°C
35
30
10
12
14
25
2
4
SUPPLY VOLTAGE (V)
Figure 18.
6
8
10
12
14
SUPPLY VOLTAGE (V)
Figure 19.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
At TA = 25°C, RL = 10kΩ, VS = 5V. Unless otherwise specified.
Output Voltage Swing
vs.
Load Current
SINK
Open Loop Frequency Response Over Temperature
60
85°C
125°C
130
GAIN
PHASE
90
40
-40°C
VS = 3.3V, 5.0V, +/-5V
25°C
-40°C
125°C
-40°C
20
10
0
125°C 85°C
125°C
SOURCE
0
5
10
15
20
ILOAD (mA)
25
CL = 20 pF
-20
10k
100k
30
-30
10M
1M
FREQUENCY (Hz)
Figure 20.
Figure 21.
Open Loop Frequency Response Over Load Conditions
Phase Margin
vs.
CL
60
50
PHASE (°)
25°C
GAIN (dB)
VOUT FROM RAIL (V)
-40°C
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
130
GAIN
80
PHASE
70
3.3V
VS=10V
CL=20 pF 90
40
60
50
10
0
100k
50
40
30
±5V
20
10
VS = 3.3V, 5.0V, 10V
CL = 20 pF, 50 pF, 100 pF
-20
10k
PHASE(°)
20
PHASE (°)
GAIN (dB)
5.0V
VS = 3.3V
CL = 100 pF
-30
10M
1M
0
1
10
Figure 22.
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1000
CLOAD (pF)
FREQUENCY (Hz)
12
100
Figure 23.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
At TA = 25°C, RL = 10kΩ, VS = 5V. Unless otherwise specified.
PSRR
vs.
Frequency
CMRR
vs.
Frequency
120
3.3V
110
5.0V
100
3.3V
±5V
PSRR (dB)
+PSRR
3.3V
5.0V
±5V
60
40
20
3.3V: VCM = 1V
CMRR (dB)
5.0V
80
90
±5V
70
50
5.0V: VCM = 2.5V
-PSRR
±5V: VCM = 0V
0
100
1k
3.3V : VCM = 1V
5.0V : VCM = 2.5V
±5V : VCM = 0V
10k
100k
1M
30
100
FREQUENCY (Hz)
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 24.
Figure 25.
Channel Separation
vs.
Frequency
Large Signal Step Response with Gain = 1
160
140
500 mV/DIV
CHANNEL SEPARATION (dB)
180
120
100
f = 250 kHz
AV = +1
VIN = 2 VPP
CL = 20 pF
80
VS = 3.3V, 5.0V, ±5V
60
100
1k
10k
100k
1M
400 ns/DIV
FREQUENCY (Hz)
Figure 26.
Figure 27.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
At TA = 25°C, RL = 10kΩ, VS = 5V. Unless otherwise specified.
Small Signal Step Response with Gain = 1
50 mV/DIV
200 mV/DIV
Large Signal Step Response with Gain = 10
f = 250 kHz
AV = +1
f = 250 kHz
AV = +10
VIN = 100 mVPP
CL = 20 pF
VIN = 200 mVPP
CL = 20 pF
400 ns/DIV
400 ns/DIV
Figure 28.
Figure 29.
Small Signal Step Response with Gain = 10
Slew Rate
vs
Supply Voltage
20 mV/DIV
SLEWRATE (V/és)
3.0
f = 250 kHz
AV = +10
VIN = 10 mVPP
CL = 20 pF
400 ns/DIV
FALLING EDGE
2.5
2.0
RISING EDGE
1.5 AV = +1
VIN = 2 VPP
1.0
RL = 10 kÖ
CL = 20 pF
2
4
Figure 30.
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6
8
10
SUPPLY VOLTAGE (V)
12
Figure 31.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
At TA = 25°C, RL = 10kΩ, VS = 5V. Unless otherwise specified.
Overshoot
vs.
CL
Input Voltage Noise
vs.
Frequency
50
100
f = 250 kHz
AV = +1
VIN = 200 mVPP
NOISE (nV/íHz)
OVERSHOOT (%)
40
30
±5V
20
5.0V
50
3.3V
5.0V
20
10
3.3V
±5V
10
0
100
10
10
1000
100
1k
CLOAD (pF)
Figure 32.
Figure 33.
THD+N
vs.
Frequency
THD+N
vs.
VOUT
1 VS = 5V
RL = 10 k:
AV = +10
AV = +10
THD + N (%)
THD + N (%)
1
VOUT = 4.5 VPP
0.01
0.1
0.01
0.001
100
AV = +1
VS = 5V
RL = 10 k:
0.001 CL = 20 pF
f = 1 kHz
AV = +1
10
100k
10
CL = 50 pF
0.1
10k
FREQUENCY (Hz)
1k
10k
100k
0.001
FREQUENCY (Hz)
0.01
0.1
1
10
VOUT (V)
Figure 34.
Figure 35.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
At TA = 25°C, RL = 10kΩ, VS = 5V. Unless otherwise specified.
Closed Loop Output Impedance
vs.
Frequency
100
10
ROUT (:)
100x
1
10x
0.1
1x
0.01
0.001
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 36.
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APPLICATION INFORMATION
INTRODUCTION
The LMV841/LMV842/LMV844 are operational amplifiers with near-precision specifications: low noise, low
temperature drift, low offset, and rail-to-rail input and output. Possible application areas include instrumentation,
medical, test equipment, audio, and automotive applications.
Its low supply current of 1mA per amplifier, temperature range of −40°C to 125°C, 12V supply with CMOS input,
and the small SC70 package for the LMV841 make the LMV841/LMV842/LMV844 a unique op amp family and a
perfect choice for portable electronics.
INPUT PROTECTION
The LMV841/LMV842/LMV844 have a set of anti-parallel diodes D1 and D2 between the input pins, as shown in
Figure 37. These diodes are present to protect the input stage of the amplifier. At the same time, they limit the
amount of differential input voltage that is allowed on the input pins.
A differential signal larger than one diode voltage drop can damage the diodes. The differential signal between
the inputs needs to be limited to ±300mV or the input current needs to be limited to ±10mA.
Note that when the op amp is slewing, a differential input voltage exists that forward biases the protection diodes.
This may result in current being drawn from the signal source. While this current is already limited by the internal
resistors R1 and R2 (both 130Ω), a resistor of 1kΩ can be placed in the feedback path, or a 500Ω resistor can be
placed in series with the input signal for further limitation.
V
+
+
V
ESD
IN
IN
ESD
V
+
R1
D1 D2
+
V
ESD
+
-
VOUT
R2
ESD
-
V
-
V
Figure 37. Protection Diodes between the Input Pins
INPUT STAGE
The input stage of this amplifier consists of both a PMOS and an NMOS input pair to achieve a rail-to-rail input
range. For input voltages close to the negative rail, only the PMOS pair is active. Close to the positive rail, only
the NMOS pair is active. In a transition region that extends from approximately 2V below V+ to 1V below V+, both
pairs are active, and one pair gradually takes over from the other. In this transition region, the input-referred
offset voltage changes from the offset voltage associated with the PMOS pair to that of the NMOS pair. The input
pairs are trimmed independently to guarantee an input offset voltage of less then 0.5 mV at room temperature
over the complete rail-to-rail input range. This also significantly improves the CMRR of the amplifier in the
transition region. Note that the CMRR and PSRR limits in the tables are large-signal numbers that express the
maximum variation of the amplifier's input offset over the full common-mode voltage and supply voltage range,
respectively. When the amplifier's common-mode input voltage is within the transition region, the small signal
CMRR and PSRR may be slightly lower than the large signal limits.
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CAPACITIVE LOAD
The LMV841/LMV842/LMV844 can be connected as non-inverting unity gain amplifiers. This configuration is the
most sensitive to capacitive loading. The combination of a capacitive load placed on the output of an amplifier
along with the amplifier’s output impedance creates a phase lag, which reduces the phase margin of the
amplifier. If the phase margin is significantly reduced, the response will be under-damped which causes peaking
in the transfer and, when there is too much peaking, the op amp might start oscillating.
The LMV841/LMV842/LMV844 can directly drive capacitive loads up to 100pF without any stability issues. In
order to drive heavier capacitive loads, an isolation resistor, RISO, should be used, as shown in Figure 38. By
using this isolation resistor, the capacitive load is isolated from the amplifier’s output, and hence, the pole caused
by CL is no longer in the feedback loop. The larger the value of RISO, the more stable the output voltage will be. If
values of RISO are sufficiently large, the feedback loop will be stable, independent of the value of CL. However,
larger values of RISO result in reduced output swing and reduced output current drive.
-
RISO
V OUT
V IN
+
CL
Figure 38. Isolating Capacitive Load
DECOUPLING AND LAYOUT
For decoupling the supply lines it is suggested that 10nF capacitors be placed as close as possible to the op
amp.
For single supply, place a capacitor between V+ and V−. For dual supplies, place one capacitor between V+ and
the board ground, and the second capacitor between ground and V−.
OP AMP CIRCUIT NOISE
The LMV841/LMV842/LMV844 have good noise specifications, and will frequently be used in low-noise
applications. Therefore it is important to determine the noise of the total circuit. Besides the input referred noise
of the op amp, the feedback resistors may have an important contribution to the total noise.
For applications with a voltage input configuration it is, in general, beneficial to keep the resistor values low. In
these configurations high resistor values mean high noise levels. However, using low resistor values will increase
the power consumption of the application. This is not always acceptable for portable applications, so there is a
trade-off between noise level and power consumption.
Besides the noise contribution of the signal source, three types of noise need to be taken into account for
calculating the noise performance of an op amp circuit:
• Input referred voltage noise of the op amp
• Input referred current noise of the op amp
• Noise sources of the resistors in the feedback network, configuring the op amp
To calculate the noise voltage at the output of the op amp, the first step is to determine a total equivalent noise
source. This requires the transformation of all noise sources to the same reference node. A convenient choice for
this node is the input of the op amp circuit. The next step is to add all the noise sources. The final step is to
multiply the total equivalent input voltage noise with the gain of the op amp configuration.
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The input referred voltage noise of the op amp is already located at the input, we can use the input referred
voltage noise without further transferring. The input referred current noise needs to be converted to an input
referred voltage noise. The current noise is negligibly small, as long as the equivalent resistance is not
unrealistically large, so we can leave the current noise out for these examples. That leaves us with the noise
sources of the resistors, being the thermal noise voltage. The influence of the resistors on the total noise can be
seen in the following examples, one with high resistor values and one with low resistor values. Both examples
describe an op amp configuration with a gain of 101 which will give the circuit a bandwidth of 44.5kHz. The op
amp noise is the same for both cases, i.e. an input referred noise voltage of 20nV/
and a negligibly small input
referred noise current.
+
en in
RF
RG
Figure 39. Noise Circuit
To calculate the noise of the resistors in the feedback network, the equivalent input referred noise resistance is
needed. For the example in Figure 39, this equivalent resistance Req can be calculated using the following
equation:
Req =
R F × RG
RF + RG
(1)
The voltage noise of the equivalent resistance can be calculated using the following equation:
enr = 4kTReq
(2)
where:
enr = thermal noise voltage of the equivalent resistor
Req (V/
)
k = Boltzmann constant (1.38 x 10–23 J/K)
T = absolute temperature (K)
Req = resistance (Ω)
The total equivalent input voltage noise is given by the equation:
en in =
2
env + enr
2
(3)
where:
en in = total input equivalent voltage noise of the circuit
env = input voltage noise of the op amp
The final step is multiplying the total input voltage noise by the noise gain, which is in this case the gain of the op
amp configuration:
en out = en in × Anoise
(4)
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The equivalent resistance for the first example with a resistor RF of 10MΩ and a resistor RG of 100kΩ at 25°C
(298 K) equals:
Req =
R F × RG
RF + R G
=
10 M: × 100 k:
= 99 k:
10 M: + 100 k:
(5)
Now the noise of the resistors can be calculated, yielding:
enr =
4kTReq
=
4 × 1.38 × 10
-23
J/K × 298K × 99 k:
= 40 nV/ Hz
(6)
The total noise at the input of the op amp is:
en in =
=
2
env + enr
( 20 nV/
2
Hz
)2 + ( 40 nV/
Hz
)2
= 45 nV/ Hz
(7)
For the first example, this input noise will, multiplied with the noise gain, give a total output noise of:
en out = en in × Anoise
= 45 nV/ Hz × 101 = 4.5 PV/ Hz
(8)
In the second example, with a resistor RF of 10kΩ and a resistor RG of 100Ω at 25°C (298K), the equivalent
resistance equals:
Req =
R F × RG
RF + R G
10 k: × 100:
10 k: + 100:
=
= 99:
(9)
The resistor noise for the second example is:
enr =
4kTReq
=
4 × 1.38 × 10
-23
J/K × 298K × 99:
= 1 nV/ Hz
(10)
The total noise at the input of the op amp is:
en in =
=
env + enr
2
2
( 20 nV/
Hz
)2 + (1 nV/
Hz
)2
= 20 nV/ Hz
(11)
For the second example the input noise will, multiplied with the noise gain, give an output noise of
en out = en in × Anoise
= 20 nV/ Hz × 101 = 2 PV/ Hz
(12)
In the first example the noise is dominated by the resistor noise due to the very high resistor values, in the
second example the very low resistor values add only a negligible contribution to the noise and now the
dominating factor is the op amp itself. When selecting the resistor values, it is important to choose values that
don't add extra noise to the application. Choosing values above 100kΩ may increase the noise too much. Low
values will keep the noise within acceptable levels; choosing very low values however, will not make the noise
even lower, but will increase the current of the circuit.
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ACTIVE FILTER
The rail-to-rail input and output of the LMV841/LMV842/LMV844 and the wide supply voltage range make these
amplifiers ideal to use in numerous applications. One of the typical applications is an active filter as shown in
Figure 40. This example is a band-pass filter, for which the pass band is widened. This is achieved by cascading
two band-pass filters, with slightly different center frequencies.
C
C
R2
R2
R1
C
-
R1
C
-
R3
+
R3
+
Figure 40. Active Filter
The center frequency of the separate band-pass filters can be calculated by:
R 1 + R3
1
fmid =
2SC í R1 R2 R3
(13)
In this example a filter was designed with its pass band at 10kHz. The two separate band-pass filters are
designed to have a center frequency of approximately 10% from the frequency of the total filter:
C = 33nF R1 = 2KΩ R2 = 6.2KΩ R3 = 45Ω
(14)
This will give for filter A:
fmid =
1
S x 33 nF
2 k: + 6.2 k:
= 9.2 kHz
2 k: x 6.2 k: x 45:
(15)
and for filter B with C = 27nF:
fmid =
1
S x 27 nF
2 k: + 6.2 k:
= 11.2 kHz
2 k: x 6.2 k: x 45:
(16)
Bandwidth can be calculated by:
1
B=
SR2C
(17)
For filter A this will give:
1
B=
= 1.6 kHz
S x 6.2 k: x 33 nF
(18)
and for filter B:
B=
1
= 1.9 kHz
S x 6.2 k: x 27 nF
(19)
The response of the two filters and the combined filter is shown in Figure 41.
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10
FILTER A
FILTER B
GAIN (dB)
0
-10
-20
-30
COMBINED
FILTER
-40
1k
10k
100k
FREQUENCY (Hz)
Figure 41. Active Filter Curve
The responses of filter A and filter B are shown as the thin lines in Figure 41; the response of the combined filter
is shown as the thick line. Shifting the center frequencies of the separate filters farther apart, will result in a wider
band; however, positioning the center frequencies too far apart will result in a less flat gain within the band. For
wider bands more band-pass filters can be cascaded.
Tip: Use the WEBENCH internet tools at www.ti.com for your filter application.
HIGH-SIDE CURRENT SENSING
The rail-to-rail input and the low VOS features make the LMV841/LMV842/LMV844 ideal op amps for high-side
current sensing applications.
To measure a current, a sense resistor is placed in series with the load, as shown in Figure 42. The current
flowing through this sense resistor will result in a voltage drop, that is amplified by the op amp.
Suppose it is necessary to measure a current between 0A and 2A using a sense resistor of 100mΩ, and convert
it to an output voltage of 0 to 5V. A current of 2A flowing through the load and the sense resistor will result in a
voltage of 200mV across the sense resistor. The op amp will amplify this 200mV to fit the current range to the
output voltage range. Use the formula:
VOUT = RF/RG * VSENSE
(20)
to calculate the gain needed. For a load current of 2A and an output voltage of 5V the gain would be VOUT /
VSENSE = 25.
If the feedback resistor, RF, is 100kΩ, then the value for RG will be 4kΩ. The tolerance of the resistors has to be
low to obtain a good common-mode rejection.
V
RF
+
RG
RS
+
RG
RF
LOAD
Z
Figure 42. High-Side Current Sensing
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HIGH IMPEDANCE SENSOR INTERFACE
With CMOS inputs, the LMV841/LMV842/LMV844 are particularly suited to be used as high impedance sensor
interfaces.
Many sensors have high source impedances that may range up to 10MΩ. The input bias current of an amplifier
will load the output of the sensor, and thus cause a voltage drop across the source resistance, as shown in
Figure 43. When an op amp is selected with a relatively high input bias current, this error may be unacceptable.
The low input current of the LMV841/LMV842/LMV844 significantly reduces such errors. The following examples
show the difference between a standard op amp input and the CMOS input of the LMV841/LMV842/LMV844.
The voltage at the input of the op amp can be calculated with
VIN+ = VS - IB * RS
(21)
For a standard op amp the input bias Ib can be 10nA. When the sensor generates a signal of 1V (VS) and the
sensors impedance is 10MΩ (RS), the signal at the op amp input will be
VIN = 1V - 10nA * 10MΩ = 1V - 0.1V = 0.9V
(22)
For the CMOS input of the LMV841/LMV842/LMV844, which has an input bias current of only 0.3pA, this would
give
VIN = 1V – 0.3pA * 10MΩ = 1V - 3μV = 0.999997V
(23)
The conclusion is that a standard op amp, with its high input bias current input, is not a good choice for use in
impedance sensor applications. The LMV841/LMV842/LMV844, in contrast, are much more suitable due to the
low input bias current. The error is negligibly small; therefore, the LMV841/LMV842/LMV844 are a must for use
with high impedance sensors.
SENSOR
RS
+
-
VS
IB
V
VIN+
+
+
-
V
Figure 43. High Impedance Sensor Interface
THERMOCOUPLE AMPLIFIER
The following is a typical example for a thermocouple amplifier application using an LMV841, LMV842, or
LMV844. A thermocouple senses a temperature and converts it into a voltage. This signal is then amplified by
the LMV841, LMV842, or LMV844. An ADC can then convert the amplified signal to a digital signal. For further
processing the digital signal can be processed by a microprocessor, and can be used to display or log the
temperature, or the temperature data can be used in a fabrication process.
Characteristics of a Thermocouple
A thermocouple is a junction of two different metals. These metals produce a small voltage that increases with
temperature.
The thermocouple used in this application is a K-type thermocouple. A K-type thermocouple is a junction
between Nickel-Chromium and Nickel-Aluminum. This is one of the most commonly used thermocouples. There
are several reasons for using the K-type thermocouple. These include temperature range, the linearity, the
sensitivity, and the cost.
A K-type thermocouple has a wide temperature range. The range of this thermocouple is from approximately
−200°C to approximately 1200°C, as can be seen in Figure 44. This covers the generally used temperature
ranges.
Over the main part of the range the behavior is linear. This is important for converting the analog signal to a
digital signal.
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The K-type thermocouple has good sensitivity when compared to many other types; the sensitivity is 41 uV/°C.
Lower sensitivity requires more gain and makes the application more sensitive to noise.
In addition, a K-type thermocouple is not expensive, many other thermocouples consist of more expensive
materials or are more difficult to produce.
THERMOCOUPLE VOLTAGE (mV)
50
40
30
20
10
0
-10
-200
0
200
400
600
800 1000 1200
TEMPERATURE (°C)
Figure 44. K-Type Thermocouple Response
Thermocouple Example
For this example suppose the range of interest is from 0°C to 500°C, and the resolution needed is 0.5°C. The
power supply for both the LMV841, LMV842, or LMV844 and the ADC is 3.3V.
The temperature range of 0°C to 500°C results in a voltage range from 0mV to 20.6mV produced by the
thermocouple. This is shown in Figure 44.
To obtain the best accuracy the full ADC range of 0 to 3.3V is used and the gain needed for this full range can
be calculated as follows:
AV = 3.3V / 0.0206V = 160.
If RG is 2kΩ, then the value for RF can be calculated with this gain of 160. Since AV = RF / RG, RF can be
calculated as follows:
RF = AV * RG = 160 x 2kΩ = 320kΩ
To get a resolution of 0.5°C a step smaller then the minimum resolution is needed. This means that at least 1000
steps are necessary (500°C/0.5°C). A 10-bit ADC would be sufficient as this will give 1024 steps. A 10-bit ADC
such as the two channel 10-bit ADC102S021 would be a good choice.
Unwanted Thermocouple Effect
At the point where the thermocouple wires are connected to the circuit, usually copper wires or traces, an
unwanted thermocouple effect will occur.
At this connection, this could be the connector on a PCB, the thermocouple wiring forms a second thermocouple
with the connector. This second thermocouple disturbs the measurements from the intended thermocouple.
Using an isothermal block as a reference will compensate for this additional thermocouple effect . An isothermal
block is a good heat conductor. This means that the two thermocouple connections both have the same
temperature. The temperature of the isothermal block can be measured, and thereby the temperature of the
thermocouple connections. This is usually called the cold junction reference temperature.
In the example, an LM35 is used to measure this temperature. This semiconductor temperature sensor can
accurately measure temperatures from −55°C to 150°C.
24
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMV841 LMV842 LMV844
LMV841, LMV842, LMV844
www.ti.com
SNOSAT1G – OCTOBER 2006 – REVISED FEBRUARY 2013
The ADC in this example also coverts the signal from the LM35 to a digital signal. Now the microprocessor can
compensate the amplified thermocouple signal, for the unwanted thermocouple effect.
Cold junction Temperature
LM35
RF
RG
T
Metal A
Copper
-
RG
LMV841
+
Metal B
Thermocouple
Copper
Amplified
Thermocouple
Output
RF
Cold junction Reference
Figure 45. Thermocouple Amplifier
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMV841 LMV842 LMV844
Submit Documentation Feedback
25
LMV841, LMV842, LMV844
SNOSAT1G – OCTOBER 2006 – REVISED FEBRUARY 2013
www.ti.com
REVISION HISTORY
Changes from Revision F (February 2013) to Revision G
•
26
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 25
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMV841 LMV842 LMV844
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LMV841MG/NOPB
ACTIVE
SC70
DCK
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
A97
LMV841MGX/NOPB
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
A97
LMV841QMG/NOPB
ACTIVE
SC70
DCK
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
ATA
LMV841QMGX/NOPB
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
ATA
LMV842MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LMV84
2MA
LMV842MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LMV84
2MA
LMV842MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AC4A
LMV842MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AC4A
LMV842QMA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV84
2QMA
LMV842QMAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV84
2QMA
LMV842QMM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AA7A
LMV842QMMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AA7A
LMV844MA/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV844MA
LMV844MAX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV844MA
LMV844MT/NOPB
ACTIVE
TSSOP
PW
14
94
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV844
MT
LMV844MTX/NOPB
ACTIVE
TSSOP
PW
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV844
MT
LMV844QMA/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV844
QMA
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
11-Apr-2013
Status
(1)
LMV844QMAX/NOPB
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOIC
D
14
2500
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
CU SN
Level-1-260C-UNLIM
(4)
-40 to 125
LMV844
QMA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LMV841, LMV841-Q1, LMV842, LMV842-Q1, LMV844, LMV844-Q1 :
• Catalog: LMV841, LMV842, LMV844
• Automotive: LMV841-Q1, LMV842-Q1, LMV844-Q1
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMV841MG/NOPB
SC70
DCK
5
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV841MGX/NOPB
SC70
DCK
5
3000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV841QMG/NOPB
SC70
DCK
5
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV841QMGX/NOPB
SC70
DCK
5
3000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV842MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMV842MM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMV842MMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMV842QMAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMV842QMM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMV842QMMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMV844MAX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LMV844MTX/NOPB
TSSOP
PW
14
2500
330.0
12.4
6.95
8.3
1.6
8.0
12.0
Q1
LMV844QMAX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMV841MG/NOPB
SC70
DCK
5
1000
210.0
185.0
35.0
LMV841MGX/NOPB
SC70
DCK
5
3000
210.0
185.0
35.0
LMV841QMG/NOPB
SC70
DCK
5
1000
210.0
185.0
35.0
LMV841QMGX/NOPB
SC70
DCK
5
3000
210.0
185.0
35.0
LMV842MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMV842MM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMV842MMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LMV842QMAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMV842QMM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMV842QMMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LMV844MAX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
LMV844MTX/NOPB
TSSOP
PW
14
2500
367.0
367.0
35.0
LMV844QMAX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
Pack Materials-Page 2
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