TI TC246

TC246
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SOCS096 – JULY 2010
680 x 500 PIXEL IMPACTRON™ COLOR CCD IMAGE SENSOR
Check for Samples: TC246
FEATURES
1
16 SAG1
15 SAG2
14 VCLD
13 SUB
FP 11
SUB 12
NC 8
VOUT 10
17 P(-)
SUB 7
VDD 9
19 P(+)
18 P(-)
THER 6
21 IAG2
20 P(+)
RST 5
22 IAG1
CMG 4
•
•
•
•
DUAL-IN-LINE PACKAGE
(TOP VIEW)
SRG2 3
•
•
•
24 SUB
•
•
High Photoresponse Uniformity Over a Wide
Spectral Range
Solid State Reliability With No Image Burn-in,
Residual Imaging, Image Distortion, or
Microphonics
Package with Built-in Peltier Cooler and
Temperature Sensor
23 ODB
•
•
•
•
•
SUB 1
•
Very Low Noise, Very High Sensitivity,
Electronically Variable Charge Domain Gain
1/2-in Format, Solid State Charge-Coupled
Device (CCD) Frame Interline Transfer Color
Image Sensor for Low Light Level Applications
with 30 Frames/s or 60 Fields/s Readout Speed
Color Mosaic Filters On Chip
340,000 Pixels per Field
Frame Memory
658 (H) x 496 (V) Active Pixels in Image
Sensing Area
Multimode Readout Capability
– Progressive Scan
– Pseudo-Interlace Scan
– Line Summing
– Pixel Summing
0-8 V Serial Operation Except CMG Gate
Continuous Electronic Exposure Control from
1/30 s to 1/2,000 s
Advanced Lateral Overflow Drain
10.0-µm Square Pixels
Low Dark Current
RoHS-Compliant Product
SRG1 2
•
DESCRIPTION
The TC246 is a frame interline transfer CCD image sensor designed for use in single-chip color NTSC TV,
computer, and special-purpose applications requiring low noise, high sensitivity, high speed, and low smear.
The TC246 is a new device of the IMPACTRON™ family of very-low noise, high sensitivity, high speed and low
smear sensors that multiply charge directly in the charge domain before conversion to voltage. The charge
carrier multiplication (CCM) is achieved by using a low-noise single-carrier, impact ionization process that occurs
during repeated carrier transfers through high field regions. Applying multiplication pulses to specially designed
gates activates the CCM. Multiplication gain is variable by adjusting the amplitude of the multiplication pulses.
The device function resembles the function of an image intensifier implemented in solid state.
The image-sensing area of the TC246 is configured into 500 lines with 680 pixels in each line. 20 pixels are
reserved in each line for dark reference. The blooming protection is based on an advanced lateral overflow drain
concept that does not reduce NIR response. The frame interline transfer from the image sensing area to the
memory area is implemented to minimize image smear. After charge is integrated and stored in the memory it is
available for readout in the next cycle. This is accomplished by using a unique serial register design that includes
special charge multiplication pixels.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TC246
SOCS096 – JULY 2010
www.ti.com
The TC246 sensor is built using TI-proprietary advanced Split-Gate Virtual-Phase CCD (SGVPCCD) technology,
which provides devices with wide spectral response, high quantum efficiency (QE), low dark current, and high
response uniformity.
This MOS device contains limited built-in protection. During storage or handling, the device leads should be
shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be
connected to Vss. Under no circumstances should pin voltages exceed absolute maximum ratings. Avoid
shorting OUT to Vss during operation to prevent damage to the amplifier. The device can also be damaged if the
output and ADB terminals are reverse-biased and excessive current is allowed to flow. Specific guidelines for
handling devices of this type are contained in the publication "Electrostatic Discharge (ESD)" available from
Texas Instruments.
NOTE
Attention to EMCCD users:
The charge carrier multiplication (CCM) gain shift can be observed over a period of time.
As a results, a property fluctuation will occur under certain usage environment. In order to
minimize the change in characteristics with time, it is better not to use CCM gains beyond
necessity. Also exposing a sensor to a strong light source should be avoided.
2
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
For stable operation, a decoupling capacitor (1 µF, >5 V) needs to be connected externally from the package FP
pin to SUB.
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TC246
SOCS096 – JULY 2010
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Sensor Topology Diagram - TC246RGB-B0
20 Dark Reference Pixels
2 Dark Isolation Pixels
658 Active Pixels
R G R G
G B G B
R G
G B
496 Active Lines
<Image Cell Topologies>
10um Square
PD-Cell
V-Cell
<Color Filter Topologies>
Primary Color, Bayer Pattern
R
G
R
G
G
B
G
B
R
G
R
G
G
B
G
B
R = Red
G = Green
B = Blue
Antiblooming Drain
R
G
R
G
G
B
G
B
500 Lines
4 Dark Isolation Lines
20 Dark
Reference Pixels
658 Active Pixels
2 Dark
Isolation Pixels
3 Dummy
Pixels
279 Dummy Pixels
4
400 Multiplication Pixels
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Sensor Topology Diagram - TC246CYM-B0
20 Dark Reference Pixels
2 Dark Isolation Pixels
658 Active Pixels
<Image Cell Topologies>
496 Active Lines
10um Square
PD-Cell
V-Cell
<Color Filter Topologies>
Complementary Color Filter
Cy Ye Cy Ye
G Mg G Mg
Cy Ye Cy Ye
Mg G Mg G
Cy = Cyan
Ye = Yellow
Mg = Magenta
G = Green
Antiblooming Drain
500 Lines
4 Dark Isolation Lines
20 Dark
Reference Pixels
2 Dark
Isolation Pixels
658 Active Pixels
3 Dummy
Pixels
279 Dummy Pixels
400 Multiplication Pixels
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
CMG
4
I
Charge multiplication gate
FP
11
-
Field plate (connect external capacitor)
IAG1
22
I
Image area gate 1
IAG2
21
I
Image area gate 2
NC
8
-
No connection
ODB
23
I
Supply voltage for anti-blooming drain
OUT
10
O
Output signal, multiplier channel
P(-)
17, 18
I
Peltier cooler negative power supply
P(+)
19, 20
I
Peltier cooler positive power supply
RST
5
I
Reset gate
SAG1
16
I
Storage area gate 1
SAG2
15
I
Storage area gate 2
SRG1
2
I
Serial register gate 1
SRG2
3
I
Serial register gate 2
SUB
1, 7, 12, 13,
24
Chip substrate
THER
6
I
Thermistor (NTC: negative temperature coefficient)
VCLD
14
I
Supply voltage for clearing drain and ESD protection circuits
VDD
9
I
Supply voltage for amplifiers
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TC246
SOCS096 – JULY 2010
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DETAILED DESCRIPTION
The TC246 consists of five basic functional blocks: The image-sensing area, the image-storage area, the serial
register, the charge multiplier, and the charge detection node with buffer amplifier. The location of each of these
blocks is identified in the functional block diagram.
Image Sensing and Storage areas
As light enters the silicon in the image-sensing area, electrons are generated and collected in potential wells of
the pixels. Color is accomplished by on-chip color mosaic filter. (see the sensor topology diagram for a mapping
of the color filter) Applying a suitable DC bias to the antiblooming drain provides blooming protection. The
electrons that exceed a specific level, determined by the ODB bias, are drained away from the pixels. After the
integration cycle is completed by applying a PD-cell readout pulse to IAG2, charge is transferred from the PD-cell
into the V-cell and then quickly transferred into the storage cell where it waits for readout. TC246CYM-B0
enables 2 lines to sum together to implement the pseudo-interlace scan.
Additionally, 4 dark lines, located between the image sensing area and the image-storage area, were added to
the array for isolation.
Advanced Lateral Overflow Drain
Each pixel is constructed with the advanced lateral overflow drain structure. By varying the DC bias of the
anti-blooming drain it is possible to control the blooming protection level and trade it for well capacity.
Electronic Exposure Control
Precise exposure control timing on a frame-by-frame basis is possible. The integration time can be arbitrarily
shortened from its nominal length by clearing residual charge from the PD-cell. To do this, apply a PD-cell clear
pulse to IAG2, which marks the beginning of integration.
Serial Register and Charge Multiplier
The serial register of TC246 image sensor consists of only poly-silicon gates. It operates at high speed, being
clocked from 0 V to 8 V. This allows the sensor to work at 30 frames/s. The serial register is used for transporting
charge stored in the pixels of the memory lines to the output amplifier. The TC246 device has a serial register
with twice the standard length. The first half has a conventional design that interfaces with the memory as it
would in any other CCD sensor. The second half, however, is unique and includes 400 charge multiplication
stages with a number of dummy pixels that are needed to transport charge between the active register blocks
and the output amplifier. Charge is multiplied as it progresses from stage to stage in the multiplier toward the
charge detection node. The charge multiplication level depends on the amplitude of the multiplication pulses
(approximately 15 V to 22 V) applied to the multiplication gate. Due to the double length of the register, first two
lines in each field or frame scan do not contain valid data and should be discarded.
Charge Detection Node and Buffer Amplifier
The last element of the charge detection and readout chain is the charge detection node with the buffer amplifier.
The charge detection node is using a standard Floating Diffusion (FD) concept followed by an on-chip,
dual-stage, source-follower buffer. Applying a pulse to the RST pin resets the detection node. Pixel charge
summing function can be easily implemented by skipping the RST pulses. To achieve the ultimate sensor
performance it is necessary to eliminate kTC noise. This is typically accomplished by using CDS (correlated
double sampling) processing techniques. IMPACTRON devices have the potential for detecting single electrons
(photons) when cooled sufficiently.
6
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VSS
Supply voltage range
VI
Input voltage range
Vcool
Supply voltage range (3)
Icool
VDD, VCLD
(1)
(2)
ODB
0 V to 15 V
0 V to 22 V
IAG1, SAG1, SAG2
-10 V to 10 V
IAG2
-10 V to 13 V
SRG1, SRG2, RST
0 V to 10 V
CMG
-5 V to 22 V
P+
0 V to 5.5 V
Supply current range (3)
P+
0 A to 1.4 A
Ith
Supply current range
THER
TA
Operating free-air temperature range
-20°C to 75°C
Tstg
Storage temperature range
-30°C to 85°C
TC
Operating case temperature range
-20°C to 75°C
Dew point inside the package (3)
(1)
(2)
(3)
0 mA to 0.31 mA
Lower than -20°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to substrate terminal.
The peltier cooler generates heat during cooling process. Heat must be removed through an external heat sink. To avoid condensation
upon the surface, do not cool the CCD to less than -20°C.
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TC246
SOCS096 – JULY 2010
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
VSS
VDD
MIN
NOM
VDD
13.5
14
14.5
VCLD
13.5
14
14.5
ODB (1)
4.5
Substrate bias
0
Supply voltage
IAG1
IAG2
SAG1
VI
SAG2
Input voltage
SRG1
SRG2
CMG (2)
RST
3
3.3
3.6
-5.8
-5.5
-5.2
High
9.5
10
10.5
Mid
3
3.3
3.6
Low
-5.8
-5.5
-5.2
High
3
3.3
3.6
Low
-5.8
-5.5
-5.2
High
3
3.3
3.6
Low
-5.8
-5.5
-5.2
High
7.5
8
8.5
High
Load capacitance
Dew point inside the package
TA
Low
(1)
(2)
(3)
8
8
8.5
0
High
7
Low
-3
-2.5
-2
High
5.5
6
6.5
Low
22
0
1.5
1.5
SRG1, SRG2, RST
12.5
25
CMG
12.5
25
OUT
MHz
6
(3)
Operating free-air temperature
V
0
7.5
IAG1, IAG2
Clock frequency
V
6.5
Low
Low
UNIT
V
High
SAG1, SAG2
fCLK
MAX
-20
25
-20
°C
55
°C
Adjustment within the specified MIN/MAX range is required to optimize performance.
Charge multiplication gain depends on high level of the CMG and temperature.
-20°C should be the minimum temperature of the cooled CCD.
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ELECTRICAL CHARACTERISTICS
TA = 25°C, integration time = 16.67 ms (unless otherwise noted)
PARAMETER
MIN
TYP
Charge multiplication gain
1
100
Excess noise factor for typical CCM gain (1)
1
1.4
Dynamic range without CCM gain
Dynamic range with typical CCM gain
(2)
Charge conversion gain without CCM gain
(3)
Signal-response delay time (4)
Output resistance
Amplifier noise-equivalent signal without CCM gain
(5)
dB
75
dB
14
µV/e
16
ns
320
Ω
e
1
e
Response linearity with no CCM gain
1
1
Parallel transfer
0.99994
Serial transfer
0.99994
Supply current
Input capacitance
(6)
63
20
Charge-transfer efficiency (6)
(2)
(3)
(4)
(5)
UNIT
Amplifier noise-equivalent signal with typical CCM gain (5)
Response linearity with typical CCM gain
(1)
MAX
1
1
2
IAG1
3
IAG2
7
IAG1, IAG2
3
SAG1
4
SAG2
5
SAG1, SAG2
3
SRG1
85
SRG2
55
CMG
25
ODB
2000
RST
7
mA
nF
pF
Excess noise factor "F" is defined as the ratio of noise sigma after multiplication divided by M times the noise sigma before multiplication
where M is the charge multiplication gain.
Dynamic range is -20 times the logarithm of the noise sigma divided by the saturation-output signal amplitude
Charge conversion factor is defined as the ratio of output signal to input number of electrons.
Signal-response delay time is the time between the falling edge of the SRG1 pulse and the output-signal valid state.
The values in the table are quoted using correlated double sampling (CDS). CDS is a signal processing technique that improves
performance by minimizing undesirable effects of reset noise.
Charge transfer efficiency is one minus the charge loss per transfer in the CCD register. The test is performed in the dark using either
electrical or optical input.
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OPTICAL CHARACTERISTICS
TA = 25°C, integration time = 16.67 ms (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Without IR-cut filter
With typical CCM gain
With IR-cut filter
Sensitivity (1)
RGB Type TC246RGB-B0
Progressive scan operation
Without IR-cut filter
Without CCM gain
With IR-cut filter
MIN
Red
2700
Green
1700
Blue
1300
Red
150
Green
200
Blue
110
Red
27
Green
17
Blue
13
Red
1.5
Green
Blue
Without IR-cut filter
With typical CCM gain
With IR-cut filter
(1)
Sensitivity
CYM Type TC246CYM-B0
Progressive scan operation
Without IR-cut filter
Without CCM gain
With IR-cut filter
2420
3735
Magenta
3195
Green
2100
Cyan
280
Yellow
475
Magenta
275
Green
240
Cyan
24
Yellow
37
Magenta
32
Green
21
Cyan
2.8
Yellow
4.8
Magenta
2.7
Anti blooming enabled, no CCM gain
With typical CCM gain
180
100
Blooming overload ratio (4)
500:1
Smear
V/lx sec
2.4
Zero input offset output (3)
28k
(5)
V/lx sec
400
1500
Image area well capacity
UNIT
2
Yellow
Green
MAX
1.1
Cyan
No CCM gain
Saturation signal output (2)
TYP
mV
mV
e
-84
dB
Dark current (6)
0.01
nA/cm2
Dark signal (7)
0.01
mV
(1)
(2)
(3)
(4)
(5)
(6)
(7)
10
Light source temperature is 2856 °K. The IR filter used is CM500 1 mm thick.
Saturation is the condition in which further increase in exposure does not lead to further increases in output signal.
Zero input offset is the residual output signal measured from the reset level with no input charge present. This level is not caused by the
dark current and remains approximately constant independent of temperature. It may vary with the amplitude of SRG1.
Blooming is the condition in which charge induced by light in one element spills over to the neighboring elements.
Smear is the measure of error signal introduced into the pixels by transferring them through the illuminated region into the memory. The
illuminated region is 1/10 of the image area height. The value in the table is obtained for the integration time of 33.3 ms and 1.5 MHz
vertical clock transfer frequency.
Dark current depends on temperature and approximately doubles every 8 Co. Dark current is also multiplied by CCM operation. The
value given in the table is with the multiplier turned off and it is a calculated value.
Dark signal is actual device output measured in dark.
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OPTICAL CHARACTERISTICS (continued)
TA = 25°C, integration time = 16.67 ms (unless otherwise noted)
PARAMETER
Column uniformity
TEST CONDITIONS
MIN
TYP
1/2000
1/30
MAX
(8)
2
Electronic-shutter capability
Dark (zone A) (see Figure 1), -15°C,
CCM gain 100
Defect (9)
UNIT
s
Exceed 20mV
0
12mV to 20mV
10
Illuminated (zone A) (see Figure 1), 25°C, 100-mV output
-20
%
dot
20
%
Vertical belt noise (10)
-15°C, CCM gain 1000
6
mV
Horizontal streaking (11)
-15°C, CCM gain 1000
70
mV
(8)
Column uniformity is obtain by summing all the lines in the array, finding the maximum of the difference of two neighboring columns
anywhere in the array, and dividing the result by the number of lines.
(9) There shall be no pixel defect which continued horizontally.
(10) Vertical belt noise is dark current from CMG stage, when CCD generates CMG 1000 times with -15°C at thermistor. When 0 digress,
this value is multiplied by about 2.5 times. These values are under the condition of non-aging test when factory out.
(11) Streaking is a phenomenon that pixel in the right of blight pixels which are generated by huge light intensity source responses blighter
data, when CCD generates CMG 1000 times with -15°C at thermistor. When 0°C, this value is multiplied by about 0.8 times. These
values are under the condition of non-aging test when factory out.
How to Check Pixel Error Under Blight Condition
This value is calculated using Equation 1:
error(%) =
| Vout_normal – Vout_error | – Vout_OB
× 100
Vout_normal – Vout_OB
(1)
Analog
video output
Vout_normal
Vout_OB
Vout_error
(Max)
Vout_error
(Min)
Basis voltage (e.g., GND)
Vout_xx means analog video output voltage (mV) at the several pixels. Vout_error is at error pixel, Vout_normal
is at non-error pixel, and Vout_OB is at Optical Black pixel. This test is done when CCD receives white light
whose intensity becomes about 60mV video data value at non-error pixel, which is calculated by (Vout_normal Vout_OB).
Figure 1. Defect Area
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How to Measure Streaking Value
Driving timing:
1. The electron in V-cell is cleared by 750 lines (1.5 times normal operation) vertical transferring from V-cell to
storage area.
2. The electron in PD-cell is moved to V-cell.
3. The electron in 250 V-cell is moved to storage area by 250 parallel pulses (0.5 times as normal operation).
4. The electron in the last line of storage area is moved to serial resister.
5. The electron in serial resister is moved out by 2046 serial pulses (3 times as normal operation).
6. All the electrons in storage area are moved out by repeated 500 times both (4) and (5). Then the following
image is out.
Measurement condition:
CMG: 1000 times
Thermistor temperature: -15°C
Light intensity: 10 Lx
Calculation:
The value of streaking is difference between the average of the electron in streaking area and the one in
area B.
12
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SRG2 (CMG)
FP
SRG1
Polysilicon Gates
Pixel Cross Section
X
!
Channel Potential
Figure 2. Serial Register Pixel Cross-Section
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V-Cell Clearing
Recommend over 750 Pulses
Transfer to Storage
Area
500 Pulses
IAG1
PD-Cell Readout Pulse
PD-Cell Clear Pulse
Pulse Position
Determines Exposure
IAG2
501 Cycles
Line Transfer
SAG1
SAG2
682 Pulses
Line #500
(Total 502 line)
682 Pulses
Line # -1 (*)
682 Pulses
Line #0 (*)
RST
SRG1
SRG2
CMG
Expanded Section of Parallel Transfer
Expanded Section of Serial Transfer
Expanded Section of Serial Transfer
IAG1
RST
RST
IAG2
SRG1
SRG1
SAG1
SRG2
SRG2
SAG2
CMG
CMG
(*) Line # "-1" and "0" do not contain valid data
Figure 3. Progressive Scan Timing
14
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V-Cell Clearing
Recommend over 750 Pulses
Transfer to Storage
Area
A-field = 500 Pulses
B-field = 501 Pulses
IAG1
PD-Cell Readout Pulse
PD-Cell Clear Pulse
Pulse Position
Determines Exposure
IAG2
251 Cycles
Line Transfer
SAG1
Line Summing
SAG2
682 Pulses
Line #250
(Total 252 line)
682 Pulses
Line # -1 (*)
682 Pulses
Line #0 (*)
RST
SRG1
SRG2
CMG
Expanded Section of Parallel Transfer
Expanded Section of Serial Transfer
Expanded Section of Serial Transfer
IAG1
RST
RST
IAG2
SRG1
SRG1
SAG1
SRG2
SRG2
SAG2
CMG
CMG
(*) Line # "-1" and "0" do not contain valid data
Figure 4. Interlace Timing of Line Summing Mode
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RST
SRG1
SRG2
CMG
Reset Level
Vout
Zero Offset Signal
Reference
Level
Output Signal *
T : Signal-response delay
Clamp
S/H
* Output signal may not be zero for zero input charge.
Figure 5. Serial Register Clock Timing for CDS Implementation
16
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Figure 6. Detailed Output Signal
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Figure 7. Serial Transfer Timing (12.5 MHz Applications)
18
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Figure 8. Vertical Transfer Timing (1.5 MHz Application)
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Figure 9. Typical Line Transfer Timing
Figure 10. Typical PD-Readout and Exposure Control Timing
20
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Tp
Tp1
SAG1
Tp2
Tpx
SAG2
Minimum
800ns
Minimum
800ns
CMG
SRG1
SRG2
MIN
TYP MAX
667
Tp1*
230
260
290
Tl2*
300
330
390
Tpx*
40
50
60
Tp*
UNIT
ns
Figure 11. Typical Line Summing and Transfer Timing (1.5-MHz Application)
IAG1
PD-Cell Readout Pulse
PD-Cell Clear Pulse
Tpd
Tpdc
Pulse Position
Determines Exposure
IAG2
Hold time of Storage area**
Tpdx*
SAG1,2
CMG SRG1,2
241H 242H
Tpd
MIN
1.0
Tpdc
1.0
V-Blanking
TYP MAX
1.5
2.0
Tpdx*
1.5
2.0
-1H
UNIT
us
Tr
Tpd,Tpdc
MIN
250
MAX
1000
Tf
Tpd,Tpdc
100
1000
0H
1H
UNIT
ns
1.0
* Tpdx : as shorter as possible
** Hold time of Storage area : Recommend shorter than 300usec
Figure 12. Typical PD-Readout and Exposure Control Timing
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Figure 13. Typical Spectral Responsivity (Without On-Chip Color Filter)
Figure 14. Typical Spectral Quantum Efficiency (Without On-Chip Color Filter)
22
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20.0
18.0
Blue
R es p on s iv ity [V /u J /c m 2]
16.0
Green
14.0
Red
12.0
10.0
8.0
6.0
4.0
2.0
0.0
400
450
500
550
600
650
700
750
800
850
900
950
1000
1050
1100
Wave Length [nm]
Figure 15. TC246RGB-B0 Typical Spectral Quantum Efficiency
20.0
18.0
Cyan
R es p on s iv ity [V /u J /c m 2]
16.0
Yellow
14.0
Magenta
12.0
Green
10.0
8.0
6.0
4.0
2.0
0.0
400
450
500
550
600
650
700
750
800
850
900
950
1000
1050
1100
Wave Length [nm]
Figure 16. TC246CYM-B0 Typical Spectral Quantum Efficiency
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Figure 17. Typical Variation of Multiplication Gain with CMG High Voltage
Figure 18. Typical Cooling Capability
24
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Figure 19. Typical Thermistor Characteristics
Figure 20. Typical Thermistor Characteristics (Detail)
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IAG2-1 IN
IAG2-1 IN
IAG2-2 IN
IAG2 OUT
Figure 21. Typical IAG Driver Circuits
26
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+5.0V
+5.0V
3.9k
0.1uF
SAG1 IN
1.0k
+
HN1A01F
0.1uF
0.1uF
100uF/16V
10
+3.0V
1
470
1.0k
2
3
10
470
1.0k
SAG2 IN
4
VS+
OE
IN
GND
VH
OUT
VL
VS-
8
SAG1 OUT
7
6
2.2
0.1uF
+
100uF/16V
5
HN1A01F
EL7156CS
10
1
1.0k
1.0k
2
3
-6.0V
470
10
4
VS+
OE
IN
GND
VH
OUT
VL
VS-
8
SAG2 OUT
7
6
2.2
-6.0V
5
470
0.1uF
0.1uF
100uF/16V
+
Figure 22. Typical SAG Driver Circuits
Figure 23. Typical SRG and RST Driver Circuits
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Figure 24. Typical CMG Driver Circuits
28
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Mechanical Data
The package for the TC246 consists of a ceramic base, a glass window, and a 24-pin lead frame. The glass
window is hermetically sealed to the package. The package leads are configured in a dual-in-line arrangement
and fit into mounting holes with 1,78 mm center-to-center spacing.
CAUTION
The TC246 glass window is very weak for the mechanical internal stress. Be careful
when attaching an external heat sink to the package. Fastening it too strongly may
crack or puncture the package, making it susceptible to moisture or humidity.
Recommended conditions are:
1. Torque control for the screw (M1.6 micro screw) should be under 0.5 kgf*cm.
2. Paste "Lock Tight" on the screw. Recommendation is Three Bond 1401B.
3. As for the soldering condition, do not exceed 80ºC for the package temperature. Since a
reflow or solder dip may cause glass lid crack or fracture, the grounded soldering iron shall
be used and the operation shall be less than 2 seconds per pin.
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