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D Very Low Noise, High Sensitivity
D
D
D
D
D
D
D
D
D
D
D
D
D
Electronically Variable
High Resolution, 1/3-in Format, Solid State
Charge-Coupled Device (CCD) Frame
Transfer Image Sensor for Black and White,
NTSC, and Computer Applications
340,000 Pixels per Field
Frame Memory
656 (H) × 496 (V) Active Pixels in Image
Sensing Area Compatible With Electronic
Centering
Multimode Readout Capability
− Progressive Scan
− Interlace Scan
− Line Summing
Fast Single-Pulse Clear Capability
Continuous Electronic Exposure Control
From 1/30 s to 1/5,000 s
7.4-µm Square Pixels
Advanced Lateral Overflow Drain
Low Dark Current
High Photoresponse Uniformity Over a
Wide Spectral Range
Solid-State Reliability With No Image
Burn-In, Resideual Imaging, Image
Distortion, Image Lag, or Microphonics
Package With Peltier Cooler
DUAL−IN−LINE PACKAGE
(TOP VIEW)
P+ 1
22 P −
P+ 2
21 P −
GND 3
20 GND
ODB 4
19 IAG1
IAG2 5
18 SAG1
SAG2 6
17 SUB
SRG1 7
16 NC
SRG2 8
15 ADB
CMG 9
14 NC
SUB 10
13 VOUT
NC 11
12 GND
description
The TC253SPD-B0 is a frame-transfer, CCD image sensor designed for use in black and white, NTSC TV,
computer, and special-purpose applications requiring high sensitivity, low noise, and small size.
The TC253SPD-B0 is a new device of the IMPACTRON family of very-low noise, high sensitivity image sensors
that multiply charge directly in charge domain before conversion to voltage. The charge carrier multiplication
(CCM) is achieved by using a low-noise single-carrier, impact ionization process that occurs during repeated
carrier transfers through high-field regions. Applying multiplication pulses to specially designed gates activates
the CCM. The amount of multiplication is adjustable depending on the amplitude of the multiplication pulses. The
device function resembles the function of image intensifiers implemented in solid state.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic-voltage level,
preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
IMPACTRON is a trademark of Texas Instruments.
Copyright 2003, Texas Instruments Incorporated
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/ (( &%!%"*
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description (continued)
The image-sensing area of the TC253SPD-B0 is configured into 500 lines with 680 pixels in each line.
Twenty-four pixels are reserved in each line for dark reference. The blooming protection is based on an
advanced lateral overflow drain concept that does not reduce NIR response. The sensor can be operated in
the interlaced or progressive scan modes and can capture a full 340,000 pixels in one image field. The frame
transfer from the image sensing area to the memory area is accomplished at a very high rate that minimizes
image smear. The electronic exposure control is achieved by clearing unwanted charge from the image area
using a short positive pulse applied to the antiblooming drain. This marks the beginning of the integration time,
which can be arbitrarily shortened from its nominal length. After the charge is integrated and stored in memory,
it becomes available for readout in the next cycle. This is accomplished using a unique serial register design
that includes special charge multiplication pixels.
The TC253SPD-B0 sensor is built using TI-proprietary advanced split-gate virtual-phase CCD (SGVPCCD)
technology, which provides devices with wide spectral response, high quantum efficiency (QE), low dark
current, and high response uniformity. The TC253SPD-B0 sensors are characterized for operation from –10°C
to 45°C.
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functional block diagram
4
ODB
Dark Reference Pixels
5
IAG2
Image Sensing Area
19
IAG1
With Blooming Protection
6
18
Image Storage Area
SAG2
7
SAG1
17
SUB
SRG1
Serial Readout Register
15
ADB
8
Clearing Drain
SRG2
13
Charge Multiplier
VO
9
CMG
Output Amplifier
10
SUB
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sensor topology diagram
24 Dark
Reference
Pixels
656 Active Pixels
(First and last are half shielded pixels)
Dark Reference Pixels
496 Active Lines
Image Sensing Area
With Blooming Protection
4 Dark
Isolation Lines
Image Storage Area
500 Lines
Optical Black Pixels (OPB)
24
656 Active Pixels
98
400 Multiplication Pixels
Dummy Pixels
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Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
ADB
15
I
Supply voltage for amplifiers and clearing drain
CMG
9
I
Charge multiplication gate
GND
3, 12, 20
IAG1
19
I
Image area gate 1
IAG2
5
I
Image area gate 2
11, 14, 16
−
No connection
NC
ODB
Ground
4
I
Supply voltage for antiblooming drain
P+
1, 2
I
Peltier cooler power supply—positive
P−
21, 22
I
Peltier cooler power supply—negative
SAG1
18
I
Storage area gate 1
SAG2
6
I
Storage area gate 2
SRG1
7
I
Serial register gate 1
SRG2
8
I
Serial register gate 2
10, 17
−
Chip substrate
13
O
Output signal, multiplier channel
SUB
VOUT
detailed description
The TC253SPD-B0 consists of four basic functional blocks: The image-sensing area, the image-storage area,
the serial register, and the charge multiplier. The location of each of these blocks is identified in the functional
block diagram.
image-sensing and storage areas
Figure 1 shows cross sections with potential-well diagrams. As light enters the silicon in the image-sensing
area, electrons are generated and collected in the potential wells of the pixels. Applying a suitable dc bias to
the antiblooming drain provides blooming protection. The electrons that exceed a specified level, determined
by the ODB bias, are drained away from the pixels. If it is necessary to remove all previously accumulated charge
from the wells, a short positive pulse must be applied to the drain. This marks the beginning of the new
integration period. After the integration cycle is completed, charge is quickly transferred into the memory where
it waits for readout. The lines can be read out from the memory in a sequential order to implement progressive
scan, or two lines can be summed together to implement the pseudo-interlace scan.
Twenty-four columns at the left edge of the image-sensing area are shielded from the incident light. These pixels
provide the dark reference used in subsequent video-processing circuits to restore the video-black level. Four
additional dark lines, located between the image sensing area and the image-storage area, are added for
isolation.
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IAG2/SAG2
IAG1/SAG1
Polysilicon Gates
p+
Virtual Phase
ÎÎÎÎÎÎÎÎÎ
+++++++++++++++++++++++++
n − Buried Channel
p − Substrate
Pixel Cross Section
X
Integrated
Charge
Ø
Channel Potential
Figure 1. Image Area and Storage Area Pixel Cross Section With Potential Diagram
advanced lateral overflow drain
The advanced lateral overflow drain structure is shared by two neighboring pixels in each line. Varying the dc
bias of the antiblooming drain controls the blooming protection level and trades it for well capacity. Applying a
pulse to the drain, approximately 7 V above the nominal level for a minimum of 1 µs, removes all charge from
the pixels. This feature permits precise control of the integration time on a frame-by-frame basis. The
single-pulse clearing capability also reduces smear by eliminating accumulated charge in pixels before the start
of the integration period (single-sided smear). The application of a negative 0.5-V pulse to the antiblooming
drain during the parallel transfer is recommended. This pulse prevents the creation of undesirable artifacts
caused by the on-chip cross talk between the image area gate clock lines and the antiblooming drain bias lines.
serial register and charge multiplier
The serial register is used for transporting charge stored in the memory pixels to the output amplifier. However,
the TC253SPD-B0 device has a serial register with twice the standard length. The first half has a conventional
design that interfaces with the memory and the clearing drain as it would in any other CCD sensor (for example
the TC237 sensor). The second half, however, is unique and includes 400 charge-multiplication stages with a
number of dummy pixels that are needed to transport charge between the active register blocks and the output
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amplifier. Charge is multiplied as it progresses from stage to stage in the multiplier toward the charge detection
node. The charge multiplication level depends on the amplitude of the multiplication pulses (approximately 11
V~15 V) applied to the multiplication gates. Due to the double length of the register, the first line in the field or
frame scan does not contain valid data and should be discarded.
readout and video processing
The last element of the charge readout and detection chain is the charge detection node. The charge detection
node uses standard floating diffusion (FD) concepts followed by dual stage source followers as buffer amplifiers.
The reset gate is internally connected to SRG1. This results in simultaneous FD resets when the SRG1 gate
is clocked high. To achieve the ultimate sensor performance, it is necessary to eliminate kTC noise using CDS
processing techniques. The IMPACTRONTM devices can detect single photons when cooled or when
sufficiently short integration times are used.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, Vss: ADB (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUB to SUB + 15 V
Supply voltage range, Vss: ODB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUB to SUB + 20 V
Input voltage range, VI: IAG, SAG, SRG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −8 V to + 8 V
Input voltage range, VI: SRG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 V to + 8 V
Input voltage range, VI: CMG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 V to + 15 V
Supply voltage range, Vcool: P+ (see Note2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V + 3 V
Supply current range, Icool: P+ (see Note2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 mA to 700 mA
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10°C to 45°C
Storage temperature range, TSTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30°C to 85°C
Operating case temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10°C to 55°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to substrate terminal.
2. Peltier cooler generates heat during cooling process. To keep case temperature range, the heat must be removed through external
heat sink.
recommended operating conditions
MIN
NOM
11.5
12
12.5
For blooming control (see Note 3)
4.3
5.3
6.3
For clearing
12
12.5
13
For transfer (see Note 4)
3.8
4.8
5.8
5.5
Substrate bias, VSS
Input voltage, VI
UNIT
0
ADB
Supply voltage, VDD
MAX
ODB
IAG1
High
4.9
5.2
IAG2, SAG1, SAG2
High
2.8
3.1
3.4
IAG1, SAG1
Low
−6.3
−6
−5.7
IAG2, SAG2
Low
−7
−6.7
−6.4
SRG1, SRG2
High
4.6
4.9
5.2
SRG1
Low
−4.6
−4.3
−4
SRG2
Low
−5.8
−5.5
−5.2
CMG (see Note 5)
High
(Gain)
7
(1)
14.5
(30)
15
(100)
−3.1
−2.8
−2.5
Low
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V
V
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Clock frequency, fclk
Load capacitance
SAG1, SAG2
3.125
IAG1, IAG2
3.125
SRG1, SRG2
12.5
CMG
12.5
OUT
Operating free-air temperature, TA
−10
MHz
6
pF
45
°C
NOTES: 3. Adjustment within the specified MIN − MAX range may be required to optimize performance.
4. Application of a negative 0.5-V pulse (with respect to blooming control level) during parallel transfer is recommended for better
antiblooming performance.
5. Over time, slight increase in CMG high level may be required to achieve corresponding gain.
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electrical characteristics over recommended operating ranges of supply voltage at operating
free-air temperature (unless otherwise noted)
MIN
TYP‡
Charge multiplication gain
1
30
Excess noise factor for typical CCM gain (see Note 6)
1
1.4
PARAMETER
τ
UNIT
Dynamic range without CCM gain
64
dB
Dynamic range with typical CCM gain (see Note 7)
66
dB
Charge conversion gain without CCM gain (see Note 8)
9
µV/e-
Signal-response delay time (see Note 9)
9
ns
Output resistance
320
Amplifier noise-equivalent signal without CCM gain†
29
Ω
e rms
Response linearity without CCM gain
1
Response linearity with typical CCM gain
1
Charge-transfer efficiency (see Note 10)
Supply current
Ci
MAX
(100)§
Input capacitance
0.9999
2
3
IAG1
3
IAG2
3.2
IAG1-IAG2
2
SAG1
3
SAG2
3.6
SAG1-SAG2
2.2
SRG1
40
SRG2
40
SRG1−SRG2
50
CMG
30
CMG−SRG1
10
ODB
Pulse amplitude rejection ratio
0.9998
4
mA
nF
pF
1,000
ADB high (see Note 11)
20
SRG−1,2 high (Note 11)
45
SRG−1,2 low (Note 11)
45
CMG high (see Note 11)
45
CMD low (see Note 11)
45
dB
OBD low (see Note 11)
45
† The values in the table are quoted using CDS = correlated double sampling. CDS is a signal-processing technique that improves performance
by minimizing undesirable effects of reset noise.
‡ All typical values are at TA = 25°C.
§ Maximum CCM gain is not ensured.
NOTES: 6. Excess noise factor F is defined as the ratio of noise sigma after multiplication divided by M times the noise sigma before
multiplication, where M is the charge multiplication gain.
7. Dynamic range is – 20 times the logarithm of the noise sigma divided by the saturation-output signal amplitude.
8. Charge-conversion factor is defined as the ratio of output signal to input number of electrons.
9. Signal-response delay time is the time between the falling edge of the SRG2 pulse and the output-signal valid state.
10. Charge transfer efficiency is one minus the charge loss per transfer in the CCD register.
11. Rejection ratio is – 20 times the logarithm of the output referenced to the reset level divided by the 1 V of amplitude change of the
corresponding gate or terminal signal.
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optical characteristics, TA = 25°C (unless otherwise noted)
PARAMETER
MIN
No IR filter
Sensitivity with typical CCM gain (see Note 12)
Sensitivity without CCM gain (see Note 12)
Vsat
Voff
TYP
MAX
UNIT
290
With IR filter
36
No IR filter
9.6
With IR filter
1.2
Saturation signal output without CCM gain (see Note 13)
300
400
Handling capacity of charge multiplier
400
500
Zero-input offset output (see Note 14)
90
Blooming overload ratio (see Note 15)
V/Lx*s
V/Lx*s
mV
200
mV
1000:1
Image area well capacity
33k
Smear (see Note 16)
e-/pixel
44k
Dark current (see Note 17 and Note 22)
0.01
60
0.03
dB
nA/cm2
Dark signal (see Note 18 and Note 22)
0.005
0.015
mV
0.15
mV
0.1
mV
1.5
mV
20
%
4.5
mV
Dark-signal uniformity (see Note 19)
Dark-signal shading (see Note 20)
Dark
Spurious nonuniformity
0.8
Illuminated
−20
Column uniformity (see Note 21)
Electronic-shutter capability
1/5000
1/30
s
NOTES: 12. Light source temperature is 2856 °K. The IR filter used is CM500, 1-mm thick.
13. Saturation is the condition in which further increase in exposure does not lead to further increases in output signal.
14. Zero-input offset is the residual output signal measured from the reset level with no input charge present. This level is not caused
by the dark current and remains approximately constant, independent of temperature. It may vary with the amplitude of SRG.
15. Blooming is the condition in which charge induced by light in one element spills over to the neighboring elements.
16. Smear is the measure of error signal introduced into the pixels by transferring them through the illuminated region into the memory.
The illuminated region is 1/10 of the image area height. The value in the table is obtained for an integration time of 16.66 ms and
a 3.125-MHz vertical-clock transfer frequency.
17. Dark current depends on temperature and approximately doubles every 8 oC. Dark current is also multiplied by CCM operation. The
value given in the table is with the multiplier turned off and it is a calculated value.
18. Dark signal is actual device output measured in darkness.
19. Dark signal uniformity is the sigma of the difference between two neighboring pixels taking from all the image area pixels.
20. Dark signal shading is the difference between maximum and minimum of a 5-pixel median taken anywhere in the array.
21. Column uniformity is obtained by summing all the lines in the array, finding the maximum of the difference between two neighboring
columns anywhere in the array, and dividing the result by the number of lines.
22. There will be an estimated 20% degradation in dark current performance when exposed to 320 nm UV light at 1 uWatt/cm2 for
2700 hours.
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Clear
Integrate
Transfer to Memory
Readout
Pulse Position
Determines Exposure
ODB
IAG1
IAG2
501 Cycles
SAG1
SAG2
685 Pulses Line 0 {
685 Pulses Line 500
SRG1
686 Pulses Line 500
686 Pulses Line 0 {
686 Pulses Line 500
686 Pulses Line 0 {
SRG2
CMG
Expanded Section of Parallel Transfer
500 Pulses
Expanded Section of Serial Transfer
Expanded Section of Serial Transfer
IAG1
IAG2
SRG1
SRG1
SAG1
SRG2
SRG2
SAG2
CMG
CMG
{ Line 0 does not contain valid data.
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Figure 2. Progressive Scan Timing
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Clear
Integrate
Transfer to Memory
Readout
Pulse Position
Determines Exposure
ODB
IAG1
IAG2
251 Cycles
SAG1
SAG2
685 Pulses Line 0 {
685 Pulses Line 250
SRG1
686 Pulses Line 250
686 Pulses Line 0 {
686 Pulses Line 250
686 Pulses Line 0 {
SRG2
CMG
Expanded Section of Parallel Transfer
500 Pulses Even Field, 501 Pulses Odd Field
Expanded Section of Serial Transfer
Expanded Section of Serial Transfer
IAG1
IAG2
SRG1
SRG1
SAG1
SRG2
SRG2
SAG2
CMG
CMG
{ Line 0 does not contain valid data.
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Figure 3. Interlace Timing for Line Summing Mode
CMG
SRG1
SRG2
VOUT
Reset Level
Zero Offset Signal
Output Signal
S/H
Clamp
* Output signal may not be zero for zero input charge.
Figure 4. Serial Resistor Clock Timing for CDS Implementation
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Vout - mV
vs
INPUT LIGHT INTENSITY
700
600
Gain100
(100 x 9 µV/e)
500
VO − mV
Gain50
(50 x 9 µV/e)
400
Gain30
(30 x 9 µV/e)
Handling Capacity of
Charge Multiplier
300
200
100
Dark signal (Depends on temperature and CCM gain)
Zero offset
0
Input Light Intensity
Figure 5. Photon Transfer Characteristic of CCD Output
TC253 SPECTRAL RESPONSIVITY
RESPONSIVITY
vs
WAVELENGTH
0.30
QE=50%
QE=40%
Responsivity − A/W
0.25
QE=30%
0.20
0.15
QE=20%
0.10
0.05
0.00
400
500
600
700
800
900
Wavelength − nm
1000 1100
Figure 6. Typical Spectral Responsivity
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TC253 SPECTRAL SENSITIVITY
SENSITIVITY
vs
WAVELENGTH
10
9
Sensitivity - V/µJ/cm2
8
7
6
5
4
3
2
1
0
400
500
600
700
800
900
1000
1100
Wavelength - nm
Figure 7. Typical Spectral Sensitivity
TC253 SPECTRAL SENSITIVITY (CCM on)
SENSITIVITY
vs
WAVELENGTH
600
550
500
Gain 100
Sensitivity - V/µJ/cm2
450
400
350
300
250
200
Gain 30
150
100
50
0
400
500
600
700
800
900
1000
1100
Wavelength - nm
Figure 8. Typical Spectral Sensitivity (CCM on)
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TC253 QUANTUM EFFICIENCY
QUANTUM EFFICIENCY
vs
WAVELENGTH
100
Quantum Efficiency − %
50
10
1
0
400
500
600
700
800
900
1000 1100
Wavelength − nm
Figure 9. Typical Spectral Quantum Efficiency
TC253 DARK CURRENT
DARK CURRENT
vs
TEMPERATURE
Dark current − e-/pix/sec
100
10
1
0
−10
−5
0
5
10
15
Temperature − °C
20
25
30
Figure 10. Typical Variation of Dark Current with Temperature
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TC253 CCM GAIN
CCM GAIN
vs
CMG VOLTAGE
1000
500
300
-8 °C
-2 °C
8 °C
25 °C
CCM Gain
100
50
30
10
5
3
1
10.8 11.2 11.6 12.0 12.4 12.8 13.2 13.6 14.0 14.4 14.8
CMG Voltage - V
Figure 11. Typical Variation of CCM Gain with CMG Voltage
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Vcc
−Vsrg2 +Vsrg2 −Vsrg1 +Vsrg1
−Viag2 +Viag2 −Viag1 +Viag1
−Vsag2 +Vsag2 −Vsag1 +Vsag1 Vodb Vcl
ODB1
1
Vcc
10 k
2
SAG2
3
−Vsag1
4
VS+
OE
IN
GND
VH
OUT
VL
VS−
1
8
−Vsag2
6
5
0.1 EL7156CS
10 k
Vcc
7
0.1
ODB1
+Vsag1
+Vsag2
2
SAG1
3
−Vsag2
4
VS+
OE
IN
GND
VH
OUT
VL
VS−
ODB2
8
ODB2
7
GND
−Vsag1
6
ODBout
ODB Driver
5
0.1 EL7156CS
0.1
Vodb
0.1
0.1
P+
+Viag2
1
Vcc
10 k
2
IAG2
3
−Viag2
4
VS+
OE
IN
GND
VH
OUT
VL
VS−
+Viag1
8
1
−Viag2
6
5
0.1 EL7156CS
10k
Vcc
7
0.1
P−
1
2
3
4
5
6
7
8
9
10
11
2
IAG1
3
−Viag1
4
VS+
OE
IN
GND
VH
OUT
VL
VS−
8
7
−Viag1
6
5
0.1 EL7156CS
0.1
0.1
0.1
P+
P−
P+
P−
GND
GND
ODB
IAG1
IAG2
SAG1
SAG2
SUB
SRG1
NC
SRG2
ADB
CMG
NC
SUB
Vout
Reserved GND
22
21
20
19
18
17
16
15
14
13
12
0.1
TC253SPD−B0
+Vsrg2
1
Vcc
10 k
2
SRG2
3
4
VS+
OE
IN
GND
VH
OUT
VL
VS−
EL7156CS
+Vsrg1
8
1
10k
Vcc
7
−Vsrg2
6
5
SRG1
2
3
4
0.1
0.1
VS+
OE
IN
GND
VH
OUT
VL
VS−
OUT
8
7
Vcmdh Vcmdl
−Vsrg1
6
CMG
5
EL7156CS
0.1
CMG
Vcmgh
Vcmgl
0.1
GND
CMGout
CMG Driver
Vcc
Vcc
+
0.1
IAG1
IAG2
SAG1
SAG2
33
SRG1
SRG2
Oscillator
CLK
GND
CMG
DC Voltages (Typ.)
Vcl
12 V
+Viag1
3.1 V
−Vsrg2
−5.5 V
Vodb
12.5 V
−Viag1
−6.0 V
Vcmgh
14.5 V
Vcc
5V
+Viag2
3.1 V
Vcmgl
−2.8 V
ODB1
ODB2
+Vsag1
3.1 V
−Viag2
−6.7 V
CLMP
S/H
SYNC
LCLMP
CLEAR
−Vsag1
−6.0 V
+Vsrg1
4.9 V
+Vsag2
3.1 V
−Vsrg1
−4.3 V
−Vsag2
−6.7 V
+Vsrg2
4.9 V
User Defined Timer
Notes: A. All values are in Ohms and Microfarads unless otherwise noted.
B. TI recommends AC coupled system for coupling to the next video processing circuits.
C. IAG and SAG signal from ”User Defined Timer” should be shifted its GND level to −V before the driver IC (EL7156CS) input.
D. The value of the CCD external capaciters (on IAG and SAG) were recommended with 1000pF.
E. P+ and P− should be connected to the cooling controller (current source for the peltier cooler).
Figure 12. Typical Application Circuit Diagram
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× JULY 2003 − SOCS084
Vcmgh
0.1
1SS226
2200p
10 k
1SS193
TP2104N3
CMG
0.1
10 k
CMGout
0.1
TN2106N3
2200p
1SS193
1SS226
10 k
0.1
Vcmgl
CMG Driver Circuit
Vodb = 24 V
2.7 k
VR
2.0 k
5.6 k
0.1
Q1
10
2.7 k
1.5 k
ODBout
1.5 k
Q2
ODB1
3.3 k
3.3 k
Q3
ODB2
3.3 k
ODB Driver Circuit
Notes: A. All values are in Ohms and Microfarads unless otherwise noted.
Figure 13. Example of CMG Driver Circuit
20
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• DALLAS, TEXAS 75265
× JULY 2003 − SOCS084
MECHANICAL DATA
The package for the TC253SPD-B0 consists of a ceramic base, a glass window, and a 22-lead frame. The glass
window is sealed to the package by an epoxy adhesive. The package leads are configured in a dual-in-line
arrangement and fit into mounting holes with 1,78-mm center-to-center spacing.
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21
× JULY 2003 − SOCS084
22
POST OFFICE BOX 655303
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