DRV8850 www.ti.com SLVSCC0A – NOVEMBER 2013 – REVISED JANUARY 2014 Low-Voltage H-Bridge IC With LDO Voltage Regulator FEATURES DESCRIPTION • The DRV8850 device provides a motor driver plus LDO voltage regulator solution for consumer products, toys, and other low-voltage or batterypowered motion-control applications. The device has one H-bridge driver to drive a DC motor, a voice-coil actuator, one winding of a stepper motor, a solenoid, or other devices. The output driver block consists of N-channel power MOSFETs configured as an Hbridge to drive the load. An internal charge pump generates the needed gate-drive voltages. 1 2 • • • • • • • • H-Bridge Motor Driver – Drives a DC Motor, One Winding of a Stepper Motor, or Other Loads – Low MOSFET On-Resistance: 45 mΩ per FET 5-A Continuous 8-A Peak-Drive Current Internal Current Sensing With Current Sense Output 2 to 5.5-V Operating Supply Voltage Range Overvoltage and Undervoltage Lockout Low-Power Sleep Mode 100-mA Isolated Low-Dropout (LDO) Voltage Regulator 24-Pin QFN Package 24-Pin HTSSOP Package APPLICATIONS • Battery-Operated Applications With High Startup Torque, such as: – Personal Hygiene (Electric Toothbrushes, Shavers) – Toys – RC Helicopters and Cars – Robotics The DRV8850 device supplies up to 5 A of continuous output current (with proper PCB heat sinking) and up to 8-A peak current. It operates on a supply voltage from 2.0 to 5.5 V. A low-dropout linear voltage regulator is integrated with the motor driver to supply power to microcontrollers or other circuits. The LDO voltage regulator can be active in device sleep mode, so that the driver may be shut down without removing power to any devices powered by the LDO voltage regulator. Internal shutdown functions provide overcurrent, short-circuit, undervoltage, overvoltage, and overtemperature protection. In addition, the device also has a built-in current sensing for accurate current measurement. The DRV8850 device is packaged in a 24-pin HTSSOP (7.7 mm × 4.4 mm) or QFN (3.5-mm × 5.5mm) package with PowerPAD™ (Eco-friendly: RoHS and no Sb/Br). 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013–2014, Texas Instruments Incorporated DRV8850 SLVSCC0A – NOVEMBER 2013 – REVISED JANUARY 2014 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. FUNCTIONAL BLOCK DIAGRAM LDOOUT 2.0 to 5.5 V LDOEN LDOOUT VCP VCC LDO Regulator LDOFB VCC Overvolt Undervolt Charge Pump VCC VCC SR VCC VCC OUT1 OverTemp OCP ISEN Gate Drive OUT1 OUT1 Osc IN1H IN1L DCM VCC Logic OUT2 IN2H IN2L Gate Drive OCP ISEN OUT2 OUT2 VPROPI nSLEEP GND GND GND GND 2 PPAD Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links :DRV8850 DRV8850 www.ti.com SLVSCC0A – NOVEMBER 2013 – REVISED JANUARY 2014 DEVICE INFORMATION OUT1 OUT1 OUT1 IN1H IN1L IN2H IN2L nSLEEP LDOEN SR GND GND 1 24 DRV8850RGY (QFN) PACKAGE (TOP VIEW) 2 23 3 22 4 21 20 5 GND 1 (PPAD) 6 7 19 18 8 17 9 16 10 15 11 14 OUT2 OUT2 OUT2 VCC VCC VCC VCP VPROPI LDOOUT LDOFB 12 13 GND GND DRV8850PWP (HTSSOP) PACKAGE (TOP VIEW) GND 1 24 GND OUT1 2 23 OUT2 OUT1 3 22 OUT2 OUT1 4 21 OUT2 IN1H 5 20 VCC IN1L 6 19 VCC IN2H 7 18 VCC IN2L 8 17 VCP nSLEEP 9 16 VPROPI LDOEN 10 15 LDOOUT SR 11 14 LDOFB GND 12 13 GND GND (PPAD) Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links :DRV8850 3 DRV8850 SLVSCC0A – NOVEMBER 2013 – REVISED JANUARY 2014 www.ti.com Table 1. Terminal Functions PIN I/O (1) DESCRIPTION NAME NO. GND 1, 12, 13, 24, PPAD – Device ground LDOOUT 15 – LDO regulator output Bypass to GND with a 2.2-μF 6.3-V ceramic capacitor VCC 21, 22, 23 – Device supply Bypass to GND with 0.1-μF and 10-μF 6.3-V ceramic capacitors VCP 17 – Charge pump POWER AND GROUND Connect a 0.1-μF 6.3-V ceramic capacitor to VCC CONTROL LDOEN 10 I LDO regulator enable Logic low disables LDO regulator Logic high enables LDO regulator Internal pulldown resistor LDOFB 14 I LDO regulator feedback Resistor divider from LDOOUT sets LDO output voltage May be connected to LDOIN to enable LDO IN1H 5 I Input 1 HS FET enable Active high enables HS FET for output 1 Internal pulldown resistor IN1L 6 I Input 1 LS FET enable Active high enables LS FET for output 1 Internal pulldown resistor IN2H 7 I Input 2 HS FET enable Active high enables HS FET for output 2 Internal pulldown resistor IN2L 8 I Input 2 LS FET enable Active high enables LS FET for output 2 Internal pulldown resistor nSLEEP 9 I Sleep mode input Logic low puts device in low-power sleep mode Logic high for typical operation Internal pulldown resistor SR 11 IO Slew rate control Resistor to ground sets output slew rate OUTPUT (1) OUT1 2, 3, 4 O Output 1 OUT2 18, 19, 20 O Output 2 VPROPI 16 O Current sense output Connect to motor winding Output current is proportional to H-bridge current. 1 kΩ, 1% resistor to GND for 2-A max current with VCC at 2 V. See text for equation if more current is required Directions: I = input, O = output, OZ = 3-state output, OD = open-drain output, IO = input or output Table 2. External Components PIN 4 DESCRIPTION NAME NO. LDOFB 14 LDO regulator feedback Resistor divider from LDOUT sets LDO output voltage. LDOOUT 15 LDO regulator output Bypass to GND with a 2.2-μF 6.3-V ceramic capacitor. SR 11 Slew rate control Resistor to ground sets output slew rate GND to 2.4 MΩ. VCC 21, 22, 23 Device supply Bypass to GND with 0.1-μF and 10-μF 6.3-V ceramic capacitors. VCP 17 Charge pump Connect a 0.1-μF 6.3-V ceramic capacitor to VCC VPROPI 16 Current sense output Output current is proportional to H-bridge current. 1 kΩ, 1% resistor to GND for 2-A max current with VCC at 2 V. See Equation 1 for if more current is required. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links :DRV8850 DRV8850 www.ti.com SLVSCC0A – NOVEMBER 2013 – REVISED JANUARY 2014 Absolute Maximum Ratings (1) (2) over operating free-air temperature range (unless otherwise noted) MIN TYP MAX VCC Power supply voltage range –0.3 7 VCP Charge pump –0.3 VCC + 7 LDOEN, IN1H, IN1L, IN2H, IN2L, nSLEEP Digital pin voltage range –0.5 7 OUT1, OUT2, SR, LDOUT, LDOFB, VPROPI Other pins –0.3 7 OUT1, OUT2 Peak motor drive output current Internally Limited LDOOUT LDO output current Internally Limited TJ Operating junction temperature range –40 150 TSTG Storage temperature range –60 150 (1) (2) UNIT V A °C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VCC Device power supply voltage range IOUT H-bridge continuous output current (1) (1) NOM MAX UNIT 2.0 5.5 V 0 5 A IOUT H-bridge peak output current 0 8 A fPWM Externally applied PWM frequency 0 50 kHz VIN Logic level input voltage 0 VCC V TA Ambient temperature –40 85 °C (1) Power dissipation and thermal limits must be observed Thermal Information DRV8850 THERMAL METRIC (1) PWP RGY 24 PINS 24 PINS θJA Junction-to-ambient thermal resistance (2) 43.8 39.1 θJCtop Junction-to-case (top) thermal resistance (3) 24.6 41.1 θJB Junction-to-board thermal resistance (4) 22.7 15.0 0.7 0.6 (5) ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter (6) 22.5 14.9 θJCbot Junction-to-case (bottom) thermal resistance (7) 4.1 3.2 (1) (2) (3) (4) (5) (6) (7) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links :DRV8850 5 DRV8850 SLVSCC0A – NOVEMBER 2013 – REVISED JANUARY 2014 www.ti.com Electrical Characteristics TA = 25°C, over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VCC) IVCC VCC operating supply current, LDO regulator and driver enabled VCC = 4.2 V, nSLEEP = LDOEN = VCC IVCQ1 VCC sleep mode supply current VCC = 4.2 V, nSLEEP = LDOEN = 0 V, INXH = INXL = 0 V IVCQ2 VCC operating supply current, LDO regulator enabled, driver disabled (1) VCC = 4.2 V, nSLEEP = 0 V, LDOEN = VCC, INXH = INXL = 0 V IVCQ3 VCC operating supply current LDO VCC = 4.2 V, nSLEEP = VCC, LDOEN = 0 V voltage regulator disabled, driver enabled VUVLO VCC undervoltage lockout voltage VOVLO VCC overvoltage lockout voltage VIL Input low voltage VIH Input high voltage VHYS Input hysteresis IIL Input low current VIN = 0 IIH Input high current VIN = 3.3 V RPD Pulldown resistance 2.9 mA 1 40 μA 2.9 mA VCC rising 2 VCC falling 1.95 VCC rising 5.6 VCC falling 5.5 μA V V LOGIC-LEVEL INPUTS (LDOEN, IN1H, IN1L, IN2H, IN2L, nSLEEP) 0 0.5 × VCC 0.2 × VCC V VCC V 1 μA 50 μA 0.08 × VCC –1 V LDOEN 3.5 MΩ nSLEEP 400 kΩ INXH, INXL 200 kΩ IOUT / 2000 A VPROPI OUTPUT (VPROPI) IVPROPI VPROPI output current VCC = 4.2 V, resistor chosen to keep VPROPI ≤ (VCC – 1 V) / IOUT 500 mA ≤ IOUT ≤ 5 A RDS(ON) HS FET on resistance VCC = 4.2 V, IO = 2 A, TA = 25°C 35 mΩ LS FET on resistance VCC = 4.2 V, IO = 2 A, TA = 25°C 30 mΩ Off-state leakage current VOUT = 0 V H-BRIDGE FETS (OUT1, OUT2) IOFF –1 1 μA 0.84 V LDO REGULATOR (LDOOUT) VFB LDO feedback (reference) voltage 0.76 0.8 VDO LDO regulator dropout voltage ΔVLINE LDO line regulation VCC from 4.2 to 5.5 V, VOUT = 3.3 V –2.5 2.5 % ΔVLOAD LDO load regulation VOUT = 3.3 V, IOUT from 1 to 100 mA –2.5 2.5 % ICL LDO output current limit VCC = 4.2 V, VOUT = 3.3 V, TA ≥ 25°C 275 mA 9.5 A VCC = 4.2 V, IOUT = 100 mA, TA = 25°C 150 VCC = 4.2 V, IOUT = 100 mA, TA = 85°C 175 mV mV PROTECTION CIRCUITS IOCP Overcurrent protection trip level tOCP Overcurrent protection deglitch time 1 µs tRETRY Overcurrent retry time 4 ms tTSD Thermal shutdown temperature Die temperature (rising) tHYS Thermal shutdown hysteresis Temperature hysteresis (1) 6 VCC = 2.5 to 5.5 V 150 160 50 180 °C °C Does not include the current consumption from the feedback resistors. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links :DRV8850 DRV8850 www.ti.com SLVSCC0A – NOVEMBER 2013 – REVISED JANUARY 2014 Timing Requirements (1) TA = 25°C, VCC = 4.2 V, RL = 2 Ω PARAMETER tR, tF tDELAY Rise and fall time (measured at OUTx) TEST CONDITIONS UNIT 70 ns 0.7 µs RSR = 2.4 MΩ 70 µs 500 ns 750 ns 50 µs 400 ns RSR = 24 kΩ 2.6 µs RSR = 2.4 MΩ 110 µs RSR short to GND 400 ns RSR = 24 kΩ 2.6 µs RSR = 2.4 MΩ 110 µs RSR short to GND 400 ns RSR = 24 kΩ 2.6 µs RSR = 2.4 MΩ 110 µs RSR short to GND 600 ns RSR = 24 kΩ 3.9 µs RSR = 2.4 MΩ 165 µs Low-side slow decay LS OFF to HS ON Low-side slow decay HS OFF to LS ON High-side slow decay or fast decay HS OFF to LS ON High-side slow decay or fast decay LS OFF to HS ON (1) MAX RSR = 24 kΩ RSR short to GND tDEAD TYP RSR connected to GND Propagation delay RSR connected to GND (measured as time between RSR = 24 kΩ input edge to output RSR = 2.4 MΩ change) Dead time (measured as time OUTx FET is Hi-Z) MIN Rise and fall time measured from 10 to 90% VCC Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links :DRV8850 7 DRV8850 SLVSCC0A – NOVEMBER 2013 – REVISED JANUARY 2014 www.ti.com TYPICAL PERFORMANCE GRAPHS Iq vs VCC 2.8 2.8 TA = +85°C TA = +25°C 2.6 TA = +85°C TA = +25°C 2.6 2.4 2.4 2.2 2.2 Iq (mA) Iq (mA) Iq vs VCC 2.0 2.0 1.8 1.8 1.6 1.6 1.4 1.4 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VCC (V) 5.5 2.0 2.5 3.0 Figure 1. Quiescent Current With Motor Driver on and LDO On 2.5 5.0 5.5 C002 TA = +85°C TA = +25°C 2.0 34 Iq (µA) 32 Iq (µA) 4.5 Iq vs VCC TA = +85°C TA = +25°C 36 4.0 Figure 2. Quiescent Current With Motor Driver on and LDO Off Iq vs VCC 38 3.5 VCC (V) C001 30 28 26 1.5 1.0 0.5 24 22 0.0 2.0 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 5.5 Figure 3. Quiescent Current With Motor Driver off and LDO On 8 2.0 2.5 3.0 3.5 4.0 VCC (V) C003 4.5 5.0 5.5 C003 C004 Figure 4. Quiescent Current With Motor Driver off and LDO off, Sleep Current Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links :DRV8850 DRV8850 www.ti.com SLVSCC0A – NOVEMBER 2013 – REVISED JANUARY 2014 RDS(ON) vs VCC 70 70 60 60 50 50 RDS(ON) (m) RDS(ON) (m) RDS(ON) vs VCC 40 30 20 40 30 20 TA = +85°C TA = +25°C TA = ±40C 10 0 2.0 2.5 3.0 TA = +85°C TA = +25°C TA = ±40C 10 0 3.5 4.0 4.5 5.0 VCC 5.5 2.0 2.5 3.0 4.5 5.0 5.5 C005 C006 Figure 6. RDS(ON), HS – OUT2 RDS(ON) vs VCC RDS(ON) vs VCC 70 70 60 60 50 50 RDS(ON) (m) RDS(ON) (m) 4.0 VCC Figure 5. RDS(ON), HS – OUT1 40 30 20 40 30 20 TA = +85°C TA = +25°C TA = ±40C 10 0 2.0 2.5 3.0 TA = +85°C TA = +25°C TA = ±40C 10 0 3.5 4.0 4.5 5.0 VCC 5.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VCC C005 C007 Figure 7. RDS(ON), LS – OUT1 5.5 C005 C007 C008 Figure 8. RDS(ON), LS – OUT2 Error vs IOUT Error vs IOUT 0.2 Error (% from 25C, 10-mA load) 1.0 Error (% from 25C, 10-mA load) 3.5 C005 C011 0.5 0.0 ±0.5 ±1.0 ±1.5 ±2.0 ±2.5 ±3.0 0.00 TA = +85°C TA = +25°C TA = ±40C 0.02 0.04 0.06 0.08 IOUT (A) 0.10 0.0 ±0.2 ±0.4 ±0.6 ±0.8 ±1.0 ±1.2 0.00 0.02 0.04 0.06 0.08 IOUT (A) C005 C009 Figure 9. LDO Output, VCC = 3.5 V, LDOOUT = 3.3 V TA = +85°C TA = +25°C TA = ±40C 0.10 C005 C010 Figure 10. LDO Output, VCC = 4.2 V, LDOOUT = 3.3 V Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links :DRV8850 9 DRV8850 SLVSCC0A – NOVEMBER 2013 – REVISED JANUARY 2014 www.ti.com Error vs IOUT VPROPI vs IOUT 2.5 0.0 2.0 ±0.2 VPROPI (V) Error (% from 25C, 10-mA load) 0.2 ±0.4 ±0.6 ±0.8 ±1.0 0.00 1.0 OUT1, TA = +85°C OUT1, TA = +25°C 0.5 TA = +85°C TA = +25°C TA = ±40C 0.02 1.5 OUT1, TA = ±40C 0.0 0.04 0.06 0.08 0.10 IOUT (A) 0 1 2 3 IOUT (A) C005 C011 Figure 11. LDO Output, VCC = 5.5 V, LDOOUT = 3.3 V 4 5 C005 C012 Figure 12. VPROPI Output, VCC = 4.2 V, OUT1 overtemperature, 1 kΩ VPROPI vs IOUT 2.5 VPROPI (V) 2.0 1.5 1.0 0.5 OUT1, TA = +85°C OUT1, TA = +25°C OUT1, TA = ±40C 0.0 0 1 2 3 IOUT (A) 4 5 C005 C013 Figure 13. VPROPI Output, VCC = 4.2 V, OUT2 overtemperature, 1 kΩ 10 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links :DRV8850 DRV8850 www.ti.com SLVSCC0A – NOVEMBER 2013 – REVISED JANUARY 2014 Functional Description Power Supervisor The LDO regulator can be active independent of the nSLEEP pin. This independence allows a microcontroller, or other device, to be powered by the LDO voltage regulator, while retaining the ability to put the DRV8850 device into sleep mode. Because of this functionality, nSLEEP and LDOEN must both be brought logic low to minimize power consumption in sleep mode. If the LDO regulator remains active in sleep mode, a quiescent current of IVCQ2 (typically 50 µA plus current through the external feedback resistors) is drawn from the supply. Table 3 shows the operation mode logic for the DRV8850 device: Table 3. DRV8850 Device Operation Mode Logic (1) (1) nSLEEP LDOEN LDO Regulator Driver 0 0 Off Sleep 0 1 Active Sleep 1 0 Off Active 1 1 Active Active A state must be active for a minimum of 1 ms before a new state is commanded. Bridge Control A corresponding input pin controls the individual FETs in the DRV8850 device. Shoot-through (the condition when both HS and LS FETs are turned on at the same time) is not allowed; with this input condition, both the HS and LS FETs turn off. Table 4 shows the logic for the DRV8850 device: Table 4. DRV8850 Device Logic INxL INxH 0 0 OUTx Z 0 1 H 1 0 L 1 1 Z Current Sensing – VPROPI The VPROPI pin outputs an analog current that is proportional to the current flowing in the H-bridge. The output current is typically 1 / 2000 of the current in both high side FETs. VPROPI is derived from the current through either of the high side FETs. Because of this, VPROPI does not represent the H-bridge current when operating in a fast-decay mode or low-side slow-decay mode. VPROPI represents the H-bridge current under forward drive, reverse drive, and high-side slow decay. VPROPI output is delayed by roughly 2 µs after the high side FET is switched on and it has reached approximately VCC (including the deglitch on the HSon). Select the external resistor so that the voltage on VPROPI is less than (VCC – 1 V), so the resistor must be sized less than: 2000 x VCC 1 V / IOUT where IOUT is the maximum drive current to be monitored (1) The range of current that can be monitored is 500 mA to 5 A, assuming the external resistor meets the prior equation. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links :DRV8850 11 DRV8850 SLVSCC0A – NOVEMBER 2013 – REVISED JANUARY 2014 www.ti.com VCC VCC 4 4 1 OUT2 OUT1 2 1 Forward drive 2 Fast decay 3 Low-side slow decay 4 High-side slow decay 1 OUT2 OUT1 1 Reverse drive 2 Fast decay 3 Low-side slow decay 4 High-side slow decay 2 3 3 FORWARD REVERSE Figure 14. Forward and Reverse Operation When using an independent half-bridge as a high-side driver, VPROPI does not output a current measurement during slow decay. During typical operation, VPROPI represents the total current flowing to loads connected to OUT1 and OUT2. VPROPI is nonfunctional when implemented as a low-side driver. VCC VCC 1 1 OUT1 2 VCC Normal operation 2 Slow decay 1 Normal operation 2 Slow decay OUT1 2 1 High-side driver Low-side driver Figure 15. High-Side and Low-Side Drivers 12 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links :DRV8850 DRV8850 www.ti.com SLVSCC0A – NOVEMBER 2013 – REVISED JANUARY 2014 Slew-Rate Control The rise and fall times (tR and tF) of the outputs can be adjusted by the value of an external resistor connected from the SR pin to ground. The output slew rate is adjusted internally by the DRV8850 device by controlling the ramp rate of the driven FET gate. The typical voltage on the SR pin is 0.6 V driven internally. Changing the resistor value monotonically increases the slew rates from approximately 100 ns to 100 µs. Recommended values for the external resistor are from GND to 2.4 MΩ. If the SR pin is grounded then the slew rate is 100 ns. Dead Time The dead time (tDEAD) is measured as the time when OUTx is Hi-Z between turning off one of the H-bridge FETs and turning on the other. For example, the output is Hi-Z between turning off the high-side FET and turning on the low-side FET. When driving current out of the pin, the output is observed to fall to one diode drop below ground during dead time. When driving current into the pin, the output is observed to rise to one diode drop above VCC. The DRV8850 has an analog dead time of approximately 100 ns. In addition to this analog dead time, the output is Hi-Z when the FET gate voltage is less than the threshold voltage. The total dead time depends on the SR resistor setting because a portion of the FET gate ramp includes the observable dead time. Propagation Delay The propagation delay time (tDELAY) is measured as the time between an input edge to an output change. This time is composed of two parts: an input deglitcher and output slewing delay. The input deglitcher prevents noise on the input pins from affecting the output state. The output slew rate also contributes to the delay time. For the output to change state during typical operation, first one FET must be turned off. The FET gate is ramped down according to the SR resistor selection, and the observed propagation delay ends when the FET gate falls to less than the threshold voltage. INxH INxL High-side Gate Low-side Gate HS Slew Rate HS Slew Rate LS Slew Rate LS Slew Rate OUTx tDELAY tDEAD tR tDELAY tF tDEAD Figure 16. Low-Side Slow Decay Operation – Current Sourced from OUTx Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links :DRV8850 13 DRV8850 SLVSCC0A – NOVEMBER 2013 – REVISED JANUARY 2014 www.ti.com INxH INxL High-side Gate HS Slew Rate HS Slew Rate Low-side Gate LS Slew Rate LS Slew Rate OUTx tDELAY tDEAD tF tDELAY tR tDEAD Figure 17. High-Side Slow Decay or Fast Decay Operation – Current Sunk into OUTx Power Supplies and Input Pins An internal charge pump generates a voltage greater than VCC that is used to drive the internal N-channel power MOSFETs. The charge pump requires a capacitor between the VCP and VCC pins. TI recommends to bypass VCC to ground with 0.1 and 10-μF ceramic capacitors, placed as close as possible to the IC. Each input pin has a weak pulldown resistor to ground (see Electrical Characteristics for more details). The input pins should not be driven to more than 0.6 V without the VCC power supply removed. LDO Voltage Regulator An LDO regulator is integrated into the DRV8850 device. The LDO regulator is typically used to provide the supply voltage for a low-power microcontroller. For proper operation, bypass the LDOOUT pin to GND using a ceramic capacitor. The recommended value for this component is 2.2 μF. Two external resistors are used to set the LDO voltage (VLDO) by creating a voltage divider between LDOOUT and LDOFB. The LDO output voltage can be given by: VFB x 1 R1 / R 2 V VLDO where • • 14 R1 is located between LDOOUT and LDOFB R2 is between LDOFB and GND Submit Documentation Feedback (2) Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links :DRV8850 DRV8850 www.ti.com SLVSCC0A – NOVEMBER 2013 – REVISED JANUARY 2014 LDOOUT LDOOUT LDO regulator R1 2.2 µF LDOFB R2 Figure 18. LDO Regulator Schematic The output voltage is adjustable from 1.6 V to VCC – VLDO using external resistors. The LDOEN pin is used to enable or disable the LDO regulator; when disabled, the output is turned off and the LDO regulator enters a verylow-power state. When the LDO current load exceeds ICL, the LDO regulator behaves like a constant current source. The LDO output voltage drops significantly with currents greater than ICL. Protection Circuits The DRV8850 device is protected against undervoltage, overvoltage, overcurrent, and overtemperature events. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than tOCP, all FETs in the H-bridge are disabled. After approximately tRETRY, the bridge re-enables automatically. Overcurrent conditions on both high and low-side devices, that is, a short to ground, supply, or across the motor winding result in an overcurrent shutdown. Thermal Shutdown (TSD) If the die temperature exceeds tTSD, all FETs in the H-bridge are disabled. Once the die temperature has fallen below tTSD – tHYS, the H-bridge automatically re-enables. Undervoltage Lockout (UVLO) If at any time the voltage on the VCC pins falls to less than the undervoltage lockout threshold voltage, all circuitry in the device is disabled and internal logic resets. Operation resumes when VCC rises to greater than the UVLO threshold. Overvoltage Lockout (OVLO) If at any time the voltage on the VCC pins rises to more than VOVLO, the output FETs are disabled (outputs are high-Z). Operation resumes when VCC falls below the VOVLO. CAUTION VCC must remain less than the absolute maximum rating for the device, or damage to the device may occur. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links :DRV8850 15 DRV8850 SLVSCC0A – NOVEMBER 2013 – REVISED JANUARY 2014 www.ti.com Thermal Information Thermal Protection The DRV8850 device has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately tTSD, the device will be disabled until the temperature drops to a safe level. Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature. Power Dissipation Power dissipation in the DRV8850 device is the sum of the motor driver power dissipation and the LDO voltage regulator dissipation. The LDO dissipation is calculated simply by (VIN – VOUT) × IOUT. The power dissipation in the motor driver is dominated by the power dissipated in the output FET resistance, or RDS(ON). Power dissipation can be estimated by: LS _ R PTOT DS (ON ) HS _ RDS (ON ) x IOUT ( RMS ) 2 where • • • PTOT is the total power dissipation RDS(ON) is the resistance of each FET IOUT(RMS) is the RMS output current being driven (3) The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and heat sinking. Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. REVISION HISTORY Changes from Original (November 2013) to Revision A • 16 Page Removed product preview banner ........................................................................................................................................ 1 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links :DRV8850 PACKAGE OPTION ADDENDUM www.ti.com 2-Jan-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DRV8850RGYR ACTIVE VQFN RGY 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV8850 DRV8850RGYT ACTIVE VQFN RGY 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV8850 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Jan-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device DRV8850RGYR Package Package Pins Type Drawing VQFN RGY 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 3.8 B0 (mm) K0 (mm) P1 (mm) 5.8 1.2 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Jan-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8850RGYR VQFN RGY 24 3000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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