TI 74AC16472

 SCAS165A − JUNE 1990 − REVISED APRIL 1996
D Members of the Texas Instruments
D
D
D
D
D
D
54AC16472 . . . WD PACKAGE
74AC16472 . . . DL PACKAGE
(TOP VIEW)
Widebus  Family
3-State True Outputs
Flow-Through Architecture Optimizes
PCB Layout
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
EPIC  (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center Pin
Spacings
1OEAB
1LEAB
1A1
GND
1A2
1A3
VCC
1A4
1A5
1A6
GND
1A7
1A8
1A9
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2A9
2LEAB
2OEAB
description
The ’AC16472 are 18-bit registered transceivers
that contain two sets of D-type latches for
temporary storage of data flowing in either
direction. They can be used as two 9-bit
transceivers or one 18-bit transceiver. Separate
latch-enable (LEAB or LEBA) and output-enable
(OEAB or OEBA) inputs are provided for each
register to permit independent control in either
direction of data flow.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
1OEBA
1LEBA
1B1
GND
1B2
1B3
VCC
1B4
1B5
1B6
GND
1B7
1B8
1B9
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2B9
2LEBA
2OEBA
27
30
When OEAB and LEAB are both low, the A-to-B
28
29
latches are transparent; a subsequent low-to-high
transition of LEAB puts the A latches in the
storage mode. With OEAB low, the B outputs are active and reflect the data present at the output of the A latches.
Data flow from B to A is similar, but requires the use of the LEBA and OEBA inputs.
The 74AC16472 is packaged in TI’s shrink small-outline package (DL), which provides twice the I/O pin count
and functionality of standard small-outline packages in the same printed-circuit-board area.
The 54AC16472 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74AC16472 is characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
! "#$%&'( $#()(! (*#+&)#( $%++'( )! #* ,%-.$)#( ")'/ +#"%$! $#(*#+& #
!,'$*$)#(! ,'+ ' '+&! #* '0)! (!+%&'(! !)(")+" 1)++)(2/
+#"%$#( ,+#$'!!(3 "#'! (# ('$'!!)+.2 ($.%"' '!(3 #* )..
,)+)&''+!/
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1
SCAS165A − JUNE 1990 − REVISED APRIL 1996
FUNCTION TABLE†
INPUTS
LEAB
OEAB
A
OUTPUT
B
X
H
X
Z
H
L
X
L
L
H
B0‡
H
L
L
L
L
† A-to-B data flow is shown: B-to-A flow is
similar but uses LEBA and OEBA.
‡ Output level before the indicated
steady-state input conditions were
established
logic symbol§
1LEAB
2
1
1OEAB
55
1LEBA
56
1OEBA
27
2LEAB
28
2OEAB
2LEBA
30
29
2OEBA
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
3
5
C1
EN2
C3
EN4
C5
EN6
C7
EN8
4
1
3D
1D
1
2
54
52
6
51
8
49
9
48
10
47
12
45
13
44
14
43
15
42
16
8
1
7D
5D
1
6
41
17
40
19
38
20
37
21
36
23
34
24
33
26
31
§ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
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•
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1B9
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2B9
SCAS165A − JUNE 1990 − REVISED APRIL 1996
logic diagram (positive logic)
1LEBA
1OEBA
1OEAB
1LEAB
1A1
55
56
1
2
C1
3
1D
54
1B1
C1
1D
To Eight Other Channels
2LEBA
2OEBA
2OEAB
2LEAB
2A1
30
29
28
27
C1
15
1D
42
2B1
C1
1D
To Eight Other Channels
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3
SCAS165A − JUNE 1990 − REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±450 mA
Maximum power package dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . 1.4 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54AC16472
VCC
VIH
Supply voltage
VCC = 3 V
VCC = 4.5 V
High-level input voltage
VCC = 5.5 V
VCC = 3 V
VIL
VI
VO
IOH
IOL
∆t/∆v
MIN
NOM
MAX
3
5
5.5
3
5
5.5
3.15
3.85
3.85
0
0
VCC = 3 V
VCC = 4.5 V
0.9
0.9
1.35
1.35
1.65
1.65
VCC
VCC
0
0
VCC
VCC
−4
−4
−24
−24
−24
−24
12
12
VCC = 4.5 V
VCC = 5.5 V
24
24
24
24
Input transition rise or fall rate
•
V
V
V
V
mA
mA
0
10
0
10
ns/V
−55
125
−40
85
°C
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UNIT
V
VCC = 5.5 V
VCC = 3 V
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
4
MAX
3.15
Output voltage
Low-level output current
NOM
2.1
Input voltage
High-level output current
MIN
2.1
VCC = 4.5 V
VCC = 5.5 V
Low-level input voltage
74AC16472
SCAS165A − JUNE 1990 − REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −50 µA
IOH = −4 mA
VOH
ICC
Ci
TA = 25°C
TYP
MAX
54AC16472
MIN
MAX
74AC16472
MIN
3V
2.9
2.9
2.9
4.5 V
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
3V
2.58
2.48
2.48
3.94
3.8
3.8
IOL = −24 mA
5.5 V
4.94
4.8
4.8
IOH = −75 mA†
5.5 V
IOL = 12 mA
IOL = 24 mA
II
IOZ‡
MIN
4.5 V
IOL = 50 µA
VOL
VCC
3.85
MAX
UNIT
V
3.85
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
3V
0.36
0.44
0.44
4.5 V
0.36
0.44
0.44
5.5 V
0.36
0.44
0.44
1.65
1.65
V
IOL = 75 mA†
VI = VCC or GND
5.5 V
5.5 V
±0.1
±1
±1
µA
A or B ports
VO = VCC or GND
VI = VCC or GND,
5.5 V
±0.5
±5
±5
µA
8
80
80
µA
Control inputs
VI = VCC or GND
VO = VCC or GND
Control inputs
IO = 0
5.5 V
5V
3
pF
Cio
A or B ports
5V
11.5
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
pF
timing requirements over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
54AC16472
MIN
MAX
74AC16472
MIN
MAX
UNIT
tw
tsu
Pulse duration, LEAB or LEBA low
4
4
4
ns
Setup time, data before LEAB or LEBA ↑
0.5
0.5
0.5
ns
th
Hold time, data after LEAB or LEBA ↑
3.5
3.5
3.5
ns
timing requirements over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
tsu
Pulse duration, LEAB or LEBA low
th
54AC16472
MIN
MAX
74AC16472
MIN
MAX
UNIT
4
4
4
ns
Setup time, data before LEAB or LEBA ↑
0.5
0.5
0.5
ns
Hold time, data after LEAB or LEBA ↑
2.5
2.5
2.5
ns
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5
SCAS165A − JUNE 1990 − REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPLH
tPHL
LEBA or LEAB
A or B
tPZH
tPZL
OEBA or OEAB
A or B
tPHZ
tPLZ
OEBA or OEAB
A or B
MIN
TA = 25°C
TYP
MAX
54AC16472
74AC16472
MIN
MAX
MIN
MAX
3.5
8
12.5
3.5
14.2
3.5
14.2
3.9
8.4
12.8
3.9
13.9
3.9
13.9
4.8
10.3
15.6
4.8
17.9
4.8
17.9
4.7
9.7
14.7
4.7
16.3
4.7
16.3
3.9
8.9
14
3.9
15.9
3.9
15.9
5
11.2
17.6
5
19.7
5
19.7
4.4
7
9.4
4.4
10
4.4
10
4
6.4
8.7
4
9.4
4
9.4
UNIT
ns
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPLH
tPHL
LEBA or LEAB
A or B
tPZH
tPZL
OEBA or OEAB
A or B
tPHZ
tPLZ
OEBA or OEAB
A or B
MIN
TA = 25°C
TYP
MAX
54AC16472
74AC16472
MIN
MAX
MIN
MAX
2.9
5.6
8.4
2.9
9.5
2.9
9.5
3.1
6
8.7
3.1
9.6
3.1
9.6
3.9
7.3
10.3
3.9
11.7
3.9
11.7
3.7
6.9
9.7
3.7
10.9
3.7
10.9
3.1
6.2
8.9
3.1
10.2
3.1
10.2
3.9
7.3
10.4
3.9
11.6
3.9
11.6
4.3
6.2
8.1
4.3
8.6
4.3
8.6
3.8
5.7
7.4
3.8
8
3.8
8
UNIT
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Outputs enabled
Power dissipation capacitance per transceiver
Outputs disabled
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CL = 50 pF,
f = 1 MHz
TYP
59
6
UNIT
pF
SCAS165A − JUNE 1990 − REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
500 Ω
LOAD CIRCUIT
Timing Input
0V
tw
50%
th
tsu
VCC
Input
VCC
50%
50%
VCC
50%
50%
Data Input
0V
0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
VCC
Input
50%
50%
0V
tPHL
tPLH
In-Phase
Output
50% VCC
Out-of-Phase
Output
50% VCC
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
50% VCC
VOL
tPLH
tPHL
VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOH
50% VCC
VOL
50%
50%
50% VCC
20% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
[ VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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7
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