SN65HVD1040A-Q1 www.ti.com....................................................................................................................................................................................................... SLLS889 – JUNE 2008 EMC-OPTIMIZED HIGH SPEED CAN TRANSCEIVER FEATURES APPLICATIONS • • • • • 1 • • • • • • • • Qualified for Automotive Applications Improved Drop-In Replacement for TJA1040 Meets or Exceeds the Requirements of ISO 11898-5 GIFT/ICT Compliant ESD Protection up to ±12 kV (Human-Body Model) on Bus Pins Low-Current Standby Mode With Bus Wake-Up, <12 µA Max High Electromagnetic Compliance (EMC) Bus-Fault Protection of –27 V to 40 V Dominant Time-Out Function Thermal Shutdown Protection Power-Up/Down Glitch-Free Bus Inputs and Outputs – High Input Impedance With Low VCC – Monotonic Outputs During Power Cycling GMW3122 Dual-Wire CAN Physical Layer SAE J2284 High-Speed CAN for Automotive Applications SAE J1939 Standard Data Bus Interface ISO 11783 Standard Data Bus Interface NMEA 2000 Standard Data Bus Interface • • • DESCRIPTION The SN65HVD1040A meets or exceeds the specifications of the ISO 11898 standard for use in applications employing a Controller Area Network (CAN). The device is qualified for use in automotive applications. As a CAN transceiver, this device provides differential transmit capability to the bus and differential receive capability to a CAN controller at signaling rates up to 1 megabit per second (Mbps) (1). (1) The signaling rate of a line is the number of voltage transitions that are made per second, expressed in the units bps (bits per second). FUNCTIONAL BLOCK DIAGRAM VCC VCC Dominant Time-Out TXD 1 VCC Input Logic Temperature Protection 3 VCC/2 5 SPLIT Driver 7 CANH STB RXD 4 6 Standby Mode 8 Output Logic CANL MUX Wake-Up Filter Bus Monitor 2 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated SN65HVD1040A-Q1 SLLS889 – JUNE 2008....................................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) Designed for operation in especially harsh environments, the SN65HVD1040A features cross-wire, over-voltage, and loss of ground protection from –27 V to 40 V, over-temperature protection, a –12-V to 12-V common-mode range, and withstands voltage transients according to ISO 7637. STB (pin 8) provides two different modes of operation: high-speed mode or low-current standby mode. The high-speed mode of operation is selected by connecting STB (pin 8) to ground. If a high logic level is applied to the STB pin of the SN65HVD1040A, the device enters a low-current standby mode, while the receiver remains active in a low-power bus-monitor standby mode. In the low-current standby mode, a dominant bit greater than 5 µs on the bus is passed by the bus-monitor circuit to the receiver output. The local protocol controller may then reactivate the device when it needs to transmit to the bus. A dominant time-out circuit in the SN65HVD1040A prevents the driver from blocking network communication with a hardware or software failure. The time-out circuit is triggered by a falling edge on TXD (pin 1). If no rising edge is seen before the time-out constant of the circuit expires, the driver is disabled. The circuit is then reset by the next rising edge on TXD. SPLIT (pin 5) is available as a VCC/2 common-mode bus voltage bias for a split-termination network (see application information). D PACKAGE (TOP VIEW) TXD 1 8 STB GND 2 7 CANH VCC 3 6 CANL RXD 4 5 SPLIT ORDERING INFORMATION (1) (1) (2) 2 PART NUMBER PACKAGE (2) MARKED AS ORDERING NUMBER SN65HVD1040A-Q1 SOIC-8 1040AQ SN65HVD1040AQDRQ1 (reel) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated SN65HVD1040A-Q1 www.ti.com....................................................................................................................................................................................................... SLLS889 – JUNE 2008 ABSOLUTE MAXIMUM RATINGS (1) (2) VALUE VCC IO Supply voltage range –0.3 V to 7 V Voltage range at bus terminals (CANH, CANL, SPLIT) –27 V to 40 V Receiver output current 20 mA VI Voltage input range, ISO 7637 transient pulse VI Voltage input range (TXD, STB) TJ Junction temperature range (1) (2) (3) (3) (CANH, CANL) –150 V to 100 V –0.5 V to 6 V –40°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with ISO 7637 test pulses 1, 2, 3a, 3b per IBEE system level test (Pulse 1 = –100 V, Pulse 2 = 100 V, Pulse 3a = –150 V, Pulse 3b = 100 V). If dc may be coupled with ac transients, externally protect the bus pins within the absolute maximum voltage range at any bus terminal. This device has been tested with dc bus shorts to +40 V with leading common-mode chokes. If common-mode chokes are used in the system and the bus lines may be shorted to dc, ensure that the choke type and value in combination with the node termination and shorting voltage either will not create inductive flyback outside of voltage maximum specification or use an external transient-suppression circuit to protect the transceiver from the inductive transients. ELECTROSTATIC DISCHARGE PROTECTION PARAMETER TEST CONDITIONS CANH and CANL Human-Body Model (2) Electrostatic discharge (1) Charged-Device Model (5) VALUE (3) ±12 kV SPLIT (4) ±10 kV All pins ±4 kV All pins ±1.5 kV Machine Model (6) (1) (2) (3) (4) (5) (6) ±200 V All typical values at 25°C. Tested in accordance JEDEC Standard 22, Test Method A114E. Test method based upon JEDEC Standard 22 Test Method A114E, CANH and CANL bus pins stressed with respect to each other and GND. Test method based upon JEDEC Standard 22 Test Method A114E, SPLIT pin stressed with respect to GND. Tested in accordance JEDEC Standard 22, Test Method C101C. Tested in accordance JEDEC Standard 22, Test Method A115A. RECOMMENDED OPERATING CONDITIONS VCC Supply voltage VI or VIC Voltage at any bus terminal (separately or common mode) VIH High-level input voltage TXD, STB VIL Low-level input voltage TXD, STB VID Differential input voltage IOH High-level output current IOL Low-level output current TA Operating free-air temperature range Copyright © 2008, Texas Instruments Incorporated Driver MIN MAX UNIT 4.75 5.25 V –12 12 V 2 5.25 V 0 0.8 V –6 6 V –70 Receiver mA –2 Driver 70 Receiver 2 See Thermal Characteristics table –40 125 Submit Documentation Feedback mA °C 3 SN65HVD1040A-Q1 SLLS889 – JUNE 2008....................................................................................................................................................................................................... www.ti.com SUPPLY CURRENT over recommended operating conditions including operating free-air temperature range (unless otherwise noted) PARAMETER ICC (1) 5-V supply current TEST CONDITIONS Standby mode STB at VCC, VI = VCC Dominant VI = 0 V, 60-Ω load, STB at 0 V Recessive VI = VCC, No load, STB at 0 V MIN TYP (1) MAX 6 12 50 70 6 10 UNIT µA mA All typical values are at 25°C with a 5-V supply. DEVICE SWITCHING CHARACTERISTICS over recommended operating conditions, TA = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS td(LOOP1) Total loop delay, driver input to receiver output, recessive to dominant td(LOOP2) Total loop delay, driver input to receiver output, dominant to recessive STB at 0 V, See Figure 9 MIN MAX UNIT 90 230 ns 90 230 ns DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions, TA = –40°C to 125°C(unless otherwise noted) PARAMETER TEST CONDITIONS CANH VI = 0 V, STB at 0 V, RL = 60 Ω, See Figure 1 and Figure 2 VO(D) Bus output voltage (dominant) VO(R) Bus output voltage (recessive) VI = 3 V, STB at 0 V, RL = 60 Ω, See Figure 1 and Figure 2 VO Bus output voltage (standby mode) STB at Vcc, RL = 60 Ω, See Figure 1 and Figure 2 VOD(D) VOD(R) CANL Differential output voltage (dominant) Differential output voltage (recessive) MIN TYP (1) MAX 2.9 3.4 4.5 0.8 2 1.75 2.5 UNIT V 3 V –0.1 0.1 V VI = 0 V, RL = 60 Ω, STB at 0 V, See Figure 1, Figure 2, and Figure 3 1.5 3 VI = 0 V, RL = 45 Ω, STB at 0 V, See Figure 1, Figure 2, and Figure 3 1.4 3 –0.012 0.012 –0.5 0.05 V VI = 3 V, STB at 0 V, RL = 60 Ω, See Figure 1 and Figure 2 VI = 3 V, STB at 0 V, No load V VSYM Output symmetry (dominant or recessive) (VO(CANH) + VO(CANL)) STB at 0 V, RL = 60 Ω, See Figure 13 VOC(ss) Steady-state common-mode output voltage STB at 0 V, RL = 60 Ω, See Figure 8 ΔVOC(ss) Change in steady-state common-mode output voltage STB at 0 V, RL = 60 Ω, See Figure 8 IIH High-level input current, TXD input VI at VCC –2 2 µA IIL Low-level input current, TXD input VI at 0 V –50 –10 µA IO(off) Power-off TXD output current VCC at 0 V, TXD at 5 V 1 µA VCANH = –12 V, CANL open, See Figure 11 IOS(ss) Short-circuit steady-state output current (1) 4 Output capacitance VCC 1.1 VCC V 2 2.5 3 V 30 –120 VCANH = 12 V, CANL open, See Figure 11 VCANL = –12 V, CANH open, See Figure 11 VCANL = 12 V, CANH open, See Figure 11 CO 0.9 VCC mV –85 0.4 1 mA –1 –0.6 75 120 See receiver input capacitance All typical values are at 25°C with a 5-V supply. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated SN65HVD1040A-Q1 www.ti.com....................................................................................................................................................................................................... SLLS889 – JUNE 2008 DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions, TA = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tPLH Propagation delay time, low-to-high level output STB at 0 V, See Figure 4 25 65 120 ns tPHL Propagation delay time, high-to-low level output STB at 0 V, See Figure 4 25 45 120 ns tr Differential output signal rise time STB at 0 V, See Figure 4 25 tf Differential output signal fall time STB at 0 V, See Figure 4 45 ten Enable time from standby mode to dominant See Figure 7 t(dom) (1) (2) Dominant time out (2) ↓VI, See Figure 10 300 450 ns ns 10 µs 700 µs All typical values are at 25°C with a 5-V supply. The TXD dominant time out (t(dom)) disables the driver of the transceiver once the TXD has been dominant longer than t(dom), which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the t(dom) minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ t(dom) = 11 bits / 300 µs = 37 kbps RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions, TA = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going input threshold voltage, high-speed mode STB at 0 V, See Table 1 VIT– Negative-going input threshold voltage, high-speed mode STB at 0 V, See Table 1 Vhys Hysteresis voltage (VIT+ – VIT–) VIT Input threshold voltage, standby mode STB at VCC VOH High-level output voltage IO = –2 mA, See Figure 6 VOL Low-level output voltage IO = 2 mA, See Figure 6 II(off) Power-off bus input current IO(off) MIN TYP (1) MAX UNIT 800 900 mV 500 650 mV 100 125 mV 500 4 1150 4.6 V 0.4 V CANH = CANL = 5 V, VCC at 0 V, TXD at 0 V 3 µA Power-off RXD leakage current VCC at 0 V, RXD at 5 V 20 µA CI Input capacitance to ground (CANH or CANL) TXD at 3 V, VI = 0.4 sin (4E6πt) + 2.5 V CID Differential input capacitance TXD at 3 V, VI = 0.4 sin (4E6πt) RID Differential input resistance TXD at 3 V, STB at 0 V 30 RIN Input resistance (CANH or CANL) TXD at 3 V, STB at 0 V 15 RI(m) Input resistance matching [1 – (RIN (CANH) / RIN (CANL))] × 100% V(CANH) = V(CANL) –3 (1) 0.2 mV 13 pF 6 pF 80 kΩ 30 40 kΩ 0 3 % All typical values are at 25°C with a 5-V supply. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 5 SN65HVD1040A-Q1 SLLS889 – JUNE 2008....................................................................................................................................................................................................... www.ti.com RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions, TA = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tPLH Propagation delay time, low-to-high-level output STB at 0 V , See Figure 6 60 90 130 ns tPHL Propagation delay time, high-to-low-level output STB at 0 V , See Figure 6 45 70 130 ns tr Output signal rise time STB at 0 V , See Figure 6 8 tf Output signal fall time STB at 0 V , See Figure 6 8 tBUS Dominant time required on bus for wake-up from standby STB at VCC, See Figure 12 (1) ns ns 1.5 µs 5 All typical values are at 25°C with a 5-V supply. STB PIN CHARACTERISTICS over recommended operating conditions, TA = –40°C to 125°C (unless otherwise noted) MIN MAX IIH High-level input current PARAMETER STB at VCC TEST CONDITIONS –10 0 UNIT µA IIL Low-level input current STB at 0 V –10 0 µA SPLIT PIN CHARACTERISTICS over recommended operating conditions, TA = –40°C to 125°C (unless otherwise noted) PARAMETER VO Output voltage –500 µA < IO < 500 µA IO(stb) Leakage current, standby mode STB at 2 V, –12 V ≤ VO ≤ 12 V (1) MIN TYP (1) MAX 0.3 VCC 0.5 VCC 0.7 VCC V 5 µA TEST CONDITIONS –5 UNIT All typical values are at 25°C with a 5-V supply. THERMAL CHARACTERISTICS over recommended operating conditions, TA = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (2) 211 High-K thermal resistance (2) 131 Low-K thermal resistance MAX UNIT θJA Junction-to-air thermal resistance (1) θJB Junction-to-board thermal resistance 53 °C/W θJC Junction-to-case thermal resistance 79 °C/W PD Average power dissipation Thermal shutdown temperature (1) (2) 6 VCC = 5 V, TJ = 27°C, RL = 60 Ω, STB at 0 V, Input to TXD at 500 kHz, 50% duty cycle square wave, CL at RXD = 15 pF °C/W 112 mW VCC = 5.5 V, TJ = 130°C, RL = 45 Ω, STB at 0 V, Input to TXD at 500 kHz, 50% duty cycle square wave, CL at RXD = 15 pF 170 185 °C The junction temperature (TJ) is calculated using the following TJ = TA + (PD × θJA). Tested in accordance with the Low-K (EIA/JESD51-3) or High-K (EIA/JESD51-7) thermal metric definitions for leaded surface-mount packages. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated SN65HVD1040A-Q1 www.ti.com....................................................................................................................................................................................................... SLLS889 – JUNE 2008 FUNCTION TABLES DRIVER (1) INPUTS (1) OUTPUTS BUS STATE TXD STB CANH CANL L L H L Dominant H L Z Z Recessive Open L Z Z Recessive X H or Open Y Y Recessive H = high level, L = low level, X = irrelevant, ? = indeterminate, Z = high impendance RECEIVER (1) DIFFERENTIAL INPUTS VID = V(CANH) – V(CANL) (1) STB OUTPUT RXD BUS STATE VID ≥ 0.9 V L L Dominant VID ≥ 1.15 V H or Open L Dominant 0.5 V < VID < 0.9 V X ? ? VID ≤ 0.5 V X H Recessive Open X H Recessive H = high level, L = low level, X = irrelevant, ? = indeterminate, Z = high impendance Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 7 SN65HVD1040A-Q1 SLLS889 – JUNE 2008....................................................................................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION IO(CANH) VO (CANH) TXD II VOD RL VO(CANH) + VO(CANL) 2 VI STB I I(S) VOC I O(CANL) + VI(S) _ V O(CANL) Figure 1. Driver Voltage, Current, and Test Definition Dominant 3.5 V Recessive VO(CANH) 2.5 V VO(CANL) 1.5 V Figure 2. Bus Logic-State Voltage Definitions CANH 0V TXD VOD 330 W ±1% RL + _ STB CANL –2 V £ VTEST £ 7 V 330 W ±1% Figure 3. Driver VOD Test Circuit CANH VCC VI TXD RL = 60 W ±1% VI VCC/2 0V VO tPLH CL = 100 pF VO STB VCC/2 tPHL 0.9 V 10% CANL tr VO(D) 90% tf 0.5 V VO(R) Figure 4. Driver Test Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated SN65HVD1040A-Q1 www.ti.com....................................................................................................................................................................................................... SLLS889 – JUNE 2008 PARAMETER MEASUREMENT INFORMATION (continued) CANH RXD VI (CANH) IO VID V + VI (CANL) VIC = I (CANH) 2 VO CANL VI (CANL) Figure 5. Receiver Voltage and Current Definitions 3.5 V CANH 2V VI RXD VI 1.5 V IO 1.5 V tPLH CANL (See Note A) STB 2.4 V CL = 15 pF ±20% (See Note B) VO VO tPHL 0.25 VCC 90% VOH 0.75 VCC 10% VOL tf tr A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes instrumentation and fixture capacitance within ±20%. Figure 6. Receiver Test Circuit and Voltage Waveforms Table 1. Differential Input Voltage Threshold Test INPUT OUTPUT VCANH VCANL |VID| –11.1 V –12 V 900 mV L R 12 V 11.1 V 900 mV L –6 V –12 V 6V L 12 V 6V 6V L –11.5 V –12 V 500 mV H 12 V 11.5 V 500 mV H –12 V –6 V 6V H 6V 12 V 6V H Open Open X H Copyright © 2008, Texas Instruments Incorporated VOL VOH Submit Documentation Feedback 9 SN65HVD1040A-Q1 SLLS889 – JUNE 2008....................................................................................................................................................................................................... www.ti.com DUT CANH TXD 0V CL(A) 60 W ±1% 0.5 VCC 0V CANL STB VI VCC VI(B) VOH 0.5 VCC VO RXD VOL ten + VO 15 pF ± 20% _ A. CL = 100 pF and includes instrumentation and fixture capacitance within ±20%. B. All VI input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle. Figure 7. ten Test Circuit and Waveforms CANH TXD VI RL CANL STB VOC = VO(CANL) VO(CANH) + VO(CANL) 2 VOC(SS) VOC VO(CANH) NOTE: All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle. Figure 8. Common-Mode Output Voltage Test and Waveforms DUT VCC CANH VI (B) TXD CL (A) 60 W ±1% TXD Input 0.5 VCC 0V tloop1 tloop2 VOH CANL STB RXD Output 0.5 VCC 0.5 VCC VOL RXD + VO _ 15 pF ±20% A. CL = 100 pF and includes instrumentation and fixture capacitance within ±20%. B. All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle. Figure 9. t(LOOP) Test Circuit and Waveforms 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated SN65HVD1040A-Q1 www.ti.com....................................................................................................................................................................................................... SLLS889 – JUNE 2008 CANH VCC VI TXD VI RL = 60 W ±1% CL (B) 0V VOD VOD(D) (A) VOD STB 900 mV 500 mV CANL 0V tdom A. All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 500 Hz, 50% duty cycle. B. CL = 100 pF includes instrumentation and fixture capacitance within ±20%. Figure 10. Dominant Time-Out Test Circuit and Waveforms | IOS(SS) | IOS 200 µs CANH TXD 0V 0 V or V CC 12 V STB CANL VIN -12 V or 12 V Vin 0V or 0V 10 µs Vin -12 V Figure 11. Driver Short-Circuit Current Test and Waveforms CANH 3.5 V VCC STB RXD VI (see Note A) IO CL (see Note B) CANL 1.5 V VI 2.65 V 0.7 µs tBUS 1.5 V VOH VO VO 400 mV VOL A. For VI bit width ≤ 0.7 µs, VO = VOH. For VI bit width ≥ 5 µs, VO = VOL. VI input pulses are supplied from a generator with the following characteristics: tr/tf < 6 ns. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 12. tBUS Test Circuit and Waveforms Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 11 SN65HVD1040A-Q1 SLLS889 – JUNE 2008....................................................................................................................................................................................................... www.ti.com CANH TXD RL VI VSYM = VO(CANH) + VO(CANL) STB CANL VO(CANL) A. VO(CANH) All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr/tf ≤ 6 ns, pulse repetition rate (PRR) = 250 kHz, 50% duty cycle. Figure 13. Driver Output Symmetry Test Circuit 12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated SN65HVD1040A-Q1 www.ti.com....................................................................................................................................................................................................... SLLS889 – JUNE 2008 Equivalent Input and Output Schematic Diagrams TXD Input RXD Output VCC VCC 15 W 4.3 kW Output Input 6V 6V CANH Input CANL Input VCC VCC 10 kW 10 kW 20 kW 20 kW Input Input 10 kW 40 V 10 kW 40 V STB Input CANH and CANL Outputs VCC VCC CANH 4.3 kW CANL Input 40 V 6V 40 V SPLIT Output VCC 2 kW Output 2 kW 6V Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 13 SN65HVD1040A-Q1 SLLS889 – JUNE 2008....................................................................................................................................................................................................... www.ti.com APPLICATION INFORMATION VBATTERY VSUP VCC Vreg (e.g., TPSxxxx) VCC VCC 3 STB Port x CANH 7 8 SN65HVD1040A CAN Transceiver MCU (e.g., TMS470) SPLIT 5 RXD RXD TXD TXD 4 1 6 2 CANL GND Figure 14. Typical Application Using Split Termination for Stabilization VCC SN65HVD1040A 3 7 VSPLIT = ½VCC in normal mode, floating in other modes 5 6 CANH SPLIT CANL 2 GND Figure 15. Split Pin Stabilization Circuitry and Application 14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 23-Jun-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing SN65HVD1040AQDRQ1 ACTIVE SOIC D Pins Package Eco Plan (2) Qty 8 2500 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 31-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65HVD1040AQDRQ1 Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 31-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65HVD1040AQDRQ1 SOIC D 8 2500 346.0 346.0 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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