U6264B Standard 8K x 8 SRAM Features Description ! 8192 x 8 bit static CMOS RAM ! 70 ns Access Times ! Common data inputs and The U6264B is a static RAM manufactured using a CMOS process technology with the following operating modes: - Read - Standby - Write - Data Retention The memory array is based on a 6-transistor cell. The circuit is activated by the rising edge of E2 (at E1 = L), or the falling edge of E1 (at E2 = H). The address and control inputs open simultaneously. According to the information of W and G, the data inputs, or outputs, are active. In a Read cycle, the data outputs are activated by the falling edge of G, afterwards the data word read will be available at the outputs DQ0 DQ7. After the address change, the data outputs go High-Z until the new read information is available. The data outputs have no preferred state. If the memory is driven by CMOS levels in the active state, and if there is no change of the outputs ! Three-state outputs ! Typ. operating supply current 70 ns: 10 mA ! Standby current: < 2 µA at Ta ≤ 70 °C ! Data retention current at 2 V: < 1 µA at Ta ≤ 70 °C ! TTL/CMOS-compatible ! Automatic reduction of power ! ! ! ! ! ! dissipation in long Read or Write cycles Power supply voltage 5 V Operating temperature ranges: 0 to 70 °C -40 to 85 °C -40 to 125 °C QS 9000 Quality Standard ESD protection > 2000 V (MIL STD 883C M3015.7) Latch-up immunity > 100 mA Packages: PDIP28 (600 mil) SOP28 (330 mil) Pin Configuration Pin Description Signal Name Signal Description A0 - A12 Address Inputs DQ0 - DQ7 Data In/Out E1 Chip Enable 1 G (OE) E2 Chip Enable 2 A10 G Output Enable DQ7 W Write Enable VCC Power Supply Voltage VSS Ground n.c. not connected n.c. 1 28 VCC A12 2 27 W (WE) A7 3 26 E2 (CE2) A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 A2 8 PDIP 22 SOP 21 A1 9 20 E1 (CE1) A0 10 19 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 VSS 14 15 DQ3 Top View April 20, 2004 address, data input and control signals W or G, the operating current (at IO = 0 mA) drops to the value of the operating current in the Standby mode. The Read cycle is finished by the falling edge of E2 or W, or by the rising edge of E1, respectively. Data retention is guaranteed down to 2 V. With the exception of E2, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required. This gate circuit allows to achieve low power standby requirements by activation with TTL-levels too. If the circuit is inactivated by E2 = L, the standby current (TTL) drops to 150 µA typ. 1 U6264B A3 A10 Memory Cell Array 256 Rows x 256 Columns DQ0 Sense Amplifier/ Write Control Logic Address Change Detector E2 E1 Clock Generator DQ1 Common Data I/O A2 Row Decoder A1 Column Decoder A0 Row Address Inputs A4 A5 A6 A7 A8 A9 A11 A12 Column Address Inputs Block Diagram DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCC 1 VSS W G Truth Table Operating Mode E1 E2 W G DQ0 - DQ7 * L * * High-Z H * * * High-Z Internal Read L H H H High-Z Read L H H L Data Outputs Low-Z Write L H L * Data Inputs High-Z Standby/not selected * H or L 2 April 20, 2004 U6264B Characteristics All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of V I, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times, in which cases transition is measured ± 200 mV from steady-state voltage. Absolute Maximum Ratings a Symbol Min. Max. Unit VCC -0.3 7 V Input Voltage VI -0.3 VCC + 0.5 b V Output Voltage VO -0.3 VCC + 0.5 b V Power Dissipation PD - 1 W Power Supply Voltage Operating Temperature C-Type K-Type A-Type Ta 0 -40 -40 70 85 125 °C °C °C Storage Temperature C/K-Type A-Type Tstg -55 -65 125 150 °C °C 100 mA Output Short-Circuit Current at VCC = 5 V and VO = 0 V c a b c Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Maximum voltage is 7 V Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s. Recommended Operating Conditions d | IOS | Symbol Conditions Min. Max. Unit 5.5 V Power Supply Voltage VCC 4.5 Data Retention Voltage VCC(DR) 2.0 Input Low Voltage d VIL -0.3 0.8 V Input High Voltage VIH 2.2 VCC + 0.3 V -2 V at Pulse Width 10 ns April 20, 2004 3 V U6264B Electrical Characteristics Symbol Conditions Supply Current - Operating Mode ICC(OP) VCC VIL VIH tcW = 5.5 V = 0.8 V = 2.2 V = 70 ns Supply Current - Standby Mode (CMOS level) ICC(SB) VCC VE1 = VE2 or VE2 C-Type K-Type A-Type = 5.5 V = VCC - 0.2 V = 0.2 V Supply Current - Standby Mode (TTL level) ICC(SB)1 VCC VE1 = VE2 or VE2 = 5.5 V = 2.2 V = 0.8 V Supply Current - Data Retention Mode ICC(DR) VCC(DR) VE1 = VE2 or VE2 C-Type K-Type A-Type = 2V = VCC(DR) - 0.2 V = 0.2 V VCC IOH VCC IOL = 4.5 V = -1.0 mA = 4.5 V = 3.2 mA VCC VOH VCC VOL = = = = VCC VIH C/K-Type A-Type = 5.5 V = 5.5 V VCC VIL C/K-Type A-Type = 5.5 V = 0V VCC VOH C/K-Type A-Type = 5.5 V = 5.5 V VCC VOL C/K-Type A-Type = 5.5 V = 0V Output High Voltage VOH Output Low Voltage VOL Output High Current IOH Output Low Current IOL 4.5 V 2.4 V 4.5 V 0.4 V Min. Max. Unit 55 mA 2 5 100 µA µA µA 3 mA 1 3 50 µA µA µA 2.4 V 0.4 V -1 mA 3.2 mA Input Leakage Current High Low Output Leakage Current High at Three-State Outputs Low at Three-State Outputs IIH IIL IOHZ IOLZ 4 - 1 2 µA µA -1 -2 - µA µA - 1 2 µA µA -1 -2 - µA µA April 20, 2004 U6264B Symbol Switching Characteristics Min. Max. Unit tt(QX) 5 10 ns tWC tRC tcW tcR 70 70 Access Time E1 LOW or E2 HIGH to Data Valid G LOW to Data Valid Address to Data Valid tACE tOE tAA ta(E) ta(G) ta(A) - Pulse Widths Write Pulse Width Chip Enable to End of Write tWP tCW tw(W) tw(E) 50 65 ns ns Setup Times Address Setup Time Chip Enable to End of Write Write Pulse Width Data Setup Time tAS tCW tWP tDS tsu(A) tsu(E) tsu(W) tsu(D) 0 65 50 35 ns ns ns ns Data Hold Time Address Hold from End of Write tDH tAH th(D) th(A) 0 0 ns ns Output Hold Time from Address Change tOH tv(A) 5 ns tHZCE tdis(E) 0 25 ns tHZWE tHZOE tdis(W) tdis(G) 0 0 30 25 ns ns Alt. IEC Time to Output in Low-Z tLZ Cycle Time Write Cycle Time Read Cycle Time E1 HIGH or E2 LOW to Output in High-Z W LOW to Output in High-Z G HIGH to Output in High-Z Data Retention Mode E1-Controlled Data Retention VCC VCC(DR) ≥ 2 V trec 2.2 V E1 tDR 0.8 V 0V Data Retention VE2(DR) ≤ 0.2 V 0V VE2(DR) ≥ VCC(DR) - 0.2 V or V E2(DR) ≤ 0.2 V VCC(DR) - 0.2 V ≤ VE1(DR) ≤ V CC(DR) + 0.3 V Chip Deselect to Data Retention Time Operating Recovery Time April 20, 2004 ns ns ns 4.5 V VCC(DR) ≥ 2 V 2.2 V tDR 70 40 70 Data Retention Mode E2-Controlled VCC 4.5 V ns ns 5 tDR : trec : min 0 ns min tcR E2 trec 0.8 V U6264B Test Configuration for Functional Check e E1 E2 W G ment of all 8 output pins DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Simultaneous measure- VIL relevant test measurement VIH Input level according to the 5V VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 960 VO 30 pFe 510 VSS In measurement of tdis(E), tdis(W), tdis(G) the capacitance is 5 pF. Capacitance Conditions Symbol Min. Max. Unit Input Capacitance VCC = 5.0 V VI = VSS CI 8 pF Output Capacitance f Ta CO 10 pF = 1 MHz = 25 °C All pins not under test must be connected with ground by capacitors. Ordering Code Example U6264B S2 K 07 LL Type Leadfree Option blank = Standard Package G1 = Leadfree Green Package f Package D = PDIP28 (600 mil, only C/K-Type) S = SOP28 (330 mil) Type 1 S2 = SOP28 (330 mil) Type 2 Operating Temperature Range C = 0 to 70 °C K = -40 to 85 °C A = -40 to 125 °C f Power Consumption blank = Standard (only A-Type) LL = Very Low Power (C/K-Type) Access Time 07 = 70 ns on special request Device Marking (example) Product specification Assembly location and trace code ZMD U6264BS2K 07LL C 0425 1 ZZ G1 Internal Code Date of manufacture (The first 2 digits indicating the year, and the last 2 digits the calendar week.) Leadfree Green Package 6 April 20, 2004 U6264B Read Cycle 1 (during Read cycle: E1 = G = VIL, E2 = W = VIH) tcR Ai DQi Output Addresses Valid ta(A) Previous Data Valid Output Data Valid tv(A) Read Cycle 2 (during Read cycle: W = VIH) tcR Ai E1 Addresses Valid ta(E) tsu(A) tt(QX) tdis(E) tsu(A) ta(E) E2 ta(G) G DQi Output tdis(E) tt(QX) tdis(G) tt(QX) High-Z Output Data Valid Write Cycle 1 (W-controlled) tcW Ai Addresses Valid tsu(E) th(A) E1 E2 W tsu(E) tsu(A) tw(W) tsu(D) DQi Input DQi tdis(W) Input Data Valid High-Z Output G April 20, 2004 th(D) 7 tt(QX) U6264B Write Cycle 2 (E1-controlled) tcW Ai E1 tsu(A) E2 Addresses Valid tw(E) tsu(E) tsu(W) W DQi th(D) tsu(D) DQi Input th(A) tt(QX) Input Data Valid tdis(W) High-Z Output G Write Cycle 3 (E2-controlled) tcW Ai Addresses Valid tsu(E) th(A) E1 tsu(A) tw(E) E2 tsu(W) W tsu(D) DQi Input tt(QX) th(D) Input Data Valid tdis(W) DQi High-Z Output G L- or H-level undefined The information describes the type of component and shall not be considered as assured characteristic. Terms of delivery and rights to change design reserved. 8 April 20, 2004 U6264B LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose. LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However Zentrum Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics. ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and conditions of sale. ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice. Zentrum Mikroelektronik Dresden AG Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: [email protected] • http://www.zmd.de April 20, 2004