U62H64 Automotive Fast 8K x 8 SRAM Features Description ! Fast 8192 x 8 bit static CMOS The U62H64 is a static RAM manufactured using a CMOS process technology with the following operating modes: - Read - Standby - Write - Data Retention The memory array is based on a 6-transistor cell. The circuit is activated by the rising edge of E2 (at E1 = L), or the falling edge of E1 (at E2 = H). The address and control inputs open simultaneously. According to the information of W and G, the data inputs, or outputs, are active. In a Read cycle, the data outputs are activated by the falling edge of G, afterwards the data word read will be available at the outputs DQ0 - DQ7. After the address change, the data outputs go High-Z until the new read information is available. The data outputs have no preferred state. If the memory is driven by CMOS levels in the active state, and if there is no ! ! ! ! ! ! ! ! ! ! ! ! ! ! RAM 35 ns Access Time Bidirectional data inputs and data outputs Three-state outputs Data retention mode at Vcc > 2V Data retention current at 2 V: < 3 µA (K-Type) < 50 µA (A-Type) Standby current < 5 µA (K-Type) < 100 µA (A-Type) TTL/CMOS-compatible Automatic reduction of power dissipation in long Read or Write cycles Power supply voltage 5 V Operating temperature ranges -40 to 85 °C -40 to 125 °C QS 9000 Quality Standard ESD protection > 2000 V (MIL STD 883C M3015.7) Latch-up immunity > 200 mA Package: SOP28 (300 mil) Pin Configuration change of the address, data input and control signals W or G, the operating current (at IO = 0 mA) drops to the value of the operating current in the Standby mode. The Read cycle is finished by the falling edge of E2 or W, or by the rising edge of E1, respectively. Data retention is guaranteed down to 2 V. With the exception of E1 and E2, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required. This gate circuit allows to achieve low power standby requirements by activation with TTL-levels too. Pin Description n.c. 1 28 VCC A12 2 27 W (WE) A7 3 26 E2 (CE2) Signal Name Signal Description A6 4 25 A8 A0 - A12 Address Inputs A5 5 24 A9 DQ0 - DQ7 Data In/Out A4 6 23 A11 E1 Chip Enable 1 A3 7 22 G (OE) E2 Chip Enable 2 A2 8 21 A10 Output Enable 9 20 E1 (CE1) G A1 10 19 DQ7 DQ0 11 18 DQ6 W VCC Write Enable A0 Power Supply Voltage DQ1 12 17 DQ5 VSS Ground DQ2 13 16 DQ4 n.c. not connected VSS 14 15 DQ3 SOP Top View April 20, 2004 1 U62H64 A3 A4 A5 Memory Cell Array 128 Rows 64 x 8 Columns DQ0 Sense Amplifier/ Write Control Logic Address Change Detector Clock Generator Bidirectional Data I/O A2 Row Decoder A1 Column Decoder A0 Row Address Inputs A6 A7 A8 A9 A10 A11 A12 Column Address Inputs Block Diagram DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 E2 VCC VSS W G E1 Truth Table Operating Mode E1 E2 W G DQ0 - DQ7 * L * * High-Z H * * * High-Z Internal Read L H H H High-Z Read L H H L Data Outputs Low-Z Write L H L * Data Inputs High-Z Standby/not selected * H or L 2 April 20, 2004 U62H64 Characteristics All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of V I, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage. Absolute Maximum Ratings a Symbol Min. Max. Unit VCC -0.3 7 V Input Voltage VI -0.3 VCC + 0.5 b V Output Voltage VO -0.3 VCC + 0.5 b V Ta -40 -40 85 125 °C °C Storage Temperature Tstg -65 150 °C Output Short-Circuit Current at VCC = 5 V and VO = 0 V c |IOS| 200 mA Power Supply Voltage Operating Temperature a b c d K-Type A-Type Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Maximum voltage is 7 V Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s. Recommended Operating Conditions Symbol Power Supply Voltage Data Retention Voltage Conditions Min. Max. Unit VCC 4.5 5.5 V VCC(DR) 2.0 - V Input Low Voltage d VIL -0.3 0.8 V Input High Voltage VIH 2.2 VCC + 0.3 V -2 V at Pulse Width 10 ns or -1 V at Pulse Width 50 ns April 20, 2004 3 U62H64 Electrical Characteristics Supply Current - Operating Mode Supply Current - Standby Mode (CMOS level) Symbol ICC(OP) ICC(SB) Conditions = 5.5 V VCC VE1 = VE2 = 2.2 V Supply Current - Data Retention Mode ICC(DR) = 2.0 V VCC(DR) VE1 = VE2 = VCC(DR) - 0.2 V K-Type A-Type Output Low Voltage VOL Output High Current IOH Output Low Current IOL Input High Leakage Current IIH Input Low Leakage Current IIL Output Leakage Current High at Three-State Outputs IOHZ Low at Three-State Outputs IOLZ Unit 50 mA 5 100 µA µA 5 (typ. 2) mA 3 50 µA µA 2.4 - V - 0.4 V - -4.0 mA 8.0 - mA - 2 µA -2 - µA - 2 µA -2 - µA = 5.5 V VCC VE1 = VE2 = VCC - 0.2 V K-Type A-Type ICC(SB)1 VOH Max. = 5.5 V = 0.8 V = 2.2 V = 35 ns VCC VIL VIH tcW Supply Current - Standby Mode (TTL level) Output High Voltage Min. VCC IOH VCC IOL = = = = 4.5 V -4.0 mA 4.5 V 8.0 mA VCC VOH VCC VOL = = = = 4.5 V 2.4 V 4.5 V 0.4 V VCC VIH VCC VIL = 5.5 V = 5.5 V = 5.5 V = 0V VCC VOH VCC VOL = 5.5 V = 5.5 V = 5.5 V = 0V 4 April 20, 2004 U62H64 Symbol Switching Characteristics Unit Min. Max. Alt. IEC tLZCE tLZOE tLZWE ten(E) ten(G) ten(W) 5 0 0 ns ns ns Cycle Time Write Cycle Time Read Cycle Time tWC tRC tcW tcR 35 35 ns ns Access Time E1 LOW or E2 HIGH to Data Valid G LOW to Data Valid Address to Data Valid tACE tOE tAA ta(E) ta(G) ta(A) Pulse Widths Write Pulse Width Chip Enable to End of Write tWP tCW tw(W) tw(E) 20 25 ns ns Setup Times Address Setup Time Chip Enable to End of Write Write Pulse Width Data Setup Time tAS tCW tWP tDS tsu(A) tsu(E) tsu(W) tsu(D) 0 25 20 15 ns ns ns ns Data Hold Time Address Hold from End of Write tDH tAH th(D) th(A) 0 0 ns ns Output Hold Time from Address Change tOH tv(A) 5 ns tHZCE tHZWE tHZOE tdis(E) tdis(W) tdis(G) Time to Output in Low-Z from E1 LOW or E2 HIGH G LOW W HIGH E1 HIGH or E2 LOW to Output in High-Z W LOW to Output in High-Z G HIGH to Output in High-Z E1 LOW or E2 HIGH to Power-Up tPU E1 HIGH or E2 LOW to Power-Down tPD 15 15 12 ns ns ns ns 35 ns Data Retention Mode E2-Controlled VCC 4.5 V VCC 4.5 V VCC(DR) ≥ 2 V VCC(DR) ≥ 2 V 2.2 V 2.2 V Data Retention ns ns ns 0 Data Retention Mode E1-Controlled tDR 35 15 35 trec 0.8 V tDR Data Retention E2 trec 0.8 V E1 0V 0V VE1(DR) ≥ VCC(DR) - 0.2 V or V E1(DR) ≤ 0.2 V VE2(DR) ≤ 0.2 V VE2(DR) ≥ VCC(DR) - 0.2 V or V E2(DR) ≤ 0.2 V VCC(DR) - 0.2 V ≤ VE1(DR) ≤ V CC(DR) + 0.3 V Chip Deselect to Data Retention Time Operating Recovery Time at VCC(DR) April 20, 2004 5 tDR: trec: min 0 ns min t cR U62H64 Test Configuration for Functional Check 5V e E1 E2 W G 481 ment of all 8 output pins DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Simultaneous measure- VIL Input level according to the relevant test measurement VIH VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 VO 30 pF e 255 VSS In measurement of tdis(E), tdis(W), tdis(G) , ten(E), ten(W) , ten(G) the capacitance is 5 pF. Capacitance Conditions Symbol Min. Max. Unit Input Capacitance VCC = 5.0 V VI = VSS CI 8 pF Output Capacitance f Ta CO 10 pF = 1 MHz = 25 °C All pins not under test must be connected with ground by capacitors. Ordering Code Example U62H64 S K 35 L Type Leadfree Option blank = Standard Package G1 = Leadfree Green Package f Package S = SOP28 (300 mil) Operating Temperature Range K = -40 to 85 °C A = -40 to 125 °C f Power Consumption blank = Standard (only A-Type) L = Low Power (only K-Type) Access Time 35 = 35 ns on special request Device Marking (example) Product specification Assembly location and trace code ZMD U62H64SK 35L C 0425 1 ZZ G1 Internal Code Date of manufacture (The first 2 digits indicating the year, and the last 2 digits the calendar week.) Leadfree Green Package 6 April 20, 2004 U62H64 Read Cycle 1 (during Read cycle: E1 = G = VIL, E2 = W = VIH, Ai-controlled) tcR Ai DQi Output Addresses Valid ta(A) Previous Data Valid tv(A) Output Data Valid Read Cycle 2 (during Read cycle: W = VIH, G-, E1- or E2-controlled) tcR Ai E1 Addresses Valid tsu(A) ta(E) ten(E) tdis(E) tsu(A) ta(E) E2 ta(G) G DQi tdis(G) ten(G) High-Z Output ICC(OP) ICC(SB) tdis(E) ten(E) Output Data Valid tPU* tPD* 50 % 50 % * The same applies to E1 Write Cycle 1 (W-controlled) tcW Ai Addresses Valid th(A) tsu(E) E1 E2 W tsu(E) tw(W) tsu(A) tsu(D) DQi Input DQi Input Data Valid tdis(W) High-Z Output G April 20, 2004 th(D) 7 ten(W) U62H64 Write Cycle 2 (E1-controlled) tcW Ai E1 Addresses Valid tw(E) tsu(A) E2 E2 W tsu(E) tsu(W) tsu(D) DQi Input DQi th(A) ten(E) th(D) Input Data Valid tdis(W) High-Z Output G Write Cycle 3 (E2-controlled) tcW Ai Addresses Valid tsu(E) th(A) E1 tsu(A) tw(E) E2 tsu(W) W tsu(D) DQi Input ten(E) th(D) Input Data Valid tdis(W) DQi High-Z Output G L- or H-level undefined The information describes the type of component and shall not be considered as assured characteristic. Terms of delivery and rights to change design reserved. 8 April 20, 2004 U62H64 LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose. LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However Zentrum Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics. ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and conditions of sale. ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice. April 20, 2004 Zentrum Mikroelektronik Dresden AG Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: [email protected] • http://www.zmd.de