U62H256A Automotive Fast 32K x 8 SRAM Features Description ! 32768 x 8 bit static CMOS RAM ! 35 and 55 ns Access Time ! Common data inputs and ! ! ! ! ! ! ! ! ! ! The U62H256A is a static RAM manufactured using a CMOS process technology with the following operating modes: data outputs - Read - Standby Three-state outputs - Write - Data Retention Typ. operating supply current The memory array is based on a 35 ns: 45 mA 6-transistor cell. 55 ns: 30 mA Standby current < 50 µA at 125 °C The circuit is activated by the falling edge of E. The address and TTL/CMOS-compatible control inputs open simultaneously. Power supply voltage 5 V According to the information of W Operating temperature range -40 °C to 85 °C and G, the data inputs, or outputs, -40 °C to 125 °C are active. In a Read cycle, the data outputs are activated by the QS 9000 Quality Standard falling edge of G, afterwards the ESD protection > 2000 V (MIL STD 883C M3015.7) data word will be available at the outputs DQ0-DQ7. After the Latch-up immunity >100 mA address change, the data outputs Package: SOP28 (300/330 mil) Pin Configuration go High-Z until the new information is available. The data outputs have no preferred state. The Read cycle is finished by the falling edge of W, or by the rising edge of E, respectively. Data retention is guaranteed down to 2 V. With the exception of E, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required. Pin Description A14 1 28 VCC A12 2 27 W A7 3 26 A13 A6 4 25 A8 Signal Name Signal Description A5 5 24 A9 A0 - A14 Address Inputs A4 6 23 A11 DQ0 - DQ7 Data In/Out A3 7 22 G E Chip Enable A2 8 21 A10 G Output Enable A1 9 20 E Write Enable A0 10 19 DQ7 W VCC Power Supply Voltage DQ0 11 18 DQ6 VSS Ground DQ1 12 17 DQ5 DQ2 13 16 DQ4 VSS 14 15 DQ3 SOP Top View April 20, 2004 1 U62H256A Row Decoder 512 Rows x 64 x 8 Columns DQ0 Sense Amplifier/ Write Control Logic Address Change Detector Clock Generator DQ1 Common Data I/O A0 A1 A2 A3 A4 A5 Memory Cell Array Column Decoder Column Address Inputs A6 A7 A8 A9 A10 A11 A12 A13 A14 Row Address Inputs Block Diagram DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCC VSS E W G Truth Table Operating Mode E W G DQ0 - DQ7 Standby/not selected H * * High-Z Internal Read L H H High-Z Read L H L Data Outputs Low-Z Write L L * Data Inputs High-Z * H or L 2 April 20, 2004 U62H256A Characteristics All voltages are referenced to V SS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of V I, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured ±200 mV from steady-state voltage. Absolute Maximum Ratings a Symbol Min. Max. Unit VCC -0.5 7 V Input Voltage VI -0.5 VCC + 0.5 b V Output Voltage VO -0.5 VCC + 0.5 b V Power Dissipation PD - 1 W Ta -40 -40 85 125 °C Tstg -65 150 °C 200 mA Power Supply Voltage Operating Temperature K-Type A-Type Storage Temperature Output Short-Circuit Current at VCC = 5 V and VO = 0 V c a b c d | IOS | Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Maximum voltage is 7 V Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s. Recommended Operating Conditions Symbol Power Supply Voltage Conditions Min. Max. Unit VCC 4.5 5.5 V Input Low Voltage d VIL -0.3 0.8 V Input High Voltage VIH 2.2 VCC + 0.3 V -2 V at Pulse Width 10 ns April 20, 2004 3 U62H256A Electrical Characteristics Supply Current - Operating Mode Symbol ICC(OP) Conditions VCC VIL VIH tcW tcW = = = = = VCC VE K-Type A-Type = 5.5 V = VCC - 0.2 V ICC(SB)1 VCC VE = 5.5 V = 2.2 V Output High Voltage VOH Output Low Voltage VOL VCC IOH VCC IOL = 4.5 V = -4.0 mA = 4.5 V = 8.0 mA VCC VIH VCC VIL = 5.5 V = 5.5 V = 5.5 V = 0V VCC VOH VCC VOL = = = = VCC VOH VCC VOL = 5.5 V = 5.5 V = 5.5 V = 0V Supply Current - Standby Mode (CMOS level) Supply Current - Standby Mode (TTL level) ICC(SB) Input High Leakage Current IIH Input Low Leakage Current IIL Output High Current IOH Output Low Current IOL Output Leakage Current High at Three-State Outputs IOHZ Low at Three-State Outputs IOLZ 4 Min. 5.5 V 0.8 V 2.2 V 35 ns 55 ns 4.5 V 2.4 V 4.5 V 0.4 V Max. Unit 90 70 mA mA 10 50 µA µA 1 mA 2.4 V 0.4 V 2 µA -2 µA -4 8 mA 2 -2 mA µA µA April 20, 2004 U62H256A Switching Characteristics Read Cycle Symbol 35 55 Unit Alt. IEC Min. Read Cycle Time tRC tcR 35 Address Access Time to Data Valid tAA ta(A) 35 55 ns Chip Enable Access Time to Data Valid tACE ta(E) 35 55 ns G LOW to Data Valid tOE ta(G) 15 25 ns E HIGH to Output in High-Z tHZCE tdis(E) 15 20 ns G HIGH to Output in High-Z tHZOE tdis(G) 12 15 ns E LOW to Output in Low-Z tLZCE ten(E) 3 3 ns G LOW to Output in Low-Z tLZOE ten(G) 0 0 ns Output Hold Time from Address Change tOH tv(A) 3 3 ns E LOW to Power-Up Time tPU 0 0 ns E HIGH to Power-Down Time tPD Switching Characteristics Write Cycle Max. Min. Max. 55 ns 35 Symbol 55 35 ns 55 Unit Alt. IEC Min. Write Cycle Time tWC tcW 35 55 ns Write Pulse Width tWP tw(W) 20 35 ns Write Setup Time tWP tsu(W) 20 35 ns Address Setup Time tAS tsu(A) 0 0 ns Address Valid to End of Write tAW tsu(A-WH) 25 40 ns Chip Enable Setup Time tCW tsu(E) 25 40 ns Pulse Width Chip Enable to End of Write tCW tw(E) 25 40 ns Data Setup Time tDS tsu(D) 15 25 ns Data Hold Time tDH th(D) 0 0 ns Address Hold from End of Write tAH th(A) 0 0 ns W LOW to Output in High-Z tHZWE tdis(W) 15 20 ns G HIGH to Output in High-Z tHZOE tdis(G) 12 15 ns W HIGH to Output in Low-Z tLZWE ten(W) 0 0 ns G LOW to Output in Low-Z tLZOE ten(G) 0 0 ns April 20, 2004 5 Max. Min. Max. U62H256A Data Retention Mode E - controlled VCC 4.5 V VCC(DR) ≥ 2 V 2.2 V tsu(DR) 2.2 V E trec Data Retention 0V VCC(DR) - 0.2 V ≤ VE(DR) ≤ VCC(DR) + 0.3 V Data Retention Characteristics Symbol Alt. Data Retention Supply Voltage VCC(DR) Data Retention Supply Current ICC(DR) Data Retention Setup Time Operating Recovery Time Conditions IEC tCDR tsu(DR) tR trec Min. Typ. Max. Unit 5.5 V 6 30 µA µA 2 VCC(DR) = 3 V VE = VCC(DR) - 0.2 V K-Type A-Type See Data Retention Waveforms (above) 0 ns tcR ns Test Configuration for Functional Check VIL A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 481 VO 30 pF e E W G e VCC Simultaneous measurement of all 8 output pins VIH Input level according to the relevant test measurement 5V 255 VSS In measurement of tdis(E),tdis(W), ten(E), ten(W), ten(G) the capacitance is 5 pF. 6 April 20, 2004 U62H256A Capacitance Conditions Input Capacitance VCC VI f Ta Output Capacitance Symbol = 5.0 V = VSS = 1 MHz = 25 °C Min. Max. Unit CI 7 pF Co 7 pF All pins not under test must be connected with ground by capacitors. Ordering Code Example U62H256A S K 35 LL Type Leadfree Option blank = Standard Package G1 = Leadfree Green Package f Package S = SOP28 (300 mil) S2 = SOP28 (330 mil) Type 2 Operating Temperature Range K = -40 to 85 °C A = -40 to 125 °C f Power Consumption blank = Standard (only A-Type) LL = Very Low Power (only K-Type) Access Time 35 = 35 ns 55 = 55 ns on special request Device Marking (example) Product specification Assembly location and trace code ZMD U62H256ASK 35LL C 0425 1 ZZ G1 Internal Code April 20, 2004 Date of manufacture (The first 2 digits indicating the year, and the last 2 digits the calendar week.) Leadfree Green Package 7 U62H256A Read Cycle 1: Ai-controlled (during Read Cycle : E = G = V IL, W = VIH) tcR Ai DQi Output Address Valid ta(A) Previous Data Valid Output Data Valid tv(A) Read Cycle 2: G-, E-controlled (during Read Cycle: W = V IH) tcR Ai E Output ICC(OP) ICC(SB) tdis(E) ten(E) ta(G) G DQi Address Valid ta(E) tsu(A) tdis(G) ten(G) High-Z Output Data Valid tPD tPU 50 % 50 % 8 April 20, 2004 U62H256A Write Cycle1: W-controlled tcW Ai Address Valid tsu(E) th(A) E W tsu(A-WH) tw(W) tsu(A) tsu(D) DQi Input th(D) Input Data Valid ten(W) High-Z tdis(W) DQi Output G Write Cycle 2: E-controlled tcW Ai E Address Valid tsu(A) th(A) tw(E) tsu(W) W tsu(D) DQi Input Input Data Valid ten(E) tdis(W) DQi Output th(D) High-Z tdis(G) G undefined L- to H-level H- to L-level The information describes the type of component and shall not be considered as assured characteristics.Terms of delivery and rights to change design reserved. April 20, 2004 9 U62H256A LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose. LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However Zentrum Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics. ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and conditions of sale. ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice. April 20, 2004 Zentrum Mikroelektronik Dresden AG Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: [email protected] • http://www.zmd.de