AMMP-6430 27-32 GHz 0.5W Power Amplifier in SMT Package Data Sheet Description Features The AMMP-6430 MMIC is a broadband 1W power amplifier in a surface mount package designed for use in transmitters that operate in various frequency bands between 27GHz and 32GHz. At 30GHz, it provides 29dBm of output power (P-1dB) and 19dB of small-signal gain from a small easy-to-use device. The device has input and output matching circuitry for use in 50Ω environments. The AMMP-6430 also integrates a temperature compensated RF power detection circuit that enables power detection of 0.3V/W. DC bias is simple and the device operates on widely available 5V for current supply (negative voltage only needed for Vg). It is fabricated in a PHEMT process for exceptional power and gain performance. • Wide Frequency Range 27-32GHz Pin Connections (Top View) • Satellite VSAT, DBS Up/Down Link 1 2 4 7 6 • 50 Ω match on input and output • ESD protection (50V MM, and 150V HBM) • Specifications (Vd=5V, Idsq=650mA) • Frequency range 27 to 32 GHz • Small signal Gain of 20dB • Output power @P-1 of 27dBm (Typ.) • Input/Output return-loss of -10dB Applications • Microwave Radio systems • LMDS & Pt-Pt mmW Long Haul 3 8 • Half watt output power Pin 1 2 3 4 5 6 7 8 Function Vgg Vdd DET_O RF_out DET_R Vdd Vgg RF_in 5 • Broadband Wireless Access (including 802.16 and 802.20 WiMax) • WLL and MMDS loops • Commercial grade military Note: 1. This MMIC uses depletion mode pHEMT devices. Negative supply is used for DC gate biasing. PACKAGE BASE GND RoHS-Exemption Attention: Observe Precautions for handling electrostatic sensitive devices. ESD Machine Model (Class A): 50V ESD Human Body Model (Class 0): 150V Refer to Avago Application Note A004R: Electrostatic Discharge Damage and Control. Please refer to Hazardous substances table on page 11. Absolute Maximum Ratings [1] Symbol Parameters [1] Units Value Notes Vd Positive Supply Voltage V 6 2 Vg Gate Supply Voltage V -3 to 0.5 Idq Drain Current mA 700 PD Power Dissipation W 5.5 2, 3 Pin CW Input Power dBm 23 2 Tch, max Maximum Operating Channel Temp. °C +155 4, 5 Tstg Storage Case Temp. °C -65 to +155 Tmax Maximum Assembly Temp (20 sec max) °C +260 Notes: 1. Operation in excess of any one of these conditions may result in permanent damage to this device. 2. Combinations of supply voltage, drain current, input power, and output power shall not exceed PD. 3. When operate at this condition with a base plate temperature of 85 °C, the median time to failure (MTTF) is significantly reduced. 4. These ratings apply to each individual FET 5. Junction operating temperature will directly affect the device MTTF. For maximum life, it is recommended that junction temperatures be maintained at the lowest possible levels. DC Specifications/ Physical Properties [6] Symbol Parameters and Test Conditions Units Value Idq Drain Supply Current (Vd=5 V, Vg set for Id Typical) mA 650 Vg Gate Supply Operating Voltage (Id(Q) = 650 (mA)) V -1.1 RθJC Thermal Resistance[6] (Channel-to-Base Plate) °C/W 16.8 Tch Channel Temperature °C 139.6 Notes: 6. Assume SnPb soldering to an evaluation RF board at 85 °C base plate temperatures. Worst case is at saturated output power when DC power consumption rises to 5.24W with 0.9W RF power delivered to load. Power dissipation is 4.34W and the temperature rise in the channel is 72.9 °C. In this condition, the base plate temperature must be remained below 82.1 °C to maintain maximum operating channel temperature below 155 °C. AMMP-6430 RF Specifications [1, 2, 3, 4] TA= 25°C, Vdd = 5.0 V, Idq =650 mA, Vg = -1.1V, Zo=50Ω Symbol Parameters and Test Conditions Units Minimum Freq Operational Frequency GHz 27 Typical Gain Small-signal Gain[3, 4] Freq = 27 GHz dB 16 20 P-1dB Output Power at 1dB[3] Gain Compression dBm 26 27 OIP3 Output Third Order Intercept Point dBm 35 RLin Input Return Loss dB 10 RLout Output Return Loss dB 10 Isolation Reverse Isolation dB 43 Maximum 32 Notes: 1. Small/Large -signal data measured in packaged form on a 2.4-mm connecter based evaluation board at TA = 25°C. 2. This final package part performance is verified by a functional test correlated to actual performance at one or more frequencies 3. Specifications are derived from measurements in a 50Ω test environment. Aspects of the amplifier performance may be improved over a narrower bandwidth by application of additional conjugate, linearity, or power matching. 4. Pre-assembly into package performance verified 100% on-wafer published specifications at Frequencies=27, 30, and 32GHz 5. The Gain and P1dB tested at 27GHz guaranteed with measurement accuracy ± 1.5 dB for gain and ±1.6dB for P1dB. AMMP-6430 Typical Performance (Data obtained from 2.4-mm connector based test fixture, and this data is including connecter loss, and board loss.) (TA = 25°C, Vdd=5V, Idq=650mA, Vg=-1.1 V, Zin = Zout = 50Ω) -30 30 0 S21[dB] 25 S11[dB] S12[dB] -5 S22[dB] 15 10 -10 Return Loss [dB] S12[dB] -15 -20 5 0 10 15 20 25 30 Frequency [GHz] 35 40 45 Figure 1. Typical Gain and Reverse Isolation -50 -25 10 15 20 40 45 40 1300 Pout(dBm) 35 30 Po[dBm], and, PAE[%] 20 15 P-1 PAE, @P-1 P-3 PAE, @P-3 10 5 24 25 26 27 28 29 30 1200 PAE[%] 30 25 P-1, P-3 [dBm], PAE[%] 35 Figure 2. Typical Input & Output Return Loss 35 0 25 30 Frequency [GHz] 1100 Id(total) 25 1000 20 900 15 800 10 700 5 600 0 500 -5 31 32 33 -25 34 -20 -15 -10 -5 0 5 10 15 400 20 Pin [dBm] Frequency[GHz] Figure 3. Typical P-1 and PAE Figure 4. Typical Pout, Ids, and PAE vs. Pin at Freq=30GHz 46 10 44 8 Noise Figure [dB] 42 IP3[dBm] 40 38 36 6 4 34 2 32 30 0 25 26 27 28 29 30 31 Frequency [GHz] 32 33 Figure 5. Typical IP3 (Third Order Intercept) @Pin=-20dBm 34 35 24 26 Figure 6. Typical Noise Figure 28 30 32 Frequency [GHz] 34 36 Ids [mA] S21[dB] 20 1 0.35 0 S22_20 0.3 S22_-40 -5 0.2 0.15 0.01 0.1 S22_85 -10 S22[dB] 0.1 Det_R - Det_O [V] Det_R - Det_O [V] 0.25 -15 -20 0.05 0 0.001 5 10 15 20 25 30 -25 35 15 20 25 30 Frequency[GHz] Pout[dBm] Figure 7. Typical Detector voltage vs. Output Power @30GHz 35 40 Figure 8. Typical S22 over temperature 0 32 S11_20 S11_-40 S11_85 -5 30 P-1 [dBm] S11[dB] 28 -10 -15 -20 -25 15 20 25 30 35 40 Figure 9. Typical S11 over temperature P-1_85de g P-1_20de g P-1_-40deg S21_20 S21_-40 25 S21_85 20 15 10 15 20 25 30 Frequency[GHz] Figure 11. Typical Gain over temperature 20 24 26 28 30 32 Frequency [GHz] Figure 10. Typical P-1 over temperature 30 S21[dB] 24 22 Frequency[GHz] 26 35 40 34 36 Typical Scattering Parameters [1] (TA = 25°C, Vdd =5 V, Idq = 650 mA, Zin = Zout = 50Ω) Freq [GHz] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 S11 dB -0.077 -0.244 -0.507 -0.857 -1.286 -1.834 -2.497 -3.218 -3.952 -4.734 -5.372 -5.892 -6.334 -6.785 -7.246 -7.822 -8.056 -8.011 -8.003 -8.086 -10.147 -10.495 -12.051 -15.378 -16.652 -17.111 -23.026 -20.256 -14.571 -13.363 -11.814 -10.715 -10.889 -11.417 -12.098 -11.897 -11.125 -10.020 -9.222 -8.609 -8.175 -7.588 -7.587 -7.506 -7.332 S21 Mag 0.991 0.972 0.943 0.906 0.862 0.810 0.750 0.690 0.634 0.580 0.539 0.507 0.482 0.458 0.434 0.406 0.396 0.398 0.398 0.394 0.311 0.299 0.250 0.170 0.147 0.139 0.071 0.097 0.187 0.215 0.257 0.291 0.285 0.269 0.248 0.254 0.278 0.316 0.346 0.371 0.390 0.417 0.417 0.421 0.430 Phase -30.672 -61.135 -91.481 -121.770 -152.370 176.860 146.160 115.480 84.820 54.869 26.213 -1.577 -28.136 -52.977 -75.942 -95.873 -113.940 -130.700 -150.530 -172.380 160.910 156.560 132.580 122.010 127.100 113.670 100.620 166.160 152.630 128.640 107.980 83.770 65.105 41.069 36.792 24.365 13.967 -0.758 -16.019 -32.089 -47.230 -62.593 -78.246 -89.361 -101.290 dB -60.460 -52.134 -55.059 -62.791 -43.769 -43.125 -47.710 -50.926 -48.273 -47.156 -46.361 -49.213 -43.321 -49.276 -48.968 -50.759 -31.831 -19.650 -8.565 2.944 16.205 19.584 19.712 20.404 20.339 19.880 20.040 20.218 20.087 19.761 19.830 19.352 18.619 18.093 15.162 7.101 -0.825 -7.753 -13.812 -19.209 -24.340 -29.416 -34.254 -38.657 -43.475 S12 Mag 0.001 0.002 0.002 0.001 0.006 0.007 0.004 0.003 0.004 0.004 0.005 0.003 0.007 0.003 0.004 0.003 0.026 0.104 0.373 1.404 6.460 9.533 9.674 10.476 10.398 9.862 10.046 10.255 10.100 9.729 9.807 9.282 8.531 8.028 5.730 2.265 0.909 0.410 0.204 0.110 0.061 0.034 0.019 0.012 0.007 Phase 156.200 7.598 -178.810 135.030 72.309 -55.096 -138.310 167.090 127.030 82.462 37.278 16.009 -18.990 -50.499 -66.480 79.915 37.293 -11.371 -65.975 -130.730 130.360 -6.027 -99.417 174.220 91.597 16.978 -54.022 -128.560 157.600 85.669 10.808 -68.718 -150.100 124.500 14.850 -75.509 -142.060 161.700 110.760 62.155 13.948 -31.372 -72.562 -112.560 -145.910 dB -81.678 -79.982 -78.816 -73.965 -66.459 -61.854 -59.371 -58.859 -51.689 -49.760 -47.391 -48.433 -47.536 -50.113 -47.510 -49.051 -53.232 -54.404 -52.389 -45.317 -44.518 -44.477 -44.466 -44.254 -44.452 -44.351 -45.333 -52.770 -49.161 -57.520 -86.823 -58.807 -62.898 -51.835 -52.719 -58.568 -57.430 -52.497 -56.625 -55.294 -56.805 -57.472 -64.193 -69.135 -60.759 S22 Mag 8.24E-05 1.00E-04 1.15E-04 2.00E-04 4.75E-04 8.08E-04 1.08E-03 1.14E-03 2.60E-03 3.25E-03 4.27E-03 3.79E-03 4.20E-03 3.12E-03 4.21E-03 3.53E-03 2.18E-03 1.90E-03 2.40E-03 5.42E-03 5.94E-03 5.97E-03 5.98E-03 6.13E-03 5.99E-03 6.06E-03 5.41E-03 2.30E-03 3.48E-03 1.33E-03 4.56E-05 1.15E-03 7.16E-04 2.56E-03 2.31E-03 1.18E-03 1.34E-03 2.37E-03 1.47E-03 1.72E-03 1.44E-03 1.34E-03 6.17E-04 3.49E-04 9.16E-04 Phase 13.553 -1.433 -26.240 -79.414 -89.529 -141.380 -174.860 151.750 128.260 76.311 33.764 -0.070 -31.732 -62.027 -80.734 -117.620 -135.710 -136.240 -100.790 -135.360 179.470 146.120 129.370 102.170 63.925 36.998 1.733 -49.664 -75.571 15.834 -92.886 -82.154 92.036 -4.332 -115.640 -48.164 -124.980 -154.340 116.090 91.256 1.705 -87.233 -136.190 -109.180 -29.843 dB -0.075 -0.218 -0.450 -0.847 -1.465 -1.593 -2.056 -2.614 -3.234 -3.919 -4.545 -5.413 -4.738 -4.740 -5.196 -5.850 -6.891 -8.605 -11.491 -15.971 -32.906 -18.247 -18.242 -17.689 -18.009 -19.138 -23.261 -18.834 -15.869 -15.535 -14.211 -13.484 -14.452 -15.301 -12.933 -12.205 -12.066 -11.605 -11.065 -10.402 -9.889 -9.293 -8.532 -7.654 -7.062 Note: 1. Data obtained from a 2.4-mm connecter based module, and this data is including connecter loss, and board loss. Mag 0.991 0.975 0.949 0.907 0.845 0.832 0.789 0.740 0.689 0.637 0.593 0.536 0.580 0.579 0.550 0.510 0.452 0.371 0.266 0.159 0.023 0.122 0.122 0.130 0.126 0.110 0.069 0.114 0.161 0.167 0.195 0.212 0.189 0.172 0.226 0.245 0.249 0.263 0.280 0.302 0.320 0.343 0.374 0.414 0.444 Phase -31.001 -61.826 -92.759 -123.780 -152.600 177.570 145.900 114.510 82.673 51.597 21.330 -7.654 -29.552 -63.489 -93.519 -122.580 -151.530 179.660 151.610 128.630 80.680 -170.070 169.400 159.240 147.290 134.330 137.140 161.640 147.670 128.380 109.870 82.184 72.563 53.869 56.976 32.346 15.583 0.967 -12.574 -26.857 -40.144 -52.531 -64.211 -77.188 -90.938 AMMP-6430 Application and Usage Recommended quiescent DC bias condition for optimum power and linearity performances is Vd=5 volts with Vg (-1.1V) set for Id=650 mA. Minor improvements in performance are possible depending on the application. The drain bias voltage range is 3 to 5V. A single DC gate supply connected to Vg will bias all gain stages. Muting can be accomplished by setting Vg to the pinch-off voltage Vp. emerging from the RF output port. The detected voltage is given by : A simplified schematic for the AMMP6430 MMIC die is shown in Figure 12. The MMIC die contains ESD and over voltage protection diodes for Vg, and Vd terminals. The package diagram for the recommended assembly is shown in Figure 13. In finalized package form, ESD diodes protect all possible ESD or over voltage damages between Vgg and ground, Vgg and Vdd, Vdd and ground. Typical ESD diode current versus diode voltage for 11connected diodes in series is shown in Figure 14. Under the recommended DC quiescent biasing condition at Vds=5V, Ids=650mA, Vgg=-1V, typical gate terminal current is approximately 0.3mA. If an active biasing technique is selected for the AMMP6430 MMIC PA DC biasing, the active biasing circuit must have more than 10-times higher internal current that the gate terminal current. There are three methods to calculate Vofs : An optional output power detector network is also provided. The differential voltage between the Det-Ref and Det-Out pads can be correlated with the RF power DET_R V = (V ref − V det ) − V ofs where Vref is the voltage at the DET_R port, Vdet is a voltage at the DET_0 port, Vofs and is the zero-inputpower offset voltage. 1. Vofs can be measured before each detector measurement (by removing or switching off the power source and measuring Vref - Vdet). This method gives an error due to temperature drift of less than 0.01dB/50°C. 2. Vofs can be measured at a single reference temperature. The drift error will be less than 0.25dB. 3. Vofs can either be characterized over temperature and stored in a lookup table, or it can be measured at two temperatures and a linear fit used to calculate Vofs at any temperature. This method gives an error close to the method #1. The RF ports are AC coupled at the RF input to the first stage and the RF output of the final stage. No ground wired are needed since ground connections are made with plated through-holes to the backside of the device. Vd Vg DQ DET_O RFout RF in Figure 12. Simplified schematic for the MMIC die Three stage 0.5W power amplifier DET_O 1 3 2 RF Input RF Output 8 4 7 6 5 DET_R 50 Ω 5V − 0 . 8V 1μF 100 pF 100 pF 1μ F Figure 13. Typical DC connection 20 |Icomp(I_METER.AMP1,0)| (mA) Diode_current 18 16 Diode Current [mA] 14 12 10 8 6 4 2 0 5 5.5 6 6.5 7 7.5 8 Voltage (V) Figure 14. Typical ESD diode current versus diode voltage for 11-connected diodes in series Pin 1 2 3 4 5 6 7 8 Function Vgg Vdd DET_O RF_out DET_R Vdd Vgg RF_in Figure 15a. Suggested PCB Land Pattern and Stencil Layout Ground vias should be solder filled Figure 15b. PCB Land Pattern and Stencil Layouts The AMMP Packaged Devices are compatible with high volume surface mount PCB assembly processes. The PCB material and mounting pattern, as defined in the data sheet, optimizes RF performance and is strongly recommended. An electronic drawing of the land pattern is available upon request from Avago Sales & Application Engineering. Figure 15c. Stencil Outline Drawing(mm) Manual Assembly • Follow ESD precautions while handling packages. • Handling should be along the edges with tweezers. • Recommended attachment is conductive solder paste. Please see recommended solder reflow profile. Neither Conductive epoxy or hand soldering is recommended. • Apply solder paste using a stencil printer or dot placement. The volume of solder paste will be dependent on PCB and component layout and should be controlled to ensure consistent mechanical and electrical performance. • Follow solder paste and vendor’s recommendations when developing a solder reflow profile. A standard profile will have a steady ramp up from room temperature to the pre-heat temp. to avoid damage due to thermal shock. • Packages have been qualified to withstand a peak temperature of 260°C for 20 seconds. Verify that the profile will not expose device beyond these limits. 300 Peak = 250 ± 5˚C Temp (°C) 250 Melting point = 218˚C 200 A properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the PCB pads. The recommended stencil layout is shown in Figure 15b. The stencil has a solder paste deposition opening approximately 70% to 90% of the PCB pad. Reducing stencil opening can potentially generate more voids underneath. On the other hand, stencil openings larger than 100% will lead to excessive solder paste smear or bridging across the I/O pads. Considering the fact that solder paste thickness will directly affect the quality of the solder joint, a good choice is to use a laser cut stencil composed of 0.127mm (5 mils) thick stainless steel which is capable of producing the required fine stencil outline. The most commonly used solder reflow method is accomplished in a belt furnace using convection heat transfer. The suggested reflow profile for automated reflow processes is shown in Figure 16. This profile is designed to ensure reliable finished joints. However, the profile indicated in Figure 1 will vary among different solder pastes from different manufacturers and is shown here for reference only. AMMP-6430 Part Number Ordering Information 150 Part Number Devices Per Container Container 100 AMMP-6430-BLKG 10 Antistatic bag AMMP-6430-TR1G 100 7” Reel AMMP-6430-TR2G 500 7” Reel 50 0 Ramp 1 0 Preheat Ramp 2 50 100 Reflow 150 200 Cooling 250 300 Seconds Figure 16. Suggested Lead-Free Reflow Profile for SnAgCu Solder Paste 300 Peak = 250 ± 5°C 250 Melting point = 218°C Temp (°C) 200 150 100 50 Ramp 1 0 0 Preheat 50 Ramp 2 100 Reflow 150 Seconds Cooling 200 250 300 Package, Tape & Reel, and Ordering Information 0.114 (2.90) 0.011 (0.28) 0.018 (0.46) 1 2 3 3 2 0.014 (0.365) 1 * AMMP XXXX YWWDNN .200 [5.08] 8 0.126 (3.2) 4 8 4 0.059 (1.5) 0.016 (0.40) 0.100 (2.54) 0.012 (0.30) 0.029 (0.75) 7 6 5 5 .200 [5.08] .075 [1.91] FRONT VIEW SIDE VIEW 6 7 0.016 (0.40) 0.028 (0.70) 0.100 (2.54) Notes: 1. Dimensions are in inches [milimeters] 2. All grounds must be soldered to PCB RF 3. Material is rogers RO4350, 0.010” Thick 0.93 (2.36) BACK VIEW DIMENSIONAL TOLERANCE FOR BACK VIEW: 0.002" (0.05 mm) 4.00 ± 0.10 SEE NOTE #2 .011 ∅1.55 ± 0.05 2.00 ± 0.05 B R 0.50 TYP. Ao 1.75 ± 0.10 5.50 ± 0.05 12.00 ± 0.10 Bo A Top View A Bo Side View Dimensional Tolerances: 0.002" [0.05mm] Ko B 8.00 ± 0.10 SECTION B-B ∅1.50 (MIN.) Ko View Back Ao A o: B o: Ko: PITCH: WIDTH: 0.30 ± 0.05 SECTION A- A 5.30 5.30 2.20 8.00 12.00 Ao Bo Ko MIN. 5.20 5.20 2.10 NOM. 5.30 5.30 2.20 MAX. 5.40 5.40 2.30 4 mm Notes: 1. Ao and Bo measured at 0.3 Mm above base of pocket. 2. 10 Pitches cumulative tolerance is ± 0.2 Mm. 3. Dimensions are in millimeters (mm). 12 mm 10 AMMP XXXX AMMP XXXX AMM P XXXX Names and Contents of the Toxic and Hazardous Substances or Elements in the Products Part Name Toxic and Hazardous Substances or Elements Lead (Pb) (Pb) Mercury (Hg) Hg Cadmium (Cd) Cd Hexavalent (Cr(VI)) Cr(VI) Polybrominated biphenyl (PBB) PBB 100pF capacitor : indicates that the content of the toxic and hazardous substance in all the homogeneous materials of the part is below the concentration limit requirement as described in SJ/T 11363-2006. : indicates that the content of the toxic and hazardous substance in at least one homogeneous material of the part exceeds the concentration limit requirement as described in SJ/T 11363-2006. (The enterprise may further explain the technical reasons for the “x” indicated portion in the table in accordance with the actual situations.) SJ/T 11363-2006 SJ/T 11363-2006 “×” Note: EU RoHS compliant under exemption clause of “lead in electronic ceramic parts (e.g. piezoelectronic devices)” For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. AV02-0623EN - August 20, 2007 Polybrominated diphenylether (PBDE) PBDE