HOLTEK HT45RM03

HT45RM03
Brushless DC Motor Type 8-Bit OTP MCU
Technical Document
· Tools Information
· FAQs
· Application Note
Features
· Operating voltage:
· Up to 0.33ms instruction cycle with 12MHz system
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
fSYS=12MHz: 4.5V~5.5V
clock at VDD=5V
· 8-level subroutine nesting
· 8 channels 9-bit resolution A/D converter
· 23 bidirectional I/O lines (max.)
· 3-channel 10-bit PWM with complementary output
· 4 interrupt input shared with 4 I/O line
shared with six I/O lines
· Two 8-bit programmable timer/event counter with
· Bit manipulation instruction
overflow interrupt and 7-stage prescaler
· 15-bit table read instruction
· On-chip crystal and RC oscillator
· 63 powerful instructions
· Watchdog Timer
· All instructions in one or two machine cycles
· 4096´15 program memory
· Low voltage reset function
· 192´8 data memory RAM
· One operational Amplifier
· Supports PFD for sound generation
· One Comparator with interrupt function
· HALT function and wake-up feature reduce power
· 28-pin SKDIP/SOP packages
consumption
General Description
oscillator options, multi-channel A/D Converter, Pulse
Width Modulation function, HALT and wake-up functions, enhance the versatility of these devices to suit a
wide range of A/D application possibilities such as sensor signal processing, motor driving, industrial control,
consumer products, subsystem controllers, etc.
The HT45RM03 is 8-bit, high performance, RISC architecture microcontroller devices specifically designed for
A/D applications that interface directly to analog signals,
such as those from sensors.
The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions,
Rev. 1.10
1
February 16, 2007
HT45RM03
Block Diagram
P A
P A
P A
P A
4 /IN
5 /IN
6 /IN
7 /IN
T 0 A
T 0 B
T 0 C
T 1
P r e s c a le r
M
T M R 0 C
U
fS
Y S
P B 7 /A N 7 /T M R 0 /T M R 1
X
T M R 0
P F D 0
In te rru p t
C ir c u it
S T A C K
P ro g ra m
R O M
P ro g ra m
C o u n te r
M
T M R 1 C
IN T C
T M R 1
U
P r e s c a le r
fS
Y S
P B 7 /A N 7 /T M R 0 /T M R 1
X
P F D 1
fS
In s tr u c tio n
R e g is te r
M
M P
U
W D T
P r e s c a le r
D a ta
M e m o ry
X
P D C
P o rt D
P D
8 -C h a n n e l
A /D C o n v e rte r
M U X
In s tr u c tio n
D e c o d e r
P B C
S T A T U S
A L U
P o rt B
P B
S h ifte r
T im in g
G e n e ra to r
O P A
P A 3 , P A 5
P A C
O S C 2
O S
R E
V D
V S
S
S
C 1
A C C
L V R
P o rt A
P A
D
C o m p a ra to r
P C
M
W D T
P o rt C
P C C
P W M
/4
Y S
U
X
R C
P D 0 /P F D
P B
P B
P B
P B
P B
0 /A
2 /A
3 /A
4 /A
7 /A
N 0
N 2
N 3
N 4
N 7
~
/O
/O
~
/T
P A
P A
P A
P A
P A
P A
P A
P A
P C
P C
P C
P C
P C
P C
0 /O
1 /C
2 /C
3 /C
4 /IN
5 /IN
6 /IN
7 /IN
0 /P
1 /P
2 /P
3 /P
4 /P
5 /P
P V
V IN
V IN
O U
T 0
T 0
T 0
T 1
W M
W M
W M
W M
W M
W M
IN P
P
N
T
A
B
C
0
P B
P
P
P B
M
0
1
1
2
O S C
1 /A N 1
O U T
V IN N
6 /A N 6
R 0 /T M R 1
2
Pin Assignment
P B 5 /A N 5
1
2 8
P B 6 /A N 6
P B 4 /A N 4
2
2 7
P B 7 /A N 7 /T M R 0 /T M R 1
P A 3 /C O U T
3
2 6
P A 4 /IN T 0 A
P A 2 /C V IN N
4
2 5
P A 5 /IN T 0 B
P A 1 /C V IN P
5
2 4
P A 6 /IN T 0 C
P A 0 /O P V IN P
6
2 3
P A 7 /IN T 1
P B 3 /A N 3 /O P V IN N
7
2 2
O S C 2
P B 2 /A N 2 /O P O U T
8
2 1
O S C 1
P B 1 /A N 1
9
2 0
V D D
P B 0 /A N 0
1 0
1 9
R E S
V S S
1 1
1 8
P D 0 /P F D
P C 0 /P W M 0
1 2
1 7
P C 5 /P W M 2
P C 1 /P W M 0
1 3
1 6
P C 4 /P W M 2
P C 2 /P W M 1
1 4
1 5
P C 3 /P W M 1
H T 4 5 R M 0 3
2 8 S K D IP -A /S O P -A
Rev. 1.10
2
February 16, 2007
HT45RM03
Pad Description
Pad Name
Option
Description
Wake-up
Pull-high
Bidirectional 8-bit input/output port. Each bit can be configured as
wake-up input by ROM code option. Software instructions determine
the CMOS output or Schmitt trigger input with or without pull-high resistor (determined by pull-high options: bit option). The INT0A, INT0B,
INT0C and INT1 are pin-shared with PA4~PA7.
The CVINP, CVINN and COUT are pin-shared with PA1, PA2 and PA3.
Once the Comparator function is used, the internal registers related to
PA1, PA2 cannot be used, PA3 can be used as input only, and the PA1,
PA2 I/O function and pull-high resistor are disabled automatically. Software instructions determine the Comparator function to be used.
The OPVINP is pin-shared with PA0.
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor
(determined by pull-high option: bit option) or A/D input. Once a PB line
is selected as an A/D input (by using software control), the I/O function
and pull-high resistor are disabled automatically.
The OPVINP, OPVINN and OPOUT are pin-shared with PA0, PB3/AN3
and PB2/AN2 respectively. Once the OPA function is used, the internal
registers related to PA0, PB3 and PB2 cannot be used, and the I/O
function and pull-high resistor are disabled automatically. Software instructions determine the OPA function to be used.
I/O
Pull-high
Bidirectional 6-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without a pull-high resistor
(determined by pull-high option: byte option). The PWM0~PWM2 and
PWM0~PWM2 output function are pin-shared with PC0, PC2, PC4 and
PC1, PC3, PC5 respectively by software control.
I/O
Pull-high
PFD
Bidirectional 1-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without a pull-high resistor
(determined by pull-high option: bit option). The PFD output function is
pin-shared with PD0.
RES
I
¾
Schmitt trigger reset input. Active low.
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground.
OSC1
OSC2
I
O
Crystal
or RC
PA0/OPVINP
PA1/CVINP
PA2/CVINN
PA3/COUT
PA4/INT0A
PA5/INT0B
PA6/INT0C
PA7/INT1
I/O
I/O
PB0/AN0
PB1/AN1
PB2/AN2/OPOUT
I/O
PB3/AN3/OPVINN
PB4/AN4~PB6/AN6
PB7/AN7/TMR0/TMR1
PC0/PWM0
PC1/PWM0
PC2/PWM1
PC3/PWM1
PC4/PWM2
PC5/PWM2
PD0/PFD
OSC1, OSC2 are connected to an RC network or a Crystal (determined
by options) for the internal system clock. In the case of RC operation,
OSC2 is the output terminal for 1/4 system clock.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.10
3
February 16, 2007
HT45RM03
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
IDD1
Operating Voltage
Operating Current
(Crystal OSC, RC OSC)
Min.
Typ.
Max.
Unit
Conditions
VDD
¾
fSYS=4MHz
2.2
¾
5.5
V
¾
fSYS=8MHz
3.3
¾
5.5
V
¾
fSYS=12MHz
4.5
¾
5.5
V
3V
No load, fSYS=4MHz
ADC disable
¾
1
2
mA
¾
2.5
5
mA
5V
IDD2
Operating Current
(Crystal OSC, RC OSC)
5V
No load, fSYS=8MHz
ADC disable
¾
4
8
mA
IDD3
Operating Current
(Crystal OSC, RC OSC)
5V
No load, fSYS=12MHz
ADC disable
¾
5
10
mA
ISTB1
Standby Current
(WDT Enabled)
¾
¾
5
mA
¾
¾
10
mA
¾
¾
1
mA
¾
¾
2
mA
ISTB2
Standby Current
(WDT Disabled)
3V
No load, system HALT
5V
3V
No load, system HALT
5V
VIL1
Input Low Voltage for I/O Ports,
TMR0, TMR1, INT0A, INT0B,
INT0C and INT1
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR0, TMR1, INT0A, INT0B,
INT0C and INT1
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
3.98
4.2
4.42
V
VIH2
VLVR1
Low Voltage Reset 1
¾
Configuration option:
4.2V
VLVR2
Low Voltage Reset 2
¾
Configuration option:
3.15V
2.98
3.15
3.32
V
VLVR3
Low Voltage Reset 3
¾
Configuration option:
2.1V
1.98
2.1
2.22
V
IOL
3V
VOL=0.1VDD
4
8
¾
mA
I/O Port Sink Current
5V
VOL=0.1VDD
10
20
¾
mA
3V
VOH=0.9VDD
-2
-4
¾
mA
5V
VOH=0.9VDD
-5
-10
¾
mA
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
V
IOH
RPH
I/O Port Source Current
Pull-high Resistance
VAD
A/D Input Voltage
¾
¾
0
¾
VDD
EAD
A/D Conversion Error
¾
¾
¾
±0.5
±1
LSB
IADC
Additional Power Consumption
if A/D Converter is Used
3V
¾
0.5
1
mA
¾
1.5
3
mA
Rev. 1.10
¾
5V
4
February 16, 2007
HT45RM03
A.C. Characteristics
Symbol
fSYS
fTIMER
Parameter
System Clock
Timer I/P Frequency
(TMR0/TMR1)
tWDTOSC Watchdog Oscillator Period
Ta=25°C
Test Conditions
Conditions
VDD
Min.
Typ.
Max.
Unit
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
4.5V~5.5V
400
¾
12000
kHz
¾
¾
0
¾
4000
kHz
3V
¾
45
90
180
ms
ms
5V
¾
32
65
130
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
Wake-up from HALT
¾
1024
¾
*tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tAD
¾
¾
ms
A/D Clock Period
¾
¾
1
tADC
A/D Conversion Time
¾
¾
¾
72
¾
tAD
tADCS
A/D Sampling Time
¾
¾
¾
32
¾
tAD
tLVR
Low Voltage Width to Reset
¾
¾
0.25
1
2
ms
Note: *tSYS=1/fSYS
OP Amplifier Electrical Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
¾
Min.
Typ.
Max.
Unit
3
¾
5.5
V
D.C. Electrical Characteristic
VDD
Operating Voltage
¾
VOS
Input Offset Voltage
5V
-5
¾
5
mV
VCM
Common Mode Voltage Range
¾
¾
VSS
¾
VDD-1.4
V
PSRR
Power Supply Rejection Ratio
¾
¾
60
¾
¾
dB
CMRR
Common Mode Rejection Ratio
¾
60
¾
¾
dB
By calibration
VDD=5V
VCM=0~VDD-1.4V
A.C. Electrical Characteristic
AOL
Open Loop Gain
¾
60
80
¾
dB
SR
Slew Rate+, Rate-
¾
No load
¾
¾
1
¾
V/ms
GBW
Gain Band Width
¾
RL=1MW, CL=100pF
¾
¾
100
kHz
Comparator Electrical Characteristics
Symbol
Parameter
Test Conditions
VDD
VDD
Operating Voltage
¾
VOS
Comparator Input Offset Voltage
5V
VCM
Comparator Common Mode
Voltage Range
¾
tPD
Comparator Response Time
¾
Rev. 1.10
Ta=25°C
Conditions
¾
Typ.
Max.
Unit
3
¾
5.5
V
-5
¾
5
mV
¾
0
¾
VDD-1.4
V
¾
¾
¾
2
ms
By calibration
5
Min.
February 16, 2007
HT45RM03
Functional Description
Execution Flow
struction code, the contents of the program counter are incremented by one. The program counter then points to the
memory word containing the next instruction code.
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
Program Counter - PC
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
The program counter (PC) controls the sequence in
which the instructions stored in program PROM are executed and its contents specify full range of program
memory.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an inS y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
Comparator Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
External Interrupt 0
0
0
0
0
0
0
0
0
1
0
0
0
External Interrupt 1
0
0
0
0
0
0
0
0
1
1
0
0
PWM Period Interrupt
0
0
0
0
0
0
0
1
0
0
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
1
0
1
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
1
1
0
0
0
@3
@2
@1
@0
Skip
Program Counter + 2
Loading PCL
*11
*10
*9
*8
@7
@6
@5
@4
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
*11~*0: Program counter bits
#11~#0: Instruction code bits
Rev. 1.10
S11~S0: Stack register bits
@7~@0: PCL bits
6
February 16, 2007
HT45RM03
Program Memory - ROM
0 0 0 H
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
4096´15 bits, addressed by the program counter and table pointer.
0 0 4 H
D e v ic e In itia liz a tio n P r o g r a m
C o m p a ra to r In te rru p t
0 0 8 H
E x te rn a l In te rru p t 0
0 0 C H
E x te rn a l In te rru p t 1
0 1 0 H
0 1 4 H
Certain locations in the program memory are reserved
for special usage:
0 1 8 H
· Location 000H
These area is reserved for program initialization. After
chip reset, the program always begins execution at location 000H.
n 0 0 H
n F F H
P W M
P e r io d In te r r u p t
T im e r /E v e n t C o u n te r 0 O v e r flo w
P ro g ra m
M e m o ry
T im e r /E v e n t C o u n te r 1 O v e r flo w
L o o k - u p T a b le ( 2 5 6 w o r d s )
· Location 004H
These area is reserved for the Comparator interrupt
service program. If the Comparator output pin is activated, and if the interrupt is enable and the stack is not
full, the program begins execution at location 004H.
F F F H
1 5 b its
N o te : n ra n g e s fro m
· Location 008H
These area is reserved for the external interrupt 0 service program. If the INT0A, INT0B or INT0C input pin
is activated, the interrupt is enabled and the stack is
not full, the program begins execution at location
008H.
0 to F
Program Memory
· Table location
Any location in the PROM space can be used as
look-up tables. The instructions ²TABRDC [m]² (the
current page, 1 page=256 words) and ²TABRDL [m]²
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
other bits of the table word are transferred to the lower
portion of TBLH, and the remaining 1 bit is read as ²0².
The Table Higher-order byte register (TBLH) is read
only. The table pointer (TBLP) is a read/write register
(07H), which indicates the table location. Before accessing the table, the location must be placed in
TBLP. The TBLH is read only and cannot be restored.
If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be
changed by the table read instruction used in the ISR.
Errors can occur. In other words, using the table read
instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read
instruction has to be applied in both the main routine
and the ISR, the interrupt is supposed to be disabled
prior to the table read instruction. It will not be enabled
until the TBLH has been backed up. All table related
instructions require two cycles to complete the operation. These areas may function as normal program
memory depending upon the requirements.
· Location 00CH
These area is reserved for the external interrupt 1 service program. If the INT1 input pin is activated, the interrupt is enabled and the stack is not full, the program
begins execution at location 00CH.
· Location 010H
These area is reserved for the PWM period interrupt
service program. If a PWM period interrupt results
from a PWM counter overflow, and if the interrupt is
enabled and the stack is not full, the program begins
execution at location 010H.
· Location 014H
These area is reserved for the Timer/Event Counter 0
interrupt service program. If a timer interrupt results
from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program
begins execution at location 014H.
· Location 018H
These area is reserved for the Timer/Event Counter 1
interrupt service program. If a timer interrupt results
from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program
begins execution at location 018H.
Instruction
L o o k - u p T a b le ( 2 5 6 w o r d s )
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
*11~*0: Table location bits
@7~@0: Table pointer bits
Rev. 1.10
P11~P8: Current program counter bits
7
February 16, 2007
HT45RM03
Stack Register - STACK
0 0 H
This is a special part of the memory which is used to save
the contents of the Program Counter only. The stack is organized into 8 levels and is neither part of the data nor
part of the program space, and is neither readable nor
writeable. The activated level is indexed by the stack
pointer (SP) and is neither readable nor writeable. At a
subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, signaled
by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a
chip reset, the SP will point to the top of the stack.
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
In d ir e c t A d d r e s s in g R e g is te r 0
0 4 H
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
0 D H
T M R 0
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 8 return addresses are stored).
0 E H
T M R 0 C
1 8 H
P D
Data Memory - RAM
1 9 H
P D C
1 A H
P W M H
0 F H
The data memory is designed with 226´8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(192´8). Most are read/write, but some are read only.
T M R 1
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 B H
P W M L
1 C H
P W M C
1 D H
M IS C
1 E H
IN T C 1
S p e c ia l P u r p o s e
D a ta M e m o ry
1 F H
The special function registers include the indirect addressing registers (00H;02H), Timer/Event Counter 0
(TMR0;0DH), Timer/Event Counter 0 control register
(TMR0C;0EH), Timer/Event Counter 1 (TMR1:10H),
Timer/Event Counter 1 control register (TMR1C; 11H),
program counter lower-order byte register (PCL;06H),
memory pointer registers (MP0;01H, MP1;03H), accumulator (ACC;05H), table pointer (TBLP;07H), table
higher-order byte register (TBLH;08H), status register
(STATUS;0AH), interrupt control register 0 (INTC0;
0BH), PWM higher-order byte register (PWMH;1AH),
PWM lower-order byte register (PWML;1BH), PWM
Control register (PWMC;1CH), Miscellaneous register
(MISC;1DH), the A/D result lower-order byte register
(ADRL;20H), the A/D result higher-order byte register
(ADRH;21H), the A/D control register (ADCR;22H), the
A/D clock setting register (ACSR;23H), the Comparator Control register (CMPC;24H), the Operational Amplifier Control register (OPAC;25H), I/O registers
(PA;12H, PB;14H, PC;16H, PD;18H) and I/O control
registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H).
The remaining space before the 26H or 40H is reserved for future expanded usage and reading these
locations will get ²00H². The general purpose data
memory, addressed from 40H to FFH, is used for data
and control information under instruction commands.
Rev. 1.10
1 0 H
2 0 H
A D R H
2 1 H
A D R L
2 2 H
A D C R
2 3 H
A C S R
2 4 H
C M P C
2 5 H
O P A C
2 6 H
2 7 H
2 8 H
3 F H
4 0 H
F F H
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 9 2 B y te s )
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer registers (MP0;01H/MP1;03H).
8
February 16, 2007
HT45RM03
Indirect Addressing Register
Arithmetic and Logic Unit - ALU
The method of indirect addressing allows data manipulation using memory pointers instead of the usual direct
memory addressing method where the actual memory
address is defined. Any action on the indirect addressing registers will result in corresponding read/write operations to the memory location specified by the
corresponding memory pointers. This device contains
two indirect addressing registers known as IAR0 and
IAR1 and two memory pointers MP0 and MP1. Note that
these indirect addressing registers are not physically
implemented and that reading the indirect addressing
registers indirectly will return a result of ²00H² and writing to the registers indirectly will result in no operation.
This circuit performs 8-bit arithmetic and logic operations.
The ALU provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but
also changes the status register.
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
The two memory pointers, MP0 and MP1, are physically
implemented in the data memory and can be manipulated in the same way as normal registers providing a
convenient way with which to address and track data.
When any operation to the relevant indirect addressing
registers is carried out, the actual address that the
microcontroller is directed to is the address specified by
the related memory pointer.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addition operations related to the status register may give
different results from those intended. The TO flag
can be affected only by system power-up, a WDT
time-out or executing the ²CLR WDT² or ²HALT² instruction. The PDF flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or a
system power-up.
Direct data transfer between two indirect addressing
registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the Program Memory by combining corresponding
indirect addressing registers.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
Bit No.
Label
Function
0
C
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
1
AC
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
3
OV
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
5
TO
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Status (0AH) Register
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9
February 16, 2007
HT45RM03
call to location 04H occurs. The related interrupt request
flag (CF) is reset, and the EMI bit is cleared to disable
further maskable interrupts.
Interrupt
The devices provides four external interrupts, two internal Timer/Event Counter 0/1 interrupts, one comparator
interrupt, and PWM period interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt control register
1 (INTC1;1EH) both contain the interrupt control bits
that are used to set the enable/disable status and interrupt request flags.
External interrupts are triggered by a an edge transition
of INT0A, INT0B, INT0C or INT1 (software control: high
to low, low to high, low to high or high to low), and the related interrupt request flag (EIF0; bit 5 of INTC0, EIF1;
bit 6 of INTC0) is set as well. After the interrupt is enabled, the stack is not full, and the external interrupt is
active, a subroutine call to location 08H or 0CH occurs.
The interrupt request flag (EIF0 or EIF1) and EMI bits
are all cleared to disable other maskable interrupts.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may happen during this interval but
only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of INTC0 and INTC1
may be set to allow interrupt nesting. If the stack is full,
the interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the SP is decremented.
If immediate service is desired, the stack must be prevented from becoming full.
The PWM period interrupt is initialized by setting the
PWM period interrupt request flag (PWMF; bit 4 of
INTC1), that is caused by a regular PWM period signal.
After the interrupt is enabled, and the stack is not full,
and the PWMF bit is set, a subroutine call to location
10H occurs. The related interrupt request flag (PWMF)
is reset and the EMI bit is cleared to disable further
maskable interrupts.
The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 5 of the INTC1), which is normally
caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T0F bit is set, a
subroutine call to location 014H occurs. The related interrupt request flag (T0F) is reset, and the EMI bit is
cleared to disable further interrupts. The Timer/Event
Counter 1 is operated in the same manner, The
Timer/Event Counter 1 related interrupt request flag is
T1F (bit 6 of the INTC1) and its subroutine call location
is 018H. The related interrupt request flag (T1F) will be
reset and the EMI bit cleared to disable further interrupts.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the contents should be saved in advance.
The Comparator output Interrupt is initialized by setting
the Comparator output Interrupt request flag (CF; bit 4 of
the INTC0), which is caused by a falling edge transition
of comparator output. After the interrupt is enabled, and
the stack is not full, and the CF bit is set, a subroutine
Bit No.
Label
Function
0
EMI
Control the master (global) interrupt (1=enabled; 0=disabled)
1
ECI
Control the Comparator interrupt (1=enabled; 0=disabled)
2
EEI0
Control the external INT0A, INT0B, INT0C interrupt(1=enabled; 0=disabled)
3
EEI1
Control the external INT1 interrupt (1=enabled; 0=disabled)
4
CF
5
EI0F
External interrupt INT0A, INT0B, INT0C request flag (1=active; 0=inactive)
6
EI1F
External interrupt INT1 request flag (1=active; 0=inactive)
7
¾
The Comparator request flag (1=active; 0=inactive)
Unused bit, read as ²0².
INTC0 (0BH) Register
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February 16, 2007
HT45RM03
Bit No.
Label
Function
0
EPWMI
1
ET0I
Control the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
2
ET1I
Control the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)
3, 7
¾
4
PWMF
5
T0F
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
6
T1F
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
Control the PWM period interrupt (1=enabled; 0=disabled)
Unused bit, read as ²0².
PWM period request flag (1=active; 0=inactive)
INTC1 (1EH) Register
serviced. Once the interrupt request flags (EI0F, EI1F,
CF, T0F, T1F, PWMF) are all set, they remain in the
INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a software instruction.
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (of course, if the stack is
not full). To return from the interrupt subroutine, ²RET² or
²RETI² may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only one
stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged
once the ²CALL² operates in the interrupt subroutine.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Comparator output Interrupt
External INT0A, INT0B, INT0C
Interrupt
Priority
Vector
1
04H
Oscillator Configuration
There are two oscillator circuits in the microcontroller.
V
O S C 1
2
08H
External INT1 Interrupt
3
0CH
PWM Period Interrupt
4
10H
Timer/Event Counter 0 Overflow
5
14H
Timer/Event Counter 1 Overflow
6
18H
4 7 0 p F
fS
O S C 2
Y S
O S C 1
O S C 2
/4
C r y s ta l O s c illa to r
R C
O s c illa to r
System Oscillator
Both are designed for system clocks, namely the RC oscillator and the Crystal oscillator, which are determined
by options. No matter what oscillator type is selected,
the signal provides the system clock. The HALT mode
stops the system oscillator and ignores an external signal to conserve power.
The Comparator interrupt request flag (CF), external interrupt 1 request flag (EI1F), External Interrupt 0 request
flag (EI0F), Enable Comparator 0 output interrupt bit
(EC0I), Enable External interrupt 1 bit (EEI1), Enable
External Interrupt 0 bit (EEI0), and enable master interrupt bit (EMI) make up of the Interrupt Control register 0
(INTC0) which is located at 0BH in the RAM.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance must
range from 24kW to 1MW. The system clock, divided by 4,
is available on OSC2 with pull-high resistor, which can be
used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of oscillation may vary with VDD, temperatures
and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an
accurate oscillator frequency is desired.
The PWM period interrupt request flag (PWMF), the
Timer/Event Counter 1 interrupt request flag (T1F), the
Timer/Event Counter 0 interrupt request flag (T0F), enable PWM period interrupt bit (EPWMI), enable
Timer/Event Counter 1 interrupt bit (ET1I), and enable
Timer/Event Counter 0 interrupt bit (ET0I), constitute the
Interrupt Control register 1 (INTC1) which is located at
1EH in the RAM.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are required. Instead of a crystal, a resona-
EMI, EEI0, EEI1, ECI, ET0I, ET1I, and EPWMI are all
used to control the enable/disable status of interrupts.
These bits prevent the requested interrupt from being
Rev. 1.10
D D
11
February 16, 2007
HT45RM03
tor can also be connected between OSC1 and OSC2 to
get a frequency reference, but two external capacitors in
OSC1 and OSC2 are required (If the oscillating frequency is less than 1MHz).
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works with a
period of approximately 65ms at 5V. The WDT oscillator
can be disabled by options to conserve power.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
WDTS (09H) Register
Watchdog Timer - WDT
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit ²TO². But in the HALT
mode, the overflow will initialize a ²warm reset², and
only the Program Counter and SP are reset to zero. To
clear the contents of WDT (including the WDT
prescaler), three methods are adopted; external reset (a
low level to RES), software instruction and a ²HALT² instruction. The software instruction include ²CLR WDT²
and the other set - ²CLR WDT1² and ²CLR WDT2². Of
these two types of instruction, only one can be active depending on the option - ²CLR WDT times selection option². If the ²CLR WDT² is selected (i.e. CLRWDT times
equal one), any execution of the ²CLR WDT² instruction
will clear the WDT. In the case that ²CLR WDT1² and
²CLR WDT2² are chosen (i.e. CLRWDT times equal
two), these two instructions must be executed to clear
the WDT; otherwise, the WDT may reset the chip as a
result of time-out.
The clock source of WDT is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), decided by options. This timer is
designed to prevent a software malfunction or sequence
from jumping to an unknown location with unpredictable
results. The Watchdog Timer can be disabled by an option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation.
Once the internal WDT oscillator (RC oscillator with a
period of 65ms at 5V normally) is selected, it is first divided by 256 (8-stage) to get the nominal time-out period of approximately 17ms at 5V. This time-out period
may vary with temperatures, VDD and process variations. By invoking the WDT prescaler, longer time-out
periods can be realized. Writing data to WS2, WS1,
WS0 (bit 2,1,0 of the WDTS) can give different time-out
periods. If WS2, WS1, and WS0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out
period is 2.1s at 5V seconds. If the WDT oscillator is disabled, the WDT clock may still come from the instruction
clock and operate in the same manner except that in the
HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. The high nibble and bit 3 of the
WDTS are reserved for user¢s defined flags, which can
be used to indicate some specified status.
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following...
· The system oscillator will be turned off but the WDT
oscillator keeps running (if the WDT oscillator is selected).
· The contents of the on chip RAM and registers remain
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
S y s te m
unchanged.
· WDT will be cleared and recounted again (if the WDT
clock is from the WDT oscillator).
W D T P r e s c a le r
C lo c k /4
W D T
O S C
O p tio n
S e le c t
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
Rev. 1.10
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February 16, 2007
HT45RM03
· All of the I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal
on port A or a WDT overflow. An external reset causes a
device initialization and the WDT overflow performs a
²warm reset². After the TO and PDF flags are examined,
the reason for chip reset can be determined. The PDF
flag is cleared by system power-up or executing the ²CLR
WDT² instruction and is set when executing the ²HALT²
instruction. The TO flag is set if the WDT time-out occurs,
and causes a wake-up that only resets the program
counter and SP; the others keep their original status.
TO
PDF
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: ²u² means ²unchanged²
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by the options. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it is awakening from an interrupt, two
sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the
program will resume execution at the next instruction. If
the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request
flag is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.
Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other
words, a dummy period will be inserted after wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will enable the SST delay. The functional unit chip reset status
are shown below.
V
D D
0 .0 1 m F *
1 0 0 k W
R E S
1 0 k W
0 .1 m F *
Reset Circuit
Note:
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to
avoid noise interference.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
V D D
R E S
Reset
tS
S T
S S T T im e - o u t
There are three ways in which a reset can occur:
C h ip
· RES reset during normal operation
R e s e t
· RES reset during HALT
Reset Timing Chart
· WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that resets only the program counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions.
Most registers are reset to the ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
H A L T
W a rm
R e s e t
W D T
R E S
O S C 1
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
R e s e t
Reset Configuration
Rev. 1.10
13
February 16, 2007
HT45RM03
An extra option load time delay is added during system reset (power-up, WDT time-out at normal mode or RES reset).
Program Counter
000H
Interrupt
Disable
WDT
Clear. After master reset, WDT begins counting
Timer/Event Counter
Off
Input/Output Ports
Input mode
Stack Pointer
Points to the top of the stack
The registers states are summarized in the following table.
Register
Reset
(Power On)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
000H
000H
000H
000H
000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMR1C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
0011 1111
0011 1111
0011 1111
0011 1111
uuuu uuuu
PCC
Program
Counter
--11 1111
--11 1111
--11 1111
--11 1111
--uu uuuu
PD
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
PDC
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
PWMH
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PWML
---- --00
---- --00
---- --00
---- --00
---- --uu
PWMC
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
MISC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
INTC1
-000 -000
-000 -000
-000 -000
-000 -000
-uuu -uuu
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADRL
x--- ----
x--- ----
x--- ----
x--- ----
u--- ----
ADCR
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
---- --00
---- --00
---- --00
---- --00
---- --uu
CMPC
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
OPAC
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Rev. 1.10
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HT45RM03
TMR0/TMR1 has received a transient from low to high
(or high to low if the T0E/T1E bit is ²0²), it will start counting until the TMR0/TMR1 returns to the original level and
resets the T0ON/T1ON.
Timer/Event Counter
Two timer/event counters (TMR0,TMR1) are implemented in the microcontroller. The Timer/Event Counter
0 and Timer/Event Counter 1 contain 8-bit programmable
count-up counter and the clock may come from an external source or an internal clock source.
The measured result remains in the timer/event counter
even if the activated transient occurs again. In other
words, only 1-cycle measurement can be made until the
T0ON/T1ON is set. The cycle measurement will
re-function as long as it receives further transient pulse.
In this operation mode, the timer/event counter begins
counting not according to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and
issues an interrupt request, as in the other two modes,
i.e., event and timer modes.
There are four registers related to the Timer/Event
Counter 0; TMR0 (0DH), TMR0C (0EH), the
Timer/Event Counter 1; TMR1(10H), TMR1C (11H).
Writing TMR0/TMR1 makes the starting value be placed
in the Timer/Event Counter 0/1 preload register and
reading TMR0/1 get the contents of the Timer/Event
Counter 0/1. The TMR0C and TMR1C are Timer/Event
Counter control register 0/1, which defines the operating
mode, counting enable or disable and an active edge.
To enable the counting operation, the Timer ON bit
(T0ON; bit 4 of the TMR0C or T1ON; bit 4 of the
TMR1C) should be set to ²1². In the pulse width measurement mode, the T0ON/T1ON is automatically
cleared after the measurement cycle is completed. But
in the other two modes, the T0ON/T1ON can only be reset by instructions.
The T0M0/T1M0 and T0M1/T1M1 bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an
external (TMR0, TMR1) pin. The timer mode functions
as a normal timer with the clock source coming from the
internal selected clock source. Finally, the pulse width
measurement mode can be used to count the high or
low level duration of the external signal (TMR0, TMR1),
and the counting is based on the internal selected clock
source.
The overflow of the Timer/Event Counter 0/1 is one of the
wake-up sources and the Timer/Event Counter 0/1 can
also be applied to a PFD (Programmable Frequency Divider) output at PD0 by software control. Only one PFD
(PFD0 or PFD1) can be applied to PD0 by software. No
In the event count or timer mode, the Timer/Event Counter
0/1 starts counting at the current contents in the
timer/event counter and ends at FFH. Once an overflow
occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request
flag (T0F; bit 5 of the INTC1, T1F; bit 6 of the INTC1).
P F D 0
P F D 1
Y S
U
T
X
P F D
Q
P D 0 D a ta C T R L
P F D
In the pulse width measurement mode with the values of
the T0ON/T1ON and T0E/T1E bits equal to ²1², after the
fS
M
S o u r c e O p tio n
PFD Source Option
7 - s ta g e P r e s c a le r
T 0 P S C 2 ~ T 0 P S C 0
D a ta B u s
f IN
8 -1 M U X
T
T 0 M 1
T 0 M 0
T M R 0
8 - b it T im e r /E v e n t C o u n te r R e lo a d
P r e lo a d R e g is te r
T 0 E
8 - b it T im e r /E v e n t
C o u n te r (T M R 0 )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
T 0 M 1
T 0 M 0
T 0 O N
O v e r flo w
to In te rru p t
P F D 0
Timer/Event Counter 0
fS
Y S
7 - s ta g e P r e s c a le r
f IN
8 -1 M U X
T 1 P S C 2 ~ T 1 P S C 0
D a ta B u s
T
T 1 M 1
T 1 M 0
T M R 1
8 - b it T im e r /E v e n t C o u n te r R e lo a d
P r e lo a d R e g is te r
T 1 E
T 1 M 1
T 1 M 0
T 1 O N
8 - b it T im e r /E v e n t
C o u n te r (T M R 1 )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
P F D 1
Timer/Event Counter 1
Rev. 1.10
15
February 16, 2007
HT45RM03
matter what the operation mode is, writing a ²0² to ET0I
or ET1I disables the related interrupt service. When the
PFD function is selected, executing ²SET [PD].0² instruction to enable the PFD output and executing ²CLR
[PD].0² instruction to disable the PFD output.
timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs. When the
timer/event counter (reading TMR0/TMR1) is read, the
clock is blocked to avoid errors, as this may results in a
counting error. Blocking of the clock should be taken
into account by the programmer. It is strongly recommended to load a desired value into the TMR0/TMR1
register first, before turning on the related timer/event
counter, for proper operation since the initial value of
TMR0/TMR1 is unknown. Due to the timer/event
scheme, the programmer should pay special attention
on the instruction to enable then disable the timer for the
first time, whenever there is a need to use the
timer/event function, to avoid unpredictable result.
After this procedure, the timer/event function can be operated normally. The bit0~bit2 of the TMR0C/TMR1C
can be used to define the pre-scaling stages of the internal clock sources of timer/event counter. The definitions
are as shown. The overflow signal of timer/event counter can be used to generate the PFD signal.
In the case of timer/event counter off condition, writing
data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the
timer/event counter is turn-on, data written to the
Bit No.
0~2
Label
3
T0E
4
T0ON
5
¾
6
7
Function
To define the prescaler stages, T0PSC2, T0PSC1, T0PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
T0PSC0~
011: fINT=fSYS/8
T0PSC2
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
T0M0
T0M1
To define the TMR0 active edge of Timer/Event Counter 0
(0=active on low to high; 1=active on high to low)
To enable or disable Timer 0 counting (0=disabled; 1=enabled)
Unused bit, read as ²0²
To define the operating mode, T0M1, T0M0=
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C (0EH) Register
Bit No.
0~2
Label
To define the prescaler stages, T1PSC2, T1PSC1, T1PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
T1PSC0~
011: fINT=fSYS/8
T1PSC2
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
3
T1E
4
T1ON
5
¾
6
7
Function
T1M0
T1M1
To define the TMR1 active edge of Timer/Event Counter 1
(0=active on low to high; 1=active on high to low)
To enable or disable Timer 1 counting (0=disabled; 1=enabled)
Unused bit, read as²0²
To define the operating mode, T1M1, T1M0=
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C (11H) Register
Rev. 1.10
16
February 16, 2007
HT45RM03
enable the PFD output function and writing ²0² will force
the PD0 to remain at ²0². The I/O functions of PD0 are
shown below.
Input/Output Ports
There are 23 bidirectional input/output lines in the
microcontroller, labeled as PA, PB, PC and PD, which
are mapped to the data memory of [12H], [14H], [16H]
and [18H] respectively. All of these I/O ports can be
used for input and output operations. For input operation, these ports are non-latching, that is, the inputs
must be ready at the T2 rising edge of instruction ²MOV
A,[m]² (m=12H, 14H, 16H or 18H). For output operation,
all the data is latched and remains unchanged until the
output latch is rewritten.
I/O
I/P
Mode (Normal)
Note:
I/P
(PFD)
O/P
(PFD)
Logical
Output
Logical
Input
PFD
(Timer on)
The PFD frequency is the timer/event counter
overflow frequency divided by 2.
The PA4, PA5, PA6, PA7 and PB7 are pin-shared with
INT0A, INT0B, INT0C, INT1 and TMR0/TMR1 pins respectively. The CVINN and COUT are pin-shared with
PA1, PA2 and PA3. Once the Comparator function is
used, the internal registers related to PA1, PA2 cannot
be used, PA3 can be used as input only (if the COUTEN
is ²1²), and the PA1, PA2 I/O function, PA3 output function and pull-high resistor are disabled automatically(if
the COUTEN is ²1²). Once the Comparator function is
used, the PA3 is the GPIO when the COUTEN is ²0².
Software instructions determine the Comparator function to be used.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, CMOS output or schmitt trigger input with or without pull-high resistor structures can
be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding
latch of the control register must write ²1². The input
source also depends on the control register. If the control register bit is ²1², the input will read the pad state. If
the control register bit is ²0², the contents of the latches
will move to the internal bus. The latter is possible in the
²read-modify-write² instruction.
CMPEN COUTEN
0
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H and 19H.
1
After a chip reset, these input/output lines remain at high
levels or floating state (dependent on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,
16H or 18H) instructions.
1
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
PA1, PA2, PA3
X
PA1, PA2, PA3 is GPIO
0
PA1, PA2 is Comparator input pin
and PA3 is GPIO. PA3 falling
edge can generate the
Comparator interrupt.
1
PA1, PA2 is comparator input pin
and PA3 is Comparator output
pin. PA3 can read the
Comparateor output status.
The OPVINP, OPVINN and OPOUT are pin-shared with
PA0, PB3/AN3 and PB2/AN2 respectively. Once the
OPA function is used, the internal registers related to
PA0, PB3 and PB2 cannot be used, and the I/O function
and pull-high resistor are disabled automatically. Software instructions determine the OPA function to be
used.
Each line of port A has the capability of waking-up the
device. The highest 7-bit of port D are not physically implemented; on reading them a ²0² is returned whereas
writing then results in a no-operation. See Application
note.
Each I/O port has a pull-high option. Once the pull-high
option is selected, the I/O port has a pull-high resistor,
otherwise, there¢s none. Take note that a non-pull-high
I/O port operating in input mode will cause a floating
state.
OPAEN
PA0, PB3/AN3, PB2/AN2
0
PA0 is GPIO and PB2/AN2, PB3/AN3 is
GPIO or analog ADC input by ADCR register.
1
PA0, PB3/AN3 is OPA input pin and
PB2/AN2 is OPA output pin. The PB2/AN2
and PB3/AN3 can be analog ADC input if
the related ADC function is enabled.
The PB can also be used as A/D converter inputs. The
A/D function will be described later. Once a PB line is selected as an A/D input (by using software control), the
I/O function and pull-high resistor are disabled automatically.
The PD0 is pin-shared with the PFD signal. If the PFD
function is selected, the output signal in output mode of
PD0 will be the PFD signal generated by the timer/event
counter overflow signal. The input mode is always remaining its original functions. Once the PFD option is
selected, the PFD output signal is controlled by PD0
data register only. Writing ²1² to PD0 data register will
Rev. 1.10
Logical
Input
PD0
O/P
(Normal)
The PWM0~PWM2 and PWM0~PWM2 output function
are pin-shared with PC0, PC2, PC4 and PC1, PC3, PC5
respectively by software control.
17
February 16, 2007
HT45RM03
²0² will force the PC0/PC2/PC4 to remain at ²0² (inactive state). Writing ²1² to PC1/PC3/PC5 data register will
enable the PWM0/PWM1/PWM2 output function and
writing ²0² will force the PC1/PC3/PC5 to remain at ²0²
inactive state). The I/O functions of PC0~PC5 are as
shown.
There is a PWM function shared with PC0~PC5. If the
PWM function is enabled, the PWM0~PWM2 and
PWM0~PWM2 signal will appear on PC0, PC2, PC4
and PC1, PC3, PC5 respectively (if PC0/PC1/PC2/PC3/
PC4/PC5 is operating in output mode).
Writing ²1² to PC0/PC2/PC4 data register will enable
the PWM0/PWM1/PWM2 output function and writing
PWMEN
PC7
PC6
PC4
PC2
PC0
0
X
X
Logical
Logical
Logical
1
0
0
Logical
Logical
PWM
1
0
1
Logical
PWM
Logical
1
1
0
PWM
Logical
Logical
1
1
1
PWM
PWM
PWM
PC3
PC1
Logical
PC0, PC2, PC4 Output Function
PWMCEN
PC7
PC6
PC5
0
X
X
Logical
Logical
1
0
0
Logical
Logical
PWM
1
0
1
Logical
PWM
Logical
1
1
0
PWM
Logical
Logical
1
1
1
PWM
PWM
PWM
PC1, PC3, PC5 Output Function
There is only one channel PWM and PWM output at a time. The PC.6 and PC.7 is to determine which PWM0/PWM0,
PWM1/PWM1 or PWM2/PWM2 appeared to the PC0/PC1, PC2/PC3 or PC4/PC5.
PC7, PC6
PWM (PWMEN=1)
PWM (PWMCEN=1)
0, 0
PC0/PWM0 is PWM output, if the PC0 is output
mode (PCC.0 = ²0²). The PC2 and PC4 are the
GPIO. Writing ²1² to PC0 data register will enable
the PWM0 output function and writing ²0² will force
the PC0 to remain at PWM0 output inactive state.
PC1/PWM0 is PWM output, if the PC1 is output
mode (PCC.1 = ²0²). The PC3 and PC5 are the
GPIO. Writing ²1² to PC1 data register will enable
the PWM0 output function and writing ²0² will force
the PC1 to remain at PWM0 output inactive state.
0, 1
PC2/PWM1 is PWM output, if the PC2 is output
mode (PCC.2 = ²0²). The PC0 and PC4 are the
GPIO. Writing ²1² to PC2 data register will enable
the PWM1 output function and writing ²0² will force
the PC2 to remain at PWM1 output inactive state.
PC3/PWM1 is PWM output, if the PC3 is output
mode (PCC.3 = ²0²). The PC1 and PC5 are the
GPIO. Writing ²1² to PC3 data register will enable
the PWM1 output function and writing ²0² will force
the PC3 to remain at PWM1 output inactive state.
1, 0
PC4/PWM2 is PWM output, if the PC4 is output
mode (PCC.4 = ²0²). The PC0 and PC2 are the
GPIO. Writing ²1² to PC4 data register will enable
the PWM2 output function and writing ²0² will force
the PC4 to remain at PWM2 output inactive state.
PC5/PWM2 is PWM output, if the PC5 is output
mode (PCC.5 = ²0²). The PC1 and PC3 are the
GPIO. Writing ²1² to PC5 data register will enable
the PWM2 output function and writing ²0² will force
the PC5 to remain at PWM2 output inactive state.
1, 1
PC0/PWM0, PC2/PWM1 and PC4/PWM2 are
PWM output, if the PC0, PC2 and PC4 are output
mode (PCC.0, 2, 4 = ²0²). Writing ²1² to
PC0/PC2/PC4 data register will enable the
PWM0/PWM1/PWM2 output function and writing
²0² will force the PC0/PC2/PC4 to remain at PWM
output inactive state.
PC1/PWM0, PC3/PWM1 and PC5/PWM2 are
PWM output, if the PC1, PC3 and PC5 are output
mode (PCC.1, 3, 5 = ²0²). Writing ²1² to
PC1/PC3/PC5 data register will enable the
PWM0/PWM1/PWM2 output function and writing
²0² will force the PC1/PC3/PC5 to remain at PWM
output inactive state.
Note:
If PWMEN=0, the PWM function output is disable and the PC0, PC2 and PC4 are the GPIO.
If PWMCEN=0, the PWM function output is disable and the PC1, PC3 and PC5 are the GPIO.
The PWMEN and PWMCEN are independent to enable or disable the PWM and PWM Complement function.
If the PCC.x is ²1², the PC.x is input mode. ²x² is from 0~5.
Rev. 1.10
18
February 16, 2007
HT45RM03
It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid
consuming power under input floating state.
V
D a ta B u s
W r ite C o n tr o l R e g is te r
C o n tr o l B it
P u ll- h ig h
Q
D
Q
C K
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
D a ta B it
Q
D
C K
S
Q
M
P C 0 /P C 1 /P C 2 /P C 3 /P C 4 /P C 5 /P D 0
P W M 0 /P W M 0 /P W M 1 /P W M 1 /P W M 2 /P W M 2 /P F D
M
R e a d D a ta R e g is te r
S y s te m
IN T 0 A
IN T 0 B
IN T 0 C
IN T 1
T M R 0 /T M R 1
fo
fo
fo
fo
fo
U
A 4
A 5
A 6
A 7
O n
O n
O n
O n
B 7 O n
X
P A
P A
P A
P A
P A
P A
P A
P A
P B
P B
P B
P B
P B
P C
P C
P C
P C
P C
P C
P D
0 /O
1 /C
2 /C
3 /C
4 /IN
5 /IN
6 /IN
7 /IN
0 /A
2 /A
3 /A
4 /A
7 /A
0 /P
1 /P
2 /P
3 /P
4 /P
5 /P
0 /P
P V IN
V IN P
V IN N
O U T
T 0 A
T 0 B
T 0 C
T 1
N 0 ~ P
N 2 /O
N 3 /O
N 4 ~ P
N 7 /T
W M 0
W M 0
W M 1
W M 1
W M 2
W M 2
F D
P
B 1
P O
P V
B 6
M R
/A N 1
U T
IN N
/A N 6
0 /T M R 1
X
W a k e -u p
( P A o n ly )
r P
r P
r P
r P
r P
U
D D
O P 0 ~ O P 7
ly
ly
ly
ly
ly
Input/Output Ports
function of PC0~PC5 is enabled (PCC.0 ~ PCC.5 = ²0²),
writing ²1² to PC0, PC2 and PC4 register will enable the
PWM output function and writing ²0² will force the PC0,
PC2 and PC4 stay at inactive state (²0² if the PWMLEV
option is select active high). Writing ²1² to PC1, PC3 and
PC5 register will enable the Complementary PWM output function and writing ²0² will force the PC1, PC3 and
PC5 stay at inactive state (²0² if the PWMCLEV option is
select active high).
PWM
The microcontroller is provided with three channel PWM
and Complementary PWM output shared with
PC0~PC5, named PWM0~PWM2 and PWM0~PWM2,
with standard 10 bits output, (9+1), (8+2), or (7+3) mode
(configuration option determined). The PWM function
provides output with a varied frequency and duty cycle
by setting particular values into PWMC and PWML,
PWMH registers. The frequency source of the PWM
counter comes from fPWM. The fPWM clock source can be
chosen from fSYS~fSYS/8 (software option determined).
The PWM clock source can be chosen form fSYS~fSYS/8
(dependent on software option). When the fPWM clock
source is selected from fSYS~fSYS/8, the PWM function
provides with a fixed frequency output (fSYS/1024~
(fSYS/8192). The PWM output provides standard 10-bit,
(9+1), (8+2) and (7+3) output mode, it¢s duty cycle is decided by writing to the PWMH and PWML registers, the
waveform of PWM output is as shown.
The PWM channel has their data registers denoted as
PWMH (1AH) and PWML (1BH). These two registers
define the PWM output duty cycle. The PWMH is an
8-bit register, and it is a higher-order data register, the
PWML is a lower-order register and two bits (bit1~bit0)
are provided in this register. The PWM duty cycle is
specified by writing to these two PWM data registers,
writing PWML will only put the written data to an internal
lower-order byte buffer (2-bit) and writing PWMH will
transfer the specified data and the contents of the
lower-order byte buffer to PWMH and PWML registers,
respectively. Once the PC0~PC5 is selected as the
PWM and Complementary PWM outputs and the output
Rev. 1.10
When the PWM output function is enabled (writing ²1² to
PC0~PC5 register, when PWM and Complementary
PWM output function is enable) and the fPWM clock
source is selected from PWM prescaler, the value of
PWMPSC0~PWMPSC1, PWML and PWMH can be
written to at any time even if the PWM and Complementary PWM output is running.
19
February 16, 2007
HT45RM03
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWMH
D9
D8
D7
D6
D5
D4
D3
D2
PWML
¾
¾
¾
¾
¾
¾
D0
D1
PWMH (1AH), PWML (1BH) Register
A (9+1) bits mode PWM cycle is divided into two modulation cycles (modulation cycle 0~modulation cycle 1). Each
modulation cycle has 512 PWM input clock period. In a (9+1) bit PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM registers are denoted by DC which are the values of PWMH.7~PWMH.0
and PWML.1 (9 bit from PWMH~PWML.1). The group 2 is denoted by AC which is the value of PWML.0. In a (9+1) bits
mode PWM cycle, the duty cycle of each modulation cycle is shown in the table.
Parameter
AC0~AC1
Duty Cycle
i<AC
(DC+1)/512
i³AC
DC/512
Modulation Cycle I (i=0~1)
A (8+2) bits mode PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3). Each
modulation cycle has 256 PWM input clock period. In a (8+2) bit PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWMH.7~PWMH.0. The
group 2 is denoted by AC which is the value of PWML.1~PWML.0 (PWML). In a (8+2) bits mode PWM cycle, the duty
cycle of each modulation cycle is shown in the table.
Parameter
AC0~AC3
Duty Cycle
i<AC
(DC+1)/256
i³AC
DC/256
Modulation Cycle I (i=0~3)
A (7+3) bits mode PWM cycle is divided into eight modulation cycles (modulation cycle 0~modulation cycle 7). Each
modulation cycle has 128 PWM input clock period. In a (7+3) bit PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWMH.7~PWMH.1. The
group 2 is denoted by AC which are the value of PWMH.0 and PWML.1~PWML.0 (PWMH.0~PWML.0). In a (7+3) bits
mode PWM cycle, the duty cycle of each modulation cycle is shown in the table.
Parameter
AC0~AC7
Duty Cycle
i<AC
(DC+1)/128
i³AC
DC/128
Modulation Cycle I (i=0~7)
The modulation frequency, cycle frequency and cycle duty of the PWM output signal are summarized in the following
table.
PWM Modulation Frequency
PWM Cycle Frequency
PWM Cycle Duty
fPWM/1024 for standard 10-bits mode
fPWM/512 for (9+1) bits mode
fPWM/256 for (8+2) bits mode
fPWM/128 for (7+3) bits mode
fPWM/1024
[PWM]/1024
fP
W M
/2
[P W M ] = 1 0 0
P W M
1 0 0 /1 0 2 4
P W M
1 0 0 /1 0 2 4
M o d u la tio n P e r io d : 1 0 2 4 /fP
P W M
F u ll C y c le : 1 0 2 4 /fP
1 0 0 /1 0 2 4
W M
W M
Standard 10 Bit PWM Mode
Rev. 1.10
20
February 16, 2007
HT45RM03
fP
W M
/2
[P W M ] = 1 0 0
P W M
5 0 /5 1 2
5 0 /5 1 2
5 0 /5 1 2
5 1 /5 1 2
5 0 /5 1 2
5 1 /5 1 2
5 1 /5 1 2
5 1 /5 1 2
5 1 /5 1 2
5 1 /5 1 2
5 2 /5 1 2
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
5 2 /5 1 2
P W M
M o d u la tio n P e r io d : 5 1 2 /fP
W M
P W M
C y c le : 1 0 2 4 /fP
W M
(9+1) PWM Mode
fP
W M
/2
[P W M ] = 1 0 0
P W M
2 5 /2 5 6
2 5 /2 5 6
2 5 /2 5 6
2 5 /2 5 6
2 5 /2 5 6
2 6 /2 5 6
2 5 /2 5 6
2 5 /2 5 6
2 5 /2 5 6
2 6 /2 5 6
2 6 /2 5 6
2 6 /2 5 6
2 5 /2 5 6
2 5 /2 5 6
2 6 /2 5 6
2 6 /2 5 6
2 6 /2 5 6
2 5 /2 5 6
2 6 /2 5 6
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
2 6 /2 5 6
P W M
M o d u la tio n P e r io d : 2 5 6 /fP
W M
P W M
F u ll P e r io d : 1 0 2 4 /fP
W M
(8+2) PWM Mode
fP
W M
/2
[P W M ] = 1 1 2
P W M
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 5 /1 2 8
1 4 /1 2 8
1 5 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 4 /1 2 8
1 4 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
1 4 /1 2 8
1 5 /1 2 8
1 5 /1 2 8
[P W M ] = 1 1 3
P W M
1 5 /1 2 8
[P W M ] = 1 1 4
P W M
1 5 /1 2 8
[P W M ] = 1 1 5
P W M
1 5 /1 2 8
[P W M ] = 1 1 6
P W M
1 5 /1 2 8
[P W M ] = 1 1 7
P W M
1 5 /1 2 8
[P W M ] = 1 1 8
P W M
1 5 /1 2 8
[P W M ] = 1 1 9
P W M
1 5 /1 2 8
P W M
M o d u la tio n P e r io d : 1 2 8 /fP
W M
P W M
F u ll P e r io d : 1 0 2 4 /fP
W M
(7+3) PWM Mode
Rev. 1.10
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February 16, 2007
HT45RM03
PWM and Complementary PWM output channels are
shown below.
PWMCEN
PC7
PC6
PWM
0
X
X
Disable PWM0,
PWM1, PWM2
PWMEN
PC7
PC6
PWM
0
X
X
Disable PWM0,
PWM1, PWM2
1
0
0
Enable PWM0
1
0
1
Enable PWM1
1
0
0
Enable PWM0
1
1
0
Enable PWM2
1
0
1
Enable PWM1
1
1
0
Enable PWM2
1
Enable PWM0,
PWM1, PWM2
1
1
1
Enable PWM0,
PWM1, PWM2
1
1
The PWM period interrupt will occur, when PWM counter is overflow. The PWM period interrupt is shown below.
PWM and Complementary PWM output are shown below.
P C
P C
0 :
1 :
0 ,
1 ,
P W
P W
P C
P C
M
M
2 o r P C 4
3 o r P C 5
In a c tiv e
A c tiv e
P W M 0 , P W M 1 o r P W M 2
P W M 0 , P W M 1 o r P W M 2
P C
P C
0 :
1 :
0 ,
1 ,
P W
P W
P C
P C
M
M
2 o r P C 4
3 o r P C 5
In a c tiv e
A c tiv e
P W M 0 , P W M 1 o r P W M 2
P W M 0 , P W M 1 o r P W M 2
PWM and Complementary PWM Output Without Dead Time (PWMLEV & PWMCLEV = ²0² & ²0²)
P C
P C
0 :
1 :
0 ,
1 ,
P W
P W
P C
P C
M
M
2 o r P C 4
3 o r P C 5
In a c tiv e
A c tiv e
P W M 0 , P W M 1 o r P W M 2
P W M 0 , P W M 1 o r P W M 2
P C
P C
0 :
1 :
0 ,
1 ,
P W
P W
P C
P C
M
M
2 o r P C 4
3 o r P C 5
In a c tiv e
A c tiv e
P W M 0 , P W M 1 o r P W M 2
P W M 0 , P W M 1 o r P W M 2
PWM and Complementary PWM Output Without Dead Time (PWMLEV & PWMCLEV = ²0² & ²1²)
Rev. 1.10
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February 16, 2007
HT45RM03
P C
P C
0 :
1 :
0 ,
1 ,
P W
P W
P C
P C
M
M
2 o r P C 4
3 o r P C 5
In a c tiv e
A c tiv e
P W M 0 , P W M 1 o r P W M 2
P W M 0 , P W M 1 o r P W M 2
P C
P C
0 :
1 :
0 ,
1 ,
P W
P W
P C
P C
M
M
2 o r P C 4
3 o r P C 5
In a c tiv e
A c tiv e
P W M 0 , P W M 1 o r P W M 2
P W M 0 , P W M 1 o r P W M 2
PWM and Complementary PWM Output Without Dead Time (PWMLEV & PWMCLEV = ²1² & ²0²)
P C
P C
0 :
1 :
0 ,
1 ,
P W
P W
P C
P C
M
M
2 o r P C 4
3 o r P C 5
In a c tiv e
A c tiv e
P W M 0 , P W M 1 o r P W M 2
P W M 0 , P W M 1 o r P W M 2
P C
P C
0 :
1 :
0 ,
1 ,
P W
P W
P C
P C
M
M
2 o r P C 4
3 o r P C 5
In a c tiv e
A c tiv e
P W M 0 , P W M 1 o r P W M 2
P W M 0 , P W M 1 o r P W M 2
PWM and Complementary PWM Output Without Dead Time (PWMLEV & PWMCLEV = ²1² & ²1²)
The Complementary PWM output provides with dead time function. The dead time is from fSYS/2~fSYS/16. The CompleP C
P C
0 :
1 :
0 ,
1 ,
P W
P W
P C
P C
M
M
2 o r P C 4
3 o r P C 5
In a c tiv e
A c tiv e
P W M
P e r io d
P W M
D u ty
P W M 0 , P W M 1 o r P W M 2
P W M 0 , P W M 1 o r P W M 2
P W M
In te rru p t
PWM and Complementary PWM Output Without Dead Time (PWMLEV & PWMCLEV = ²0² & ²0²)
Rev. 1.10
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February 16, 2007
HT45RM03
mentary PWM output with dead time is shown below.
P C
P C
0 :
1 :
0 ,
1 ,
P W
P W
P C
P C
M
M
D T
2 o r P C 4
3 o r P C 5
In a c tiv e
A c tiv e
P W M
D T
P e r io d
P W M 0 , P W M 1 o r P W M 2
P W M 0 , P W M 1 o r P W M 2
P W M
D u ty
PWM and Complementary PWM Output With Dead Time (PWMLEV & PWMCLEV = ²0² & ²0²)
Bit No.
Label
Function
0
PWMEN
1
PWMCEN
To enable/disable PWM output (0=disabled; 1=enabled)
2
DTEN
3
4
5
PWMPS0
PWMPS1
PWMPS2
These three bits select the PWM clock prescaler rate.
6
7
PWMDT0
PWMDT1
These two bits select the PWM Complementary output dead time
To enable/disable PWM Complementary output (0=disabled; 1=enabled)
To enable/disable PWM Complementary output with dead time
(0=without dead time; 1=with dead time)
PWMC (1CH) Register
The bits 3~5 of the PWM control register (PWMC) can be used to define the pre-scaling stages of the PWM clock.
PWMPS2
PWMPS1
PWMPS0
To Define the Prescaler Stages
0
0
0
fPWM=fSYS
0
0
1
fPWM=fSYS/2
0
1
0
fPWM=fSYS/4
0
1
1
fPWM=fSYS/8
1
0
0
fPWM=fSYS/16
1
0
1
fPWM=fSYS/32
1
1
0
fPWM=fSYS/64
1
1
1
fPWM=fSYS/128
PWM period according different PWM prescaler rate bits and system clock.
PWMPS2
PWMPS1
PWMPS0
fSYS=4MHz
fSYS=8MHz
fSYS=12MHz
0
0
0
3.91
7.81
11.72
0
0
1
1.95
3.91
5.86
0
1
0
0.98
1.95
2.93
0
1
1
0.49
0.98
1.46
1
0
0
0.24
0.49
0.73
1
0
1
0.12
0.24
0.37
1
1
0
0.06
0.12
0.18
1
1
1
0.03
0.06
0.09
Unit
kHz
10-bit PWM Full Frequency (fSYS is 4, 8, 12MHz)
Rev. 1.10
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February 16, 2007
HT45RM03
The bits 7~6 of the PWM control register (PWMC) can be used to define the PWM Complementary output dead time.
PWMDT1
PWMDT0
To Define the PWM Complementary Output Dead Time
0
0
Dead Time=fSYS/2
0
1
Dead Time=fSYS/4
1
0
Dead Time=fSYS/8
1
1
Dead Time=fSYS/16
PWMDT1
PWMDT0
fSYS=4MHz
fSYS=8MHz
fSYS=12MHz
0
0
0.50
0.25
0.17
0
1
1.00
0.50
0.33
1
0
2.00
1.00
0.67
1
1
4.00
2.00
1.33
Unit
ms
Dead Time Setting (fSYS is 4, 8, 12MHz)
PWM Options
There are two options to define the PWM and PWM Complementary output level. These two bits can be read by software.
Options
Description
PWM output level selection;
PWMLEV.
This option is to determine the PWM output level. Active Low or Active High
selection. Disable this bit to ²0², the PWM output will be defined as an active
high output, Enable this bit to ²1², the PWM output will be defined as an active low output. If the PWM function disable, this bit is invalid.
This option is to determine the PWM Complementary output level. Active low
or active high selection. Disable this bit to ²0², the PWM Complementary outPWM Complementary output level
put will be defined as an active high output, Enable this bit to ²1², the PWM
selection; PWMCLEV.
Complementary output will be defined as an active low output. If the PWM
Complementary function disable, this bit is invalid.
P C 0 /P W M 0
P W M
P W M H
P W M L
O u tp u t
P W M C T R L , P C 7 ,
P C 6 , P W M L E V
P W M
P W M
P W M
P C 2 /P W M 1
P C 4 /P W M 2
P e r io d In te r r u p t
D e a d T im e C o n tr o l
P W M
P W M E N
P W M
C o m p le m e n ta r y O u tp u t
P W M C T R L , P C 7 ,
P C 6 , P W M C L E V
P W M C E N
P C 1 /P W M 0
P C 3 /P W M 1
P C 5 /P W M 2
PWM
Rev. 1.10
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February 16, 2007
HT45RM03
A/D Converter
The 8 channels and 9-bit resolution A/D converter are implemented in this microcontroller. The reference voltage is
VDD. The A/D converter contains 4 special registers which are; ADRL (20H), ADRH (21H), ADCR (22H) and ACSR
(23H). The ADRH and ADRL are A/D result register higher-order byte and lower-order byte and are read-only. After the
A/D conversion is completed, the ADRH and ADRL should be read to get the conversion result data. The ADCR is an
A/D converter control register, which defines the A/D channel number, analog channel select, start A/D conversion control bit and the end of A/D conversion flag. If the users want to start an A/D conversion, define PB configuration, select
the converted analog channel, and give START bit a raising edge and falling edge (0®1®0). At the end of A/D conversion, the EOCB bit is cleared and an A/D converter interrupt occurs (if the A/D converter interrupt is enabled). The
ACSR is A/D clock setting register, which is used to select the A/D clock source.
The A/D converter control register is used to control the A/D converter. The bit2~bit0 of the ADCR are used to select an
analog input channel. There are a total of eight channels to select. The bit5~bit3 of the ADCR are used to set PB configurations. PB can be an analog input or as digital I/O line decided by these 3 bits. Once a PB line is selected as an analog input, the I/O functions and pull-high resistor of this I/O line are disabled and the A/D converter circuit is power on.
The EOCB bit (bit6 of the ADCR) is end of A/D conversion flag. Check this bit to know when A/D conversion is completed. The START bit of the ADCR is used to begin the conversion of the A/D converter. Giving START bit a rising edge
and falling edge means that the A/D conversion has started. In order to ensure the A/D conversion is completed, the
START should remain at ²0² until the EOCB is cleared to ²0² (end of A/D conversion).
Bit No.
Label
0
1
ADCS0
ADCS1
2~7
¾
Function
Selects the A/D converter clock source
00= system clock/2
01= system clock/8
10= system clock/32
11= undefined
Unused bit, read as ²0²
ACSR (23H) Register
Bit No.
Label
0
1
2
ACS0
ACS1
ACS2
Function
Defines the analog channel select.
3
4
5
PCR0
PCR1
PCR2
Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all 0, the ADC circuit is
power off to reduce power consumption
6
EOCB
Indicates end of A/D conversion. (0 = end of A/D conversion)
Each time bits 3~5 change state the A/D should be initialized by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See ²Important note for A/D initialization².
7
START
Starts the A/D conversion. (0®1®0= start; 0®1= Reset A/D converter and set EOCB to ²1²)
ADCR (22H) Register
PCR2
PCR1
PCR0
7
6
5
4
3
2
1
0
0
0
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
0
0
1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
AN0
0
1
0
PB7
PB6
PB5
PB4
PB3
PB2
AN1
AN0
0
1
1
PB7
PB6
PB5
PB4
PB3
AN2
AN1
AN0
1
0
0
PB7
PB6
PB5
PB4
AN3
AN2
AN1
AN0
1
0
1
PB7
PB6
PB5
AN4
AN3
AN2
AN1
AN0
1
1
0
PB7
PB6
AN5
AN4
AN3
AN2
AN1
AN0
1
1
1
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Port B Configuration
Rev. 1.10
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February 16, 2007
HT45RM03
ACS2
ACS1
ACS0
Analog Channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
Analog Input Channel Selection
Bit1 and bit0 of the ACSR register are used to select the A/D clock source.
When the A/D conversion has completed, the EOCB bit will be cleared. The EOCB bit is set to ²1² when the START bit
is set from ²0² to ²1².
Important Note for A/D initialization:
Special care must be taken to initialize the A/D converter each time the Port B A/D channel selection bits are modified,
otherwise the EOCB flag may be in an undefined condition. An A/D initialization is implemented by setting the START
bit high and then clearing it to zero within 10 instruction cycles of the Port B channel selection bits being modified. Note
that if the Port B channel selection bits are all cleared to zero then an A/D initialization is not required.
Register
Bit7
ADRL
D0
¾
¾
¾
¾
¾
¾
¾
ADRH
D8
D7
D6
D5
D4
D3
D2
D1
Note:
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
D0~D8 is A/D conversion result data bit LSB~MSB.
ADRL (20H), ADRH (21H) Register
The following two programming examples illustrate how to setup and implement an A/D conversion. In the example,
the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete.
Example: using EOCB Polling Method to detect end of conversion
mov
a,00000001B
mov
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
a,00100000B
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov
ADCR,a
; and select AN0 to be connected to the A/D converter
:
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
START
set
START
; reset A/D
clr
START
; start A/D
Rev. 1.10
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February 16, 2007
HT45RM03
Polling_EOC:
sz
EOCB
; poll the ADCR register EOCB bit to detect end of A/D conversion
jmp
polling_EOC
; continue polling
mov
a,ADRH
; read conversion result high byte value from the ADRH register
mov
adrh_buffer,a
; save result to user defined memory
mov
a,ADRL
; read conversion result low byte value from the ADRL register
mov
adrl_buffer,a
; save result to user defined memory
:
:
jmp
start_conversion
M in im u m
; start next A/D conversion
o n e in s tr u c tio n c y c le n e e d e d , M a x im u m
te n in s tr u c tio n c y c le s a llo w e d
S T A R T
E O C B
A /D s a m p lin g tim e
tA D C S
P C R 2 ~
P C R 0
0 0 0 B
A /D
tA
s a m p lin g tim e
A /D
tA
D C S
1 0 0 B
1 0 0 B
s a m p lin g tim e
D C S
1 0 1 B
0 0 0 B
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 2 ~
A C S 0
0 0 0 B
P o w e r-o n
R e s e t
0 1 0 B
0 0 0 B
0 0 1 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
1 : D e fin e P B c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
tA D C
A /D c o n v e r s io n tim e
N o te :
A /D
tA D
tA
C S
D C
c lo c k m u s t b e fS
= 3 2 tA D
= 7 6 tA D
Y S
/2 , fS
Y S
/8 o r fS
Y S
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
d o n 't c a r e
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
/3 2
A/D Conversion Timing
Comparator
The CVINP, CVINN and COUT are pin-shared with PA1,
PA2 and PA3. Once the Comparator function is used,
the internal registers related to PA1, PA2 cannot be
used, PA3 can be used as input only( if the COUTEN is
²1²), and the PA1, PA2 I/O function, PA3 output function
and pull-high resistor are disabled automatically(if the
COUTEN is ²1²). Once the Comparator function is used,
the PA3 is the GPIO when the COUTEN is ²0². Software
instructions determine the Comparator function to be
used.
There is one Comparator in the device. The CMPEN bits
is used as the enable or disable bits, if the CMPEN is
cleared to ²0², the Comparator is disabled, the
PA1/CVINP, PA2/CVINN, PA3/COUT are all GPIO pins,
if the CMPEN is set to ²1², the Comparator is enabled,
the PA1/CVINP, PA2/CVINN are Comparator input pins,
PA3/COUT is a Comparator output pin.
P A 1 /C V IN P
P A 2 /C V IN N
P A 3 /C O U T
S 1
S 2
C M P O P
In te rru p t
S 3
C O F 0 ~ C O F 3
C M P E N
C R S
0
0
1
1
C O F M
0
1
0
1
S 1
O N
O F F
O N
O N
S 2
O N
O N
O N
O F F
S 3
O F F
O N
O F F
O N
Comparator Block Diagram
Rev. 1.10
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February 16, 2007
HT45RM03
Bit No.
0~3
Label
Function
COF0~COF3 Comparator input offset voltage cancellation control bits
Comparator input offset voltage cancellation reference selection bit
1/0: select CVINP/CVINN as the reference input
4
CRS
5
COFM
6
CMPOP
Comparator output; positive logic. This bit is read only.
7
CMPEN
Comparator enable/disable (1/0)
Input offset voltage cancellation mode and comparator mode selection
1/0: input offset voltage cancellation mode/comparator mode
CMPC Register (Comparator Control Register)
CMPEN
COUTEN
0
X
PA1, PA2, PA3 is GPIO
PA1, PA2, PA3
1
0
PA1, PA2 is Comparator input pin and PA3 is GPIO.
1
1
PA1, PA2 is Comparator input pin and PA3 is Comparator output pin.
PA3 can read the Comparator output status.
The Comparator enable/disable register, Comparator output pin enable/disable register and Comparator output flag
are shown below.
PA3/COUT selection
COUTEN 0: PA3/COUT is as a GPIO pin
1: PA3/COUT is Comparator output, and the status of COUT can be read by reading the PA3 register.
The Comparator can be used for stopping the PWM by PWWSP0 and PWMSP1 register, which are shown below. The
stopping PWM is used to clear the PWMCTRL bit to ²0².
Stopping the PWMand PWM using hardware selection. The stopping PWM method is to clear PWMCTRL
PWMSP0 bit to ²0² by hardware.
00: PWM module output can be stop by software control only
01: PWM module output can be stop by COUT falling edge
PWMSP1 10: PWM module output can be stop by INT1 interrupt
11: PWM module output can be stop by COUT falling edge or by INT1 interrupt
OPA (Operation Amplifier)
The OPA can be disabled or enabled by software control.
There is one OPA in the device. This OPA can be used
for amplifier by user requirement. The OPAEN bits is
used as the enable or disable bits, if the OPAEN is
cleared to ²0², the OPA is disabled and power off to save
power consumption, the PB2/AN2/OPOUT, PB3/AN3/
OPVINN, PA0/OPVINP are all GPIO pins, if the OPAEN
is set to ²1², the OPA is enabled, the PB3/AN3/OPVINN
and PA0/OPVINP are OPA inverting and non-inverting
input pins, PB2/AN2/OPOUT is a OPA output pin, PB2,
PB3, PA0 output and pull-high resistor are disabled.
P A 0 /O P V IN P
P B 3 /A N 3 /O P V IN N
P B 2 /A N 2 /O P O U T
The OPVINP, OPVINN and OPOUT are pin-shared with
PA0, PB3/AN3 and PB2/AN2 respectively. Once the
OPA function is used, the internal registers related to
PA0, PB3 and PB2 cannot be used, and the I/O function
and pull-high resistor are disabled automatically. Software instructions determine the OPA function to be
used.
S 1
S 2
O P A O P
S 3
A O F 0 ~ A O F 3
O P A E N
A R S
0
0
1
1
A O F M
0
1
0
1
S 1
O N
O F F
O N
O N
S 2
O N
O N
O N
O F F
S 3
O F F
O N
O F F
O N
Operational Amplifier Block Diagram
Rev. 1.10
29
February 16, 2007
HT45RM03
Bit No.
0~3
Label
Function
AOF0~AOF3 Operational amplifier input offset voltage cancellation control bits
Operational amplifier input offset voltage cancellation reference selection bit
1/0: select OPP/OPN as the reference input
4
ARS
5
AOFM
6
OPAOP
Operational amplifier output; positive logic. This bit is read only.
7
OPAEN
Operational amplifier enable/disable (1/0)
Input offset voltage cancellation mode and operational amplifier mode selection
1/0: input offset voltage cancellation mode/operational amplifier mode
OPAC Register (Operational Amplifier Control Register)
OPAEN
PA0, PA3/AN3, PB2/AN2
0
PA0 is GPIO and PB2/AN2, PB3/AN3 is GPIO or analog ADC input by ADCR register.
1
PA0, PB3/AN3 is OPA input pin and PB2/AN2 is OPA output pin. The PB2/AN2 and PB3/AN3 can be analog ADC input if the related ADC function is enabled.
Miscellaneous Register
There is one miscellaneous control registers for various functions. The Miscellaneous register is to enable/disable
Comparator, enable/disable OPA, enable/disable Comparator COUT pin, enable/disable stopping PWM by hardware.
Bit No.
0
1
Label
PWMLEV
This bit is read only. It¢s is the PWM output level option.
0: PWM output will be defined as an active high
1: PWM output will be defined as an active low
If the PWM function disable, this bit is invalid.
This bit is read only. It¢s is the PWM output level option.
0: PWM output will be defined as an active high
PWMCLEV
1: PWM output will be defined as an active low
If the PWM function disable, this bit is invalid.
2
PWMSP0
3
PWMSP1
4
Function
Stopping the PWM and PWM using hardware selection
00: PWM module output can be stop by software control only
01: PWM module output can be stop by COUT falling edge
10: PWM module output can be stop by INT1 interrupt
11: PWM module output can be stop by COUT falling edge or by INT1 interrupt
PWMCTRL To active/inactive PWM and PWM Complementary output (0=inactive; 1=active)
5
COUTEN
6
COUTR
7
¾
PA3/COUT selection
0: PA3/COUT is as a GPIO pin
1: PA3/COUT is Comparator output, and the status of COUT can be read by reading
the PA3 register.
Comparator output flag. This bit is read only
0: Comparator output is low state
1: Comparator output is high state
Unused bit, read as ²0²
MISC (1DH) Register
Rev. 1.10
30
February 16, 2007
HT45RM03
Low Voltage Reset - LVR
The LVR includes the following specifications:
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally.
· The low voltage (0.9V~VLVR) has to remain in their
original state to exceed tLVR. If the low voltage state
does not exceed tLVR, the LVR will ignore it and do not
perform a reset function.
· The LVR uses the ²OR² function with the external RES
signal to perform chip reset.
The relationship between VDD and VLVR is shown below.
V D D
5 .5 V
V
V D D
5 .5 V
O P R
5 .5 V
V
V D D
5 .5 V
O P R
5 .5 V
V
V
2 .1 V
L V R
2 .2 V
3 .1 5 V
O P R
5 .5 V
V
L V R
L V R
4 .2 V
2 .2 V
0 .9 V
V
2 .2 V
0 .9 V
0 .9 V
Note: VOPR is the voltage range for proper chip operation at 4MHz system clock.
V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
*1
R e s e t
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since low voltage state has to be maintained in its original state for over tLVR, therefore after tLVR delay,
the device enters the reset mode.
Rev. 1.10
31
February 16, 2007
HT45RM03
Options
No.
Options
1
OSC type selection.
This option is to decide if an RC or crystal oscillator is chosen as system clock.
2
WDT source selection.
There are three types of selection: on-chip RC oscillator, instruction clock or disable the WDT.
3
CLRWDT times selection.
This option defines how to clear the WDT by instruction. ²One time² means that the CLR WDT instruction can
clear the WDT. ²Two times² means only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, then WDT can be cleared.
4
Wake-up selection.
This option defines the wake-up function activity. External I/O pins (PA only) all have the capability to wake-up
the chip from a HALT.
5
Pull-high selection.
This option is to decide whether a pull-high resistance is visible or not in the input mode of the I/O ports.
PA0~PA7, PB0~PB7, can be independently selected.
6
PFD selection:
PD0: level output or PFD output
7
Low voltage reset selection: Enable or disable LVR function, and LVR voltage selection.
8
PWM mode selection: 10 (9+1), (8+2) or (7+3) mode
9
INT0A, INT0B, INT0C and INT1 trigger edge: disable; high to low; low to high or low to high or high to low.
10
PWM output level selection; PWMLEV.
This option is to determine the PWM output level. Active Low or Active High selection. Disable this bit to ²0², the
PWM output will be defined as an active high output, Enable this bit to ²1², the PWM output will be defined as an
active low output. If the PWM function disable, this bit is invalid.
11
PWM Complementary output level selection; PWMCLEV.
This option is to determine the PWM Complementary output level. Active low or active high selection. Disable
this bit to ²0², the PWM Complementary output will be defined as an active high output, Enable this bit to ²1²,
the PWM Complementary output will be defined as an active low output. If the PWM Complementary function
disable, this bit is invalid.
Rev. 1.10
32
February 16, 2007
HT45RM03
Application Circuits
Application Circuits 1
V
D D
0 .0 1 m F *
V D D
1 0 0 k W
0 .1 m F
R E S
P C 0 ~ P C 5
1 0 k W
M O S F E T
&
D r iv e r
B L D C
0 .1 m F *
V S S
O S C
C ir c u it
P A 4 /IN T 0 A
P A 5 /IN T 0 B
P A 6 /IN T 0 C
O S C 1
O S C 2
P A 7 /IN T 1
S e e R ig h t S id e
H A L L S e n s o r In p u t
V
P A 2 /C V IN N
D D
4 7 0 p F
P A 1 /C V IN P
P A 3 /C O U T
R
P B 7 /A N 7 /T M R 0 /T M R 1
P B 0 /A N 0 ~ P B 1 /A N 1
P B 4 /A N 4 ~ P B 6 /A N 6
P B 2 /A N 2 /O P
P B 3 /A N 3 /O
P A 0 /O
P D 0
O U
P IN
P IN
/P F
O S C
O S C 1
fS
C 1
C 2
P
R 1
D
H T 4 5 R M 0 3
/4
O S C 2
O S C 1
T
N
Y S
R C S y s te m O s c illa to r
2 4 k W < R O S C < 1 M W
C ry s ta l S y s te m
F o r th e v a lu e s ,
s e e ta b le b e lo w
O s c illa to r
O S C 2
O S C
C ir c u it
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only)
Crystal or Resonator
C1, C2
R1
8MHz Crystal
0pF
5.3kW
8MHz Resonator
10pF
6.3kW
4MHz Crystal
0pF
13kW
4MHz Resonator
10pF
12kW
3.58MHz Crystal
0pF
15kW
3.58MHz Resonator
25pF
10kW
2MHz Crystal
25pF
10kW
2MHz Resonator
25pF
12kW
1MHz Crystal
35pF
15kW
480kHz Resonator
300pF, 100pF
9.1kW
455kHz Resonator
300pF
10kW
429kHz Resonator
300pF
10kW
400kHz Resonator
300pF
10kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur.
Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.
Note:
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is
stable and remains within a valid operating voltage range before bringing RES high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
Rev. 1.10
33
February 16, 2007
HT45RM03
Application Circuits 2
1
V
D D
2
R 4
3
4
R 1
5
O v e r C u rre n t 6
R 3
R 5
P B 6 /A N 6
P B 7 /A N 7 /T M R 0 /T M R 1
P A 3 /C O U T
P A 4 /IN T 0 A
P A 2 /C V IN N
P A 5 /IN T 0 B
P A 1 /C V IN P
P A 6 /IN T 0 C
P A 0 /O P V IN P
7
R 2
P B 5 /A N 5
P B 4 /A N 4
C u rre n tA N
8
B A T V o lA N
S p e e d A N
1 0
9
1 1
P A 7 /IN T 1
P B 3 /A N 3 /O P V IN N
O S C 2
P B 2 /A N 2 /O P O U T
O S C 1
P B 1 /A N 1
V D D
P B 0 /A N 0
R E S
1 2
P W M 0
1 3
P W M 1
1 4
V S S
P W M 0
2 8
2 7
B r a k e S ig n a l
2 6
S e n s o r_ C
2 5
S e n s o r_ B
2 4
S e n s o r_ A
2 3
R u n U p
V
2 2
D D
2 1
2 0
V D D
R 6
C 1
1 9
C 2
1 8
P D 0 /P F D
P C 0 /P W M 0
P C 5 /P W M 2
P C 1 /P W M 0
P C 4 /P W M 2
P C 2 /P W M 1
P C 3 /P W M 1
1 7
1 6
P W M 2
P W M 2
1 5
P W M 1
R 7
C 3
H T 4 5 R M 0 3
V
M
D 1
1
2
3
V S S
V D D
V M
V D A T
N C
A T
4
R 8
5
P W M 0
R 9
6
P W M 1
R 1 0
7
P W M 1
R 1 1
8
P W M 2
R 1 2
9
P W M 2
R 1 3
1 0
1 1
1 2
2 3
V D D
A B
A T L
V D B T
A B L
B T
B T L
V S B T
B B L
B B
C T L
V D C T
C B L
C T
2 1
1 9
C 5
P h a s e A
D 2
A B
C 6
+
C 7
B T
1 8
1 7
1 5
P h a s e B
D 3
B B
1 6
C 8
+
C T
1 4
1 3
C B
V S S
+
A T
2 0
V S C T
N C
C 4
2 2
V S A T
V S S
P W M 0
2 4
C 9
P h a s e C
C B
H T 4 5 B 0 C
U b a t
R 1 4
A T
B T
Q 1
R 1 8
R 1 9
C N 1
P h a s e A
C 1 0
R 1 6
A B
R 2 4
C T
R 1 5
B B
Q 2
R 2 5
C N 2
P h a s e B
C 1 1
R 2 0
C N 3
P h a s e C
R 1 7
C 1 2
R 2 6
C B
R 2 1
R 2 7
R 2 2
O v e r_ c u rre n t
R 2 3
V
1
1
V D D
2
V D D
2
3
R u n U p
3
R 2 8
H 2
C 1 3
4
H 4
C 1 9
C 2 0
+ 4 8 V
V S S
Rev. 1.10
V D D
2
R 2 9
R 3 0
C 1 5
C 1 4
5
+ 4 8 V
C N 4
R 3 8
R 3 9
C N 5
C 2 1
R 4 0
R 4 1
B A T V o lA N
R 3 7
S e n s o r_ C
S e n s o r_ B
S e n s o r_ A
R 3 4
H 3
R 3 1
R 3 6
R 3 3
4
S p e e d A N
R 3 5
R 3 2
3
B r a k e S ig n a l
+ 4 8 V
U b a t
U b a t
V S S
1
V S S
V S S
D D
C 1 6
R 4 2
C 2 3
C 1 7
C 1 8
L M 3 1 7
V M
+ 1 5 V
R 4 3
C 2 2
C 2 4
7 8 L 0 5
C 2 5
2
V
D D
+ 5 V
C 2 6
C 2 7
R 4 4
C N 6
34
February 16, 2007
HT45RM03
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.10
35
February 16, 2007
HT45RM03
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.10
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
36
February 16, 2007
HT45RM03
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
37
February 16, 2007
HT45RM03
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
38
February 16, 2007
HT45RM03
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
39
February 16, 2007
HT45RM03
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
40
February 16, 2007
HT45RM03
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
41
February 16, 2007
HT45RM03
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
42
February 16, 2007
HT45RM03
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
43
February 16, 2007
HT45RM03
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
44
February 16, 2007
HT45RM03
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
45
February 16, 2007
HT45RM03
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
46
February 16, 2007
HT45RM03
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
47
February 16, 2007
HT45RM03
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
48
February 16, 2007
HT45RM03
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
49
February 16, 2007
HT45RM03
Package Information
28-pin SKDIP (300mil) Outline Dimensions
A
B
2 8
1 5
1
1 4
H
C
D
E
Symbol
Rev. 1.10
F
a
G
I
Dimensions in mil
Min.
Nom.
Max.
A
1375
¾
1395
B
278
¾
298
C
125
¾
135
D
125
¾
145
E
16
¾
20
F
50
¾
70
G
¾
100
¾
H
295
¾
315
I
330
¾
375
a
0°
¾
15°
50
February 16, 2007
HT45RM03
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
Symbol
Rev. 1.10
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
697
¾
713
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
51
February 16, 2007
HT45RM03
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1.0
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13.0+0.5
-0.2
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
Rev. 1.10
52
February 16, 2007
HT45RM03
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
SOP 28W
Symbol
W
Description
Dimensions in mm
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.85±0.1
B0
Cavity Width
18.34±0.1
K0
Cavity Depth
2.97±0.1
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
Rev. 1.10
21.3
53
February 16, 2007
HT45RM03
Holtek Semiconductor Inc. (Headquarters)
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Copyright Ó 2007 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
54
February 16, 2007