ML145403 ML145404 ML145405 ML145408 Drivers/Receivers RS 232/EIA–232–E and CCITT V.28 Legacy Device: Motorola MC145403, MC145404, MC145405, MC145408 These devices are silicon gate CMOS ICs that combine both the transmitter and receiver to fulfill the electrical specifications of EIA Standard 232–E and CCITT V.28. The drivers feature true TTL input compatibility, slew rate limiting outputs, 300 Ω power–off source impedance, and output typically switching to within 25% of the supply rails. The receivers can handle up to ± 25 V while presenting 3 to 7 kΩ impedance. Hysteresis in the receivers aid in the reception of noisy signals. By combining both drivers and receivers in a single CMOS chip, these devices provide efficient, low–power solutions for both EIA–232–E and V.28 applications. These devices offer the following performance features: • Operating Temperature Range TA = –40° to +85°C Drivers • ± 5 to ± 12 V Supply Range • 300 Ω Power–Off Source Impedance • Output Current Limiting • TTL and CMOS Compatible Inputs • Driver Slew Rate Range Limited to 30 V/µs Maximum Receivers • ± 25 V Input Range • 3 to 7 kΩ Input Impedance • 0.8 V of Hysteresis for Enhanced Noise Immunity • TTL and CMOS Compatible Outputs Available Driver/Receiver Combinations Device Drivers Receivers Figure No. of Pins ML145403 3 5 1 20 ML145404 4 4 2 20 ML145405 5 3 3 20 ML145408 5 5 4 24 Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE. Alternative EIA–232 devices to consider are: Three Supply ML145406 (3 x 3) Page 1 of 8 Single Supply ML145407 (3 x 3) www.lansdale.com Issue A ML145403, ML145404, ML145405, ML145408 LANSDALE Semiconductor, Inc. PIN ASSIGNMENTS (DIP AND SOG) ML145403 3 DRIVERS/5 RECEIVERS VDD Rx1 Tx1 Rx2 Rx3 Tx2 Rx4 Rx5 Tx3 VSS 1 ML145404 4 DRIVERS/4 RECEIVERS 20 V CC 2 19 R 3 D 4 17 R 5 16 R 6 D 7 15 14 R 8 18 13 R 9 D 10 12 11 VDD DO1 Rx1 DI1 Tx1 DO2 Rx2 DO3 Tx2 DI2 Rx3 DO4 Tx3 DO5 Rx4 DI3 Tx4 GND VSS 1 2 20 V CC 3 4 D D 8 D 14 13 R 9 16 15 R 7 18 17 R 5 6 19 R D 12 11 10 ML145405 5 DRIVERS/3 RECEIVERS VDD DO1 Rx1 DI1 Tx1 DO2 Tx2 DI3 Rx2 DO3 Tx3 DI3 Tx4 DO4 Rx3 DI4 Tx5 GND VSS 1 2 20 V CC D 4 D D 7 D 10 17 15 14 13 R 9 18 16 R 6 8 19 R 3 5 ML145408 5 DRIVERS/5 RECEIVERS D 12 11 VDD DO1 Rx1 DI1 Tx1 DI2 Rx2 DO2 Tx2 DI3 Rx3 DI4 Tx3 DO3 Rx4 DI5 Tx4 GND Rx5 Tx5 VSS 24 V CC 1 2 23 R 3 D 4 D 6 D 8 D 10 20 DI2 DO3 18 DI3 DO4 16 DI4 15 R 11 DO2 17 R 9 DI1 19 R 7 22 21 R 5 DO1 D DO5 14 DI5 13 12 GND FUNCTIONAL DIAGRAM RECEIVER ESD PROTECTION DRIVER VCC VDD VCC 15 kΩ VDD VCC + Rx 300 Ω DO LEVEL SHIFT Tx – 5.4 kΩ ++ DI – – 1.4 V VSS VSS 1.0 V 1.8 V Page 2 of 8 www.lansdale.com Issue A ML145403, ML145404, ML145405, ML145408 LANSDALE Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND, except where noted) Rating Symbol Value Unit DC Supply Voltage (VDD ≥ VCC) VDD VSS VCC – 0.5 to + 13.5 + 0.5 to – 13.5 – 0.5 to + 6.0 V Input Voltage Range VIR Rx1 – Rxn DI1 – DIn V VSS – 15 to VDD + 15 0.5 to VCC + 15 I ± 00 mA Power Dissipation PD 1 W Operating Temperature Range TA – 40 to + 85 °C Tstg – 85 to + 150 °C DC Current Drain per Pin Storage Temperature Range This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vout and Vin be constrained to the ranges described as follows: Digital I/O: Driver Inputs (DI): (GND ≤ VDI ≤ VCC). Receiver Outputs (DO): (GND ≤ VDO ≤ VCC). EIA–232 I/O: Driver Outputs (Tx): (VSS ≤ VTx1 – Txn ≤ VDD). Receiver Inputs (Rx): VSS – 15 V ≤ VRx1 – Rxn ≤ VDD + 15 V). Reliability of operation is enhanced if unused outputs are tied off to an appropriate logic voltage level (e.g., either GND or VCC for DI, and GND for Rx). DC ELECTRICAL CHARACTERISTICS (All polarities referenced to GND = 0 V, TA = – 40 to + 85°C) Parameter Symbol Min Typ Max Unit VDD VSS VCC 4.5 – 4.5 4.5 5 to 12 – 5 to – 12 5 13.2 – 13.2 5.5 V IDD ISS ICC — — — 425 – 400 110 635 – 600 200 µA DC Supply Voltage Quiescent Supply Current (Outputs Unloaded, Inputs Low) VDD = + 12 V VSS = – 12 V VCC = + 5 V RECEIVER ELECTRICAL SPECIFICATIONS (Voltage polarities referenced to GND = 0 V, VDD = + 12 V, VSS = – 12 V, TA = – 40 to + 85°C, VCC = + 5 V, ± 10%) Characteristic Symbol Min Typ Max Unit Input Turn–On Threshold VDO = VOL Rx1 – Rxn Von 1.35 1.8 2.35 V Input Turn–Off Threshold VDO = VOH Rx1 – Rxn Voff 0.75 1 1.25 V Vhys 0.6 0.8 — V Rin 3 5.4 7 k Input Threshold Hysteresis ∆ = Von – Voff Input Resistance (VSS – 15 V) ≤ V Rx1 – Rxn ≤ (VDD + 15 V) High Level Output Voltage VRx = – 3 to – 25 V* (DO1 – DOn) Iout = – 20 µA Iout = – 1.0 mA VOH 4.9 3.8 4.9 4.3 — — V Low Level Output Voltage VRx = + 3 to + 25 V* (DO1 – DOn) Iout = + 2 mA Iout = + 4 mA VOL — — 0.02 0.5 0.5 0.7 V * This is the range of input voltages as specified by EIA–232–E to cause a receiver to be in the high or low. Page 3 of 8 www.lansdale.com Issue A ML145403, ML145404, ML145405, ML145408 LANSDALE Semiconductor, Inc. DRIVER ELECTRICAL SPECIFICATIONS (Voltage Polarities Referenced to GND = 0 V, VDD = + 12 V, VSS = – 12 V, TA = – 40 to + 85°C, VCC = + 5 V, ± 10%) Characteristic Symbol Min Typ Max VIL VIH — 2 — — 0.8 — IIL IIH — — 7 — — ± 1.0 Digital Input Voltage Logic 0 Logic 1 DI1 – DIn Input Current VDI = GND VDI = VCC DI1 – DIn Output High Voltage VDI = Logic 0, RL = 3 kΩ VDD = + 5.0 V, VSS = – 5.0 V VDD = + 6.0 V, VSS = – 6.0 V VDD = + 12.0 V, VSS = – 12.0 V Tx1 – Txn Output Low Voltage* VDI = Logic 1, RL = 3 kΩ VDD = + 5.0 V, VSS = – 5.0 V VDD = + 6.0 V, VSS = – 6.0 V VDD = + 12.0 V, VSS = – 12.0 V Tx1 – Txn Input Current (Figure 5) Tx1 – Txn Zoff Output Short Circuit Current VDD = + 12 V, VSS = – 12 V Tx Shorted to GND** Tx Shorted to ± 15 V*** Tx1 – Txn ISC Unit V µA VOH V 3.5 4.3 9.2 3.9 4.7 9.5 — — — VOL V –4 – 4.5 – 10 – 4.3 – 5.2 – 10.3 — — — 300 — — mA — — ± 22 ± 60 ± 60 ± 100 * Voltage specifications are in terms of absolute values. ** Specification is for one Tx output pin to be shorted at a time. Should all three driver outputs be shorted simultaneously, device power dissipation limits will be exceeded. *** This condition could exceed package limitations. SWITCHING CHARACTERISTICS (VCC = + 5 V, ± 10%, VDD = + 12 V, VSS = – 12 V, TA = – 40 to + 85°C; See Figures 2 and 3) Symbol Characteristic Min Typ Max Unit Drivers Propagation Delay Time Tx Low–to–High RL = 3 kΩ, CL = 50 pF tPLH High–to–Low RL = 3 kΩ, CL = 50 pF tPHL Output Slew Rate Minimum Load RL = 7 kΩ, CL = 0 pF (VDD = 6 to 12 V, VSS = – 6 to – 12 V) ns — 500 1000 — 700 1000 SR Maximum Load RL = 3 kΩ, CL = 2500 pF (VDD = 12 V, VSS = – 12 V, VCC = 5 V) V/µs — ±6 ± 30 4 — — — 360 610 Receivers (CL = 50 pF) Propagation Delay Time Low–to–High tPLH ns High–to–Low tPHL — 130 610 Output Rise Time tr — 250 400 ns Output Fall Time tf — 40 100 ns Page 4 of 8 www.lansdale.com Issue A ML145403, ML145404, ML145405, ML145408 LANSDALE Semiconductor, Inc. 1 22 20 18 16 14 24 VDD VCC 3 DI1 Tx1 DI2 Tx2 DI3 Tx3 DI4 Tx4 DI5 VDD Tx5 GND 12 13 5 Vin = ± 2 V 7 9 11 R out V in I Figure 1. Power–Off Source Resistance Illustrated for ML145408 DRIVERS +3V DI 50% 0V tr tf VOH 90% Tx 10% tPHL VOL tPLH RECEIVERS DRIVERS +3V Rx 50% Tx 0V tPHL tPLH 90% DO 10% tf VOH tSHL VOL Slew Rate = tr Figure 2. Switching Characteristics –3V tSLH 6V tSLH or tSHL Figure 3. Slew Rate Characteristics PIN DESCRIPTIONS VCC Digital Power Supply The digital supply pin, which is connected to the logic power supply (+ 5.5 V maximum). GND Ground Ground return pin is typically connected to the signal ground pin of the EIA–232–E connector (Pin 7) as well as to the logic power supply ground. VDD Most Positive Device Pin The most positive power supply pin, which is typically + 5 to + 12 V. Page 5 of 8 +3V +3V –3V VSS Most Negative Device Pin The most negative power supply pin, which is typically – 5 to – 12 V. Rx1 – Rxn Receive Data Input Pins These are the EIA–232–E receive signal inputs. A voltage between + 3 and + 25 V is decoded as a space, and causes the corresponding DO pin to swing to ground (0 V). A voltage between – 3 and – 25 V is decoded as a mark, and causes the corresponding DO pin to swing to VCC. DO1 – DOn Data Output Pins These are the receiver digital output pins which swing fromVCC to GND. Each output pin is capable of driving one LSTTL input load. www.lansdale.com Issue A ML145403, ML145404, ML145405, ML145408 LANSDALE Semiconductor, Inc. DI1 – DIn Data Input Pins These are the high impedance digital input pins to the drivers. Input voltage levels on these pins are LSTTL compatible and must be between VCC and GND. A weak pull–up on each input sets all unused DI pins to VCC, causing the corresponding unused driver outputs to be at VSS. switched off while the + 5 V is on and the off supply is a low impedance to ground, the diode D1 will prevent current flow through the internal diode. The diode D2 is used as a voltage clamp, to prevent VSS from drifting positive to VCC, in the event that power is removed from VSS (Pin 12). If VSS power is removed, and the impedance from the VSS pin to ground is greater than approximately 3 kΩ, this pin will be pulled to VCC by internal circuitry causing excessive current in the VCC pin. If by design, neither of the above conditions are allowed to exist, then the diodes D1 and D2 are not required. Tx1 – TXn Transmit Data Output Pins These are the EIA–232–E transmit signal output pins, which swing from VDD to VSS. A logic 1 at the DI input causes the corresponding Tx output to swing to VSS. A logic 0 at the DI input causes the corresponding Tx out to swing to VDD. The actual levels and slew rate achieved will depend on the output loading (RL//CL). ESD PROTECTION – CAUTION ESD protection on IC devices that have their pins accessible to the outside world is essential. High static voltages applied to the pins when someone touches them either directly or in directly can cause damage to gate oxides and transistor junctions by coupling a portion of the energy from the I/O pin to the power supply buses of the IC. This coupling will usually occur through the internal ESD protection diodes. The key to protecting the IC is to shunt as much of the energy to ground as possible before it enters the IC. Figure 4 shows a technique which will clamp the ESD voltage at approximately ± 15 V using the MMBZ15VDLT1. Any residual voltage which appears on the supply pins is shunted to ground through the capacitors C1 – C3. This scheme has provided protection to the interface part up to ± 10kV, using the human body model test. LEGACY APPLICATION INFORMATION POWER SUPPLY CONSIDERATIONS Figure 4 shows a technique to guard against excessive device current. The diode D1 prevents excessive current from flowing through an internal diode from the VCC pin to the VDD pinwhen VDD < VCC by approximately 0.6 V or greater. This high current condition can exist for a short period of time during power up/down. Additionally, if the + 12 V supply is + 12 V MMBZ15VDLT1 x 10 C1 +5V 1N4001 D1 VDD 1 Rx1 2 Tx1 3 Rx2 4 Tx2 5 24 VCC C2 1N4001 23 DO1 R D 22 DI1 21 DO2 R 20 DI2 D C3 Rx3 6 Tx3 7 Rx4 8 Tx4 9 Rx5 10 Tx5 11 VSS 12 19 DO3 R D 18 DI3 17 DO4 R D 16 DI4 15 DO5 R D 14 DI5 13 GND D2 – 12 V 1N5818 Figure 4. Page 6 of 8 www.lansdale.com Issue A ML145403, ML145404, ML145405, ML145408 LANSDALE Semiconductor, Inc. OUTLINE DIMENSIONS P DIP 20 = RP (ML145403RP, ML145404RP, ML145405RP) PLASTIC DIP CASE 738–03 -A20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B C -T- L DIM A B C D E F G J K L M N K SEATING PLANE M E G N F J 20 PL 0.25 (0.010) D 20 PL 0.25 (0.010) M T A M T B M M INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 15° 0° 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0° 15° 1.01 0.51 P DIP 24 = LP (ML145408LP) PLASTIC DIP CASE 724–03 –A– 24 13 1 12 NOTES: 1. CHAMFERED CONTOUR OPTIONAL. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 4. CONTROLLING DIMENSION: INCH. –B– L C –T– N E G M J F D 24 PL 0.25 (0.010) 24 PL 0.25 (0.010) Page 7 of 8 NOTE 1 K SEATING PLANE M T A M www.lansdale.com M T B M DIM A B C D E F G J K L M N INCHES MIN MAX 1.230 1.265 0.250 0.270 0.145 0.175 0.015 0.020 0.050 BSC 0.040 0.060 0.100 BSC 0.007 0.012 0.110 0.140 0.300 BSC 0 15 0.020 0.040 MILLIMETERS MIN MAX 31.25 32.13 6.35 6.85 3.69 4.44 0.38 0.51 1.27 BSC 1.02 1.52 2.54 BSC 0.18 0.30 2.80 3.55 7.62 BSC 0 15 0.51 1.01 Issue A ML145403, ML145404, ML145405, ML145408 LANSDALE Semiconductor, Inc. OUTLINE DIMENSIONS SO 20W = -6P (ML145403-6P, ML145404-6P, ML145405-6P) SOG PACKAGE CASE 751D–04 –A– 20 11 –B– 10X P 0.010 (0.25) 1 M B M 10 20X D 0.010 (0.25) M T A B S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R J S F R X 45 C –T– 18X G SEATING PLANE SO 24W = -6P (ML145408-6P) SOG PACKAGE CASE 751E–04 24 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 13 –B– 12X P 0.010 (0.25) 1 M B M 12 D J 0.010 (0.25) M T A S B S F R C –T– SEATING PLANE M 22X INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0 7 0.395 0.415 0.010 0.029 M K –A– 24X MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0 7 10.05 10.55 0.25 0.75 G K X 45 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0 8 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0 8 0.395 0.415 0.010 0.029 Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc. Page 8 of 8 www.lansdale.com Issue A