NSC CLC5602IM

N
CLC5602
Dual, High Output, Video Amplifier
General Description
Features
The National CLC5602 has a new output stage that delivers high
output drive current (130mA), but consumes minimal
quiescent supply current (1.5mA/ch) from a single 5V supply. Its
current feedback architecture, fabricated in an advanced complementary bipolar process, maintains consistent performance over
a wide range of gains and signal levels, and has a linear-phase
response up to one half of the -3dB frequency.
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The CLC5602 offers 0.1dB gain flatness to 22MHz and differential gain and phase errors of 0.06% and 0.02°. These features are
ideal for professional and consumer video applications.
■
130mA output current
0.06%, 0.02° differential gain, phase
1.5mA/ch supply current
135MHz bandwidth (Av = +2)
-87/-95dBc HD2/HD3 (1MHz)
15ns settling to 0.05%
300V/µs slew rate
Stable for capacitive loads up to 1000pf
Single 5V or ±5V supplies
Applications
■
The CLC5602 offers superior dynamic performance with a
135MHz small-signal bandwidth, 300V/µs slew rate and 5.7ns
rise/fall times (2Vstep). The combination of low quiescent power,
high output current drive, and high-speed performance make
the CLC5602 well suited for many battery-powered personal
communication/computing systems.
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The ability to drive low-impedance, highly capacitive loads,
makes the CLC5602 ideal for single ended cable applications.
It also drives low impedance loads with minimum distortion.
The CLC5602 will drive a 100Ω load with only -86/-85dBc
second/third harmonic distortion (Av = +2, Vout = 2Vpp, f = 1MHz).
With a 25Ω load, and the same conditions, it produces only -86/
-72dBc second/third harmonic distortion.
CLC5602
Dual, High Output, Video Amplifier
June 1999
Video line driver
ADSL/HDSL driver
Coaxial cable driver
UTP differential line driver
Transformer/coil driver
High capacitive load driver
Portable/battery-powered applications
Differential A/D driver
Maximum Output Voltage vs. RL
10
Output Voltage (Vpp)
9
The CLC5602 can also be used for driving differential-input stepup transformers for applications such as Asynchronous Digital
Subscriber Lines (ADSL) or High-Bit-Rate Digital Subscriber
Lines (HDSL).
8
VCC = ±5V
7
6
5
4
3
Vs = +5V
2
When driving the input of high-resolution A/D converters, the
CLC5602 provides excellent -87/-95dBc second/third harmonic
distortion (Av = +2, Vout = 2Vpp, f = 1MHz, RL = 1kΩ) and fast
settling time.
1
10
100
Typical Application
Pinout
Differential Line Driver with Load Impedance Conversion
DIP & SOIC
Rf2
Rg2
Vo1
Vd/2
Vin
+
Rt1
1/2
CLC5602
1/2
CLC5602
Rf1
Rg1
-Vd/2
+
Rt2
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
1000
RL (Ω)
Rm/2
Req
1:n
RL
UTP
Rm/2
Vinv1
Io
Zo
+
Vo
-
Vnon-inv1
-VCC
+VCC
Vo2
Vinv2
Vnon-inv2
http://www.national.com
+5V Electrical Characteristics (A
v
PARAMETERS
Ambient Temperature
= +2, Rf = 750Ω, RL = 100Ω, Vs = +5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified)
CONDITIONS
CLC5602IN/IM
TYP
+25°C
MIN/MAX RATINGS
+25°C
0 to 70°C -40 to 85°C
UNITS
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
Vo = 0.5Vpp
Vo = 2.0Vpp
-0.1dB bandwidth
Vo = 0.5Vpp
gain peaking
<200MHz, Vo = 0.5Vpp
gain rolloff
<30MHz, Vo = 0.5Vpp
linear phase deviation
<30MHz, Vo = 0.5Vpp
differential gain
NTSC, RL = 150Ω to -1V
differential phase
NTSC, RL = 150Ω to -1V
100
65
22
0
0.1
0.3
0.04
0.09
85
60
20
0.5
0.3
0.5
–
–
75
55
17
0.9
0.4
0.6
–
–
70
50
15
1.0
0.5
0.6
–
–
MHz
MHz
MHz
dB
dB
deg
%
deg
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.05%
overshoot
slew rate
6.1
25
10
220
8.5
35
20
190
9.2
50
22
165
10.0
80
22
150
ns
ns
%
V/µs
-77
-80
-63
-85
-82
-62
-74
-77
-59
-81
-79
-57
-71
-75
-57
-78
-76
-54
-71
-70
-57
-78
-76
-54
dBc
dBc
dBc
dBc
dBc
dBc
3.4
6.3
8.7
-72
4.4
8.2
11.3
–
4.9
9.0
12.4
–
4.9
9.0
12.4
–
nV/√Hz
pA/√Hz
pA/√Hz
dB
1
7
5
25
3
10
48
49
1.5
4
–
12
–
10
–
45
47
1.7
5
15
15
60
12
20
43
45
1.8
6
15
16
60
13
20
43
45
1.8
mV
µV/˚C
µA
nA/˚C
µA
nA/˚C
dB
dB
mA
0.46
1.8
4.2
0.8
4.0
1.0
4.1
0.9
100
55
0.36
2.75
4.1
0.9
3.9
1.1
4.0
1.0
80
90
0.32
2.75
4.1
0.9
3.9
1.1
4.0
1.0
65
90
0.32
2.75
4.0
1.0
3.8
1.2
3.9
1.1
40
120
MΩ
pF
V
V
V
V
V
V
mA
mΩ
2V step
1V step
2V step
2V step
DISTORTION AND NOISE RESPONSE
2Vpp, 1MHz
2nd harmonic distortion
2Vpp, 1MHz; RL = 1kΩ
2Vpp, 5MHz
3rd harmonic distortion
2Vpp, 1MHz
2Vpp, 1MHz; RL = 1kΩ
2Vpp, 5MHz
equivalent input noise
voltage (eni)
>1MHz
non-inverting current (ibn)
>1MHz
inverting current (ibi)
>1MHz
crosstalk (input referred)
10MHz, 1Vpp
STATIC DC PERFORMANCE
input offset voltage
average drift
input bias current (non-inverting)
average drift
input bias current (inverting)
average drift
power supply rejection ratio
common-mode rejection ratio
supply current per channel
DC
DC
RL= ∞
MISCELLANEOUS PERFORMANCE
input resistance (non-inverting)
input capacitance (non-inverting)
input voltage range, High
input voltage range, Low
output voltage range, High
RL = 100Ω
output voltage range, Low
RL = 100Ω
output voltage range, High
RL = ∞
output voltage range, Low
RL = ∞
output current
output resistance, closed loop
DC
NOTES
A
A
A
A
B
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
Notes
A) J-level: spec is 100% tested at +25°C.
B) The short circuit current can exceed the maximum safe
output current.
1) Vs = VCC - VEE
supply voltage (VCC - VEE)
output current (see note C)
common-mode input voltage
maximum junction temperature
storage temperature range
lead temperature (soldering 10 sec)
ESD rating (human body model)
Reliability Information
Transistor Count
MTBF (based on limited test data)
http://www.national.com
98
290Mhr
2
+14V
140mA
VEE to VCC
+150°C
-65°C to +150°C
+300°C
1000V
±5V Electrical Characteristics (A
v
PARAMETERS
Ambient Temperature
= +2, Rf = 750Ω, RL = 100Ω, VCC = ±5V, unless specified)
CONDITIONS
CLC5602IN/IM
TYP
+25°C
GUARANTEED MIN/MAX
+25°C
0 to 70°C -40 to 85°C
UNITS
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
Vo = 1.0Vpp
Vo = 4.0Vpp
-0.1dB bandwidth
Vo = 1.0Vpp
gain peaking
<200MHz, Vo = 1.0Vpp
gain rolloff
<30MHz, Vo = 1.0Vpp
linear phase deviation
<30MHz, Vo = 1.0Vpp
differential gain
NTSC, RL=150Ω
differential phase
NTSC, RL=150Ω
135
48
20
0
0.1
0.15
0.06
0.02
115
45
18
0.5
0.3
0.3
0.18
0.04
105
42
15
0.9
0.4
0.4
–
–
100
40
12
1.0
0.5
0.4
–
–
MHz
MHz
MHz
dB
dB
deg
%
deg
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.05%
overshoot
slew rate
5.7
15
18
300
6.2
25
20
225
6.8
40
22
190
7.3
60
22
175
ns
ns
%
V/µs
-86
-87
-70
-85
-95
-66
-82
-83
-64
-81
-90
-64
-79
-80
-61
-78
-87
-61
-79
-80
-60
-78
-87
-60
dBc
dBc
dBc
dBc
dBc
dBc
3.4
6.3
8.7
-72
4.4
8.2
11.3
–
4.9
9.0
12.4
–
4.9
9.0
12.4
–
nV/√Hz
pA/√Hz
pA/√Hz
dB
2
8
5
40
8
20
48
51
1.6
6
–
12
–
24
–
45
49
1.9
7
–
16
–
28
45
43
47
2.0
8
–
17
–
28
45
43
47
2.0
mV
µV/˚C
µA
nA/˚C
µA
nA/˚C
dB
dB
mA
0.59
1.45
±4.2
±3.8
±4.0
130
40
0.47
2.15
±4.1
±3.6
±3.8
100
70
0.43
2.15
±4.1
±3.6
±3.8
80
70
0.43
2.15
±4.0
±3.5
±3.7
50
90
MΩ
pF
V
V
V
mA
mΩ
2V step
2V step
2V step
2V step
DISTORTION AND NOISE RESPONSE
2Vpp, 1MHz
2nd harmonic distortion
2Vpp, 1MHz; RL = 1kΩ
2Vpp, 5MHz
3rd harmonic distortion
2Vpp, 1MHz
2Vpp, 1MHz; RL = 1kΩ
2Vpp, 5MHz
equivalent input noise
voltage (eni)
>1MHz
non-inverting current (ibn)
>1MHz
inverting current (ibi)
>1MHz
crosstalk (input referred)
10MHz, 1Vpp
STATIC DC PERFORMANCE
input offset voltage
average drift
input bias current (non-inverting)
average drift
input bias current (inverting)
average drift
power supply rejection ratio
common-mode rejection ratio
supply current (per channel)
DC
DC
RL= ∞
MISCELLANEOUS PERFORMANCE
input resistance (non-inverting)
input capacitance (non-inverting)
common-mode input range
output voltage range
RL = 100Ω
output voltage range
RL = ∞
output current
output resistance, closed loop
DC
Notes
Model
CLC5602IN
CLC5602IM
CLC5602IMX
Package Thermal Resistance
Plastic (IN)
Surface Mount (IM)
B
Ordering Information
B) The short circuit current can exceed the maximum safe
output current.
Package
NOTES
θJC
θJA
65°C/W
50°C/W
130°C/W
145°C/W
3
Temperature Range
Description
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
8-pin PDIP
8-pin SOIC
8-pin SOIC tape & reel
http://www.national.com
+5V Typical Performance (A
= +2, Rf = 750Ω, RL = 100Ω, Vs = +5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified)
v
0
-90
-180
Av = +5
Rf = 301Ω
-270
Av = +10
Rf = 200Ω
-360
-450
1M
10M
100M
Av = -1
Rf = 649Ω
Gain
Av = -2
Rf = 649Ω
Phase
Vo = 0.5Vpp
180
135
90
Av = -5
Rf = 649Ω
45
Av = -10
Rf = 500Ω
1M
0
-180
-270
-360
10M
-450
1M
100M
10M
Open Loop Transimpedance Gain, Z(s)
140
0.1
Phase
0
-0.1
Magnitude (dBΩ)
Magnitude (0.05dB/div)
0.2
Gain
100
135
80
90
60
45
-0.2
10
0
100M
180
Gain
-0.3
10M
Phase
120
0.3
Frequency (Hz)
20
40
1k
30
10k
Frequency (MHz)
10M
0
100M
2nd & 3rd Harmonic Distortion
3.6
60
1M
Frequency (Hz)
Equivalent Input Noise
PSRR & CMRR
100k
12.5
-30
30
20
10
10
3.5
Inverting Current 8.7pA/√Hz
3.4
Voltage 3.35nV/√Hz
5
3.3
0
3.2
1k
10k
100k
1M
10M
100k
1M
2nd & 3rd Harmonic Distortion, RL = 25Ω
2nd
RL = 1kΩ
-70
3rd
RL = 100Ω
-80
2nd
RL = 100Ω
-100
10M
1M
2nd & 3rd Harmonic Distortion, RL = 100Ω
2nd & 3rd Harmonic Distortion, RL = 1kΩ
-50
3rd, 10MHz
3rd, 10MHz
3rd, 10MHz
-50
-50
2nd, 10MHz
-60
3rd, 1MHz
-60
-60
-70
2nd, 10MHz
-80
3rd, 1MHz
-90
-80
Distortion (dBc)
Distortion (dBc)
-40
2nd, 10MHz
-70
-80
2nd, 1MHz
-90
2nd, 1MHz
2nd, 1MHz
3rd, 1MHz
-90
-100
0
0.5
1
1.5
2
2.5
-100
0
Output Amplitude (Vpp)
0.5
1
1.5
2
2.5
0
Output Amplitude (Vpp)
Offset Voltage VIO (mV)
Output Resistance (Ω)
2
2.5
3
10
1
0.1
VIO
1.0
2
IBI
0.5
1
0
0
-0.5
-1
IBN
-1.0
-2
-1.5
0.01
10k
100k
1M
10M
Frequency (Hz)
4
100M
-3
-60
-20
20
60
Temperature (°C)
100
140
IBI, IBN (µA)
Output Voltage (0.5V/div)
1.5
IBI, IBN, VIO vs. Temperature
VCC = ±5V
Large Signal
Time (10ns/div)
1
-1.5
100
Small Signal
0.5
Output Amplitude (Vpp)
Closed Loop Output Resistance
Large & Small Signal Pulse Response
http://www.national.com
10M
Frequency (Hz)
-40
-70
3rd
RL = 1kΩ
-60
Frequency (Hz)
-20
-30
-50
-90
2.5
10k
100M
Frequency (Hz)
Distortion (dBc)
7.5
Non-Inverting Current 7pA/√Hz
-40
Distortion (dBc)
Noise Voltage (nV/√Hz)
CMRR
40
Noise Current (pA/√Hz)
PSRR & CMRR (dB)
Vo = 2Vpp
PSRR
50
Phase (deg)
Vo = 2Vpp
225
0.4
Phase (deg)
Vo = 1Vpp
100M
Frequency (Hz)
Gain Flatness & Linear Phase
Vo = 0.1Vpp
-90
RL = 25Ω
0
0.5
Magnitude (1dB/div)
Phase
Frequency (Hz)
Frequency Response vs. Vo
RL = 100Ω
Gain
-45
Frequency (Hz)
1M
RL = 1kΩ
Magnitude (1dB/div)
Av = +1
Rf = 1.0kΩ
Phase
Vo = 0.5Vpp
Phase (deg)
Av = +2
Rf = 649Ω
Frequency Response vs. RL
Phase (deg)
Vo = 0.5Vpp
Gain
Normalized Magnitude (1dB/div)
Inverting Frequency Response
Phase (deg)
Normalized Magnitude (1dB/div)
Non-Inverting Frequency Response
±5V Typical Performance (A
= +2, Rf = 750Ω, RL = 100Ω, VCC = ±5V, unless specified)
v
Inverting Frequency Response
Av = +1
Rf = 1.0kΩ
Phase
0
-45
-90
Av = +5
Rf = 301Ω
-135
Av = +10
Rf = 200Ω
-180
-225
1M
10M
Vo = 1.0Vpp
Av = -2
Rf = 649Ω
Gain
Av = -1
Rf = 649Ω
Phase
180
135
90
Av = -5
Rf = 649Ω
45
Av = -10
Rf = 500Ω
RL = 1kΩ
Gain
RL = 100Ω
Phase
0
-90
-270
0
10M
-360
-450
100M
1M
10M
Frequency (Hz)
Frequency (Hz)
100M
Frequency (Hz)
Gain Flatness & Linear Phase
Frequency Response vs. Vo
-180
RL = 25Ω
-45
1M
100M
Vo = 1.0Vpp
Magnitude (1dB/div)
Gain
Normalized Magnitude (1dB/div)
Av = +2
Rf = 649Ω
Phase (deg)
Vo = 1.0Vpp
Frequency Response vs. RL
Phase (deg)
Phase (deg)
Normalized Magnitude (1dB/div)
Frequency Response
Small Signal Pulse Response
0.4
Vo = 0.1Vpp
Vo = 2Vpp
0.3
Gain
0.2
0.1
Av = +2
Amplitude (200mV/div)
Magnitude (0.1dB/div)
Vo = 1Vpp
Phase (deg)
Magnitude (1dB/div)
Vo = 5Vpp
Phase
0
Av = -2
-0.1
1M
10M
0
100M
10
5
15
20
Time (10ns/div)
30
25
Frequency (MHz)
Frequency (Hz)
Large Signal Pulse Response
Differential Gain & Phase
2nd & 3rd Harmonic Distortion vs. Frequency
0
0
-30
Gain Neg Sync
Amplitude (0.5V/div)
-0.04
-0.04
-0.08
Phase Neg Sync
Phase Pos Sync
-0.12
-0.12
-0.16
-0.16
-0.2
-0.2
Phase (deg)
Gain (%)
Gain Pos Sync
-0.08
Distortion Level (dBc)
Vo = 2Vpp
Av = +2
-40
2nd
RL = 100Ω
-50
-60
2nd
RL = 1kΩ
-70
3rd
RL = 1kΩ
-90
Av = -2
Time (20ns/div)
1
2
3
-100
4
1
10
Number of 150 Ω Loads
2nd & 3rd Harmonic Distortion, RL = 25Ω
Frequency (MHz)
2nd & 3rd Harmonic Distortion, RL = 1kΩ
2nd & 3rd Harmonic Distortion, RL = 100Ω
-30
3rd
RL = 100Ω
-80
-50
-40
3rd, 10MHz
-50
-50
-60
2nd, 10MHz
-70
3rd, 1MHz
-80
3rd, 10MHz
-60
Distortion (dBc)
3rd, 10MHz
Distortion (dBc)
Distortion (dBc)
-40
-60
2nd, 10MHz
-70
-80
3rd, 1MHz
-90
2nd, 1MHz
-90
-100
-100
1
2
3
4
5
0.5
1
1.5
2
0
2.5
0.1
0.05
0
-0.05
-0.1
-0.15
0.1
0.05
0
-0.05
-0.1
-0.2
1000
10000
3
4
5
IBI, IBN, VOS vs. Temperature
-0.15
-0.2
2
1.4
Offset Voltage VOS(mV)
0.15
Vo (% Output Step)
0.15
1
Output Amplitude (Vpp)
Long Term Settling Time
0.2
Time (ns)
3rd, 1MHz
3
1.3
2
IBI
1.2
1
1.1
0
VOS
1
-1
IBN
0.9
-2
0.8
1µ
10µ
100µ
1m
Time (s)
5
10m
100m
IBI, IBN (µA)
Vo (% Output Step)
Short Term Settling Time
100
-90
Output Amplitude (Vpp)
0.2
10
2nd, 1MHz
-110
0
Output Amplitude (Vpp)
1
-80
-100
2nd, 1MHz
-110
0
2nd, 10MHz
-70
-3
-60
-20
20
60
100
140
Temperature (°C)
http://www.national.com
±5V Typical Channel Matching Performance (A
Channel Matching
v
= +2, Rf = 750Ω, RL = 100Ω, VCC = ±5V, unless specified)
Input Referred Crosstalk
Pulse Crosstalk
-20
Vo = 1Vpp
Channel 1
Active Channel
Amplitude (0.2V/div)
Magnitude (dB)
Magnitude (0.5dB/div)
Channel 2
-40
-50
-60
-70
Inactive Output
Channel
Inactive Channel
Amplitude (20mV/div)
Active Output
Channel
-30
-80
-90
1M
10M
100M
10M
1M
Frequency (Hz)
Time (10ns/div)
100M
Frequency (Hz)
CLC5602 OPERATION
The CLC5602 is a current feedback amplifier built in an
advanced complementary bipolar process. The CLC5602
operates from a single 5V supply or dual ±5V supplies.
Operating from a single supply, the CLC5602 has the
following features:
■
■
■
Vo
=
Vin
Av
Rf
1+
Z(jω )
Equation 1
where:
■
Provides 100mA of output current while
consuming 7.5mW of power
Offers low -80/-82dB 2nd and 3rd harmonic
distortion
Provides BW > 60MHz and 1MHz distortion
< -65dBc at Vo = 2.0Vpp
■
■
■
The CLC5602 performance is further enhanced in ±5V
supply applications as indicated in the ±5V Electrical
Characteristics table and ±5V Typical Performance plots.
Av is the closed loop DC voltage gain
Rf is the feedback resistor
Z(jω) is the CLC5602’s open loop
transimpedance gain
Z( jω )
is the loop gain
Rf
The denominator of Equation 1 is approximately equal to
1 at low frequencies. Near the -3dB corner frequency, the
interaction between Rf and Z(jω) dominates the circuit
performance. The value of the feedback resistor has a
large affect on the circuits performance. Increasing Rf
has the following affects:
Current Feedback Amplifiers
Some of the key features of current feedback technology
are:
■ Independence of AC bandwidth and voltage gain
■ Inherently stable at unity gain
■ Adjustable frequency response with feedback resistor
■ High slew rate
■ Fast settling
■
■
■
■
■
Current feedback operation can be described using a simple
equation. The voltage gain for a non-inverting or inverting
current feedback amplifier is approximated by Equation 1.
Decreases loop gain
Decreases bandwidth
Reduces gain peaking
Lowers pulse response overshoot
Affects frequency response phase linearity
Refer to the Feedback Resistor Selection section for
more details on selecting a feedback resistor value.
CLC5602 DESIGN INFORMATION
Single Supply Operation (VCC = +5V, VEE = GND)
The specifications given in the +5V Electrical Characteristics table for single supply operation are measured with
a common mode voltage (Vcm) of 2.5V. Vcm is the voltage around which the inputs are applied and the
output voltages are specified.
+4.2V. The typical output range with RL=100Ω is +1.0V
to +4.0V.
For single supply DC coupled operation, keep input
signal levels above 0.8V DC. For input signals that drop
below 0.8V DC, AC coupling and level shifting the signal
are recommended. The non-inverting and inverting
configurations for both input conditions are illustrated in
the following 2 sections.
Operating from a single +5V supply, the Common Mode
Input Range (CMIR) of the CLC5602 is typically +0.8V to
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6
VCC
DC Coupled Single Supply Operation
Figures 1 and 2 show the recommended non-inverting
and inverting configurations for input signals that remain
above 0.8V DC.
6.8µF
+
VCC
2
VCC
Note: Rt, RL and Rg are tied
to Vcm for minimum power
consumption and maximum
output swing.
Vin
6.8µF
3
1/2
CLC5602
2
Rt
Vcm
-
4
RL
low frequency cutoff =
Vcm
R
Vo
= A v = 1+ f
Vin
Rg
Vin
Vcm
2
1/2
CLC5602
-
4
1
Vo
Rf
1
2πR gC c
Dual Supply Operation
The CLC5602 operates on dual supplies as well as
single supplies. The non-inverting and inverting configurations are shown in Figures 5 and 6.
VCC
6.8µF
VCC
+
6.8µF
+
+
8
0.1µF
1/2
CLC5602
-
Rg
4
Vo
1
Vin
RL
Rf
3
Rt
2
+
Rt
8
-
Vo
1
Rf
4
0.1µF
Rg
R
Vo
= Av = − f
Vin
Rg
0.1µF
1/2
CLC5602
Vcm
Vcm
0.1µF
Figure 4: AC Coupled Inverting Configuration
Figure 1: Non-Inverting Configuration
Rb
2
8
 R 
Vo = Vin  − f  + 2.5
 Rg 
Vo
1
Rf
Vcm
3
Rg
+
R
Rg
Note: Rb, provides DC bias
for non-inverting input.
Rb, RL and Rt are tied
to Vcm for minimum power
consumption and maximum
output swing.
3
0.1µF
8
+
Cc
Vin
+
R
Select Rt to yield
desired Rin = Rt || Rg
R
Vo
= A v = 1+ f
Vin
Rg
+
6.8µF
VEE
Figure 2: Inverting Configuration
Figure 5: Dual Supply Non-Inverting Configuration
AC Coupled Single Supply Operation
Figures 3 and 4 show possible non-inverting and inverting configurations for input signals that go below 0.8V
DC. The input is AC coupled to prevent the need for
level shifting the input signal at the source. The resistive
voltage divider biases the non-inverting input to VCC ÷ 2
= 2.5V (For VCC = +5V).
VCC
6.8µF
+
Rb
3
VCC
2
6.8µF
+
Vin
R
Cc
3
VCC
2

R 
Vo = Vin 1 + f  + 2.5
R

g
low frequency cutoff =
R
2
+
8
4
1
-
4
0.1µF
1
Rf
0.1µF
Vo
Vo
Note: Rb provides DC bias
for the non-inverting input.
Select Rt to yield desired
Rin = Rt || Rg.
+
R
Vo
= Av = − f
Vin
Rg
Rf
Rg
C
1
R
, where: Rin =
2πRinC c
2
Rg
8
1/2
CLC5602
Rt
0.1µF
1/2
CLC5602
-
Vin
+
6.8µF
VEE
Figure 6: Dual Supply Inverting Configuration
R >> R source
Figure 3: AC Coupled Non-Inverting Configuration
7
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Figure 8 shows typical inverting and non-inverting circuit
configurations for matching transmission lines.
Feedback Resistor Selection
The feedback resistor, Rf, affects the loop gain and
frequency response of a current feedback amplifier.
Optimum performance of the CLC5602, at a gain of
+2V/V, is achieved with Rf equal to 750Ω. The frequency
response plots in the Typical Performance sections
illustrate the recommended Rf for several gains. These
recommended values of Rf provide the maximum bandwidth with minimal peaking. Within limits, Rf can be
adjusted to optimize the frequency response.
■
■
Non-inverting gain applications:
■
■
■
Decrease Rf to peak frequency response and
extend bandwidth
Increase Rf to roll off frequency response and
compress bandwidth
R1
V2 +-
■
■
Magnitude (1dB/div)
R7
Rf
Connect R3 directly to ground.
Make the resistors R4, R6, and R7 equal to Zo.
Make R5 II Rg = Zo.
Power Dissipation
Follow these steps to determine the power consumption
of the CLC5602:
1. Calculate the quiescent (no-load) power:
Pamp = ICC (VCC - VEE)
2. Calculate the RMS power at the output stage:
Po = (VCC - Vload) (Iload), where Vload and Iload
are the RMS voltage and current across the
external load.
3. Calculate the total RMS power:
Pt = Pamp + Po
CL = 10pF
Rs = 46.4Ω
CL = 100pF
Rs = 20Ω
CL = 1000pF
Rs = 6.7Ω
The maximum power that the DIP and SOIC packages
can dissipate at a given temperature is illustrated in
Figure 9. The power derating curve for any CLC5602
package can be derived by utilizing the following
equation:
(175° − Tamb )
θ JA
Rs
1k
1k
100M
Frequency (Hz)
Figure 7: Frequency Response vs. CL
where
Transmission Line Matching
One method for matching the characteristic impedance
(Zo) of a transmission line or cable is to place the
appropriate resistor at the input or output of the amplifier.
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Vo
The input and output matching resistors attenuate the
signal by a factor of 2, therefore additional gain is needed.
Use C6 to match the output transmission line over a
greater frequency range. C6 compensates for the increase
of the amplifier’s output impedance with frequency.
Vo = 1Vpp
10M
-
Z0
R6
Inverting gain applications:
Driving Cables and Capacitive Loads
When driving cables, double termination is used to
prevent reflections. For capacitive load applications, a
small series resistor at the output of the CLC5602 will
improve stability and settling performance. The
Frequency Response vs. CL plot, shown below in
Figure 7, gives the recommended series resistance value
for optimum flatness at various capacitive loads.
1M
Rg
1/2
CLC5602
Figure 8: Transmission Line Matching
Load Termination
The CLC5602 can source and sink near equal amounts
of current. For optimum performance, the load should be
tied to Vcm.
1k
Z0
C6
+
R5
■
CL
R3
R2
R4
Unity Gain Operation
The recommended Rf for unity gain (+1V/V) operation
is 1kΩ. Rg is left open. Parasitic capacitance at the
inverting node may require a slight increase in Rf to
maintain a flat frequency response.
-
Z0
V1 +-
As a rule of thumb, if the recommended Rf is doubled,
then the bandwidth will be cut in half.
+
Connect Rg directly to ground.
Make R1, R2, R6, and R7 equal to Zo.
Use R3 to isolate the amplifier from reactive
loading caused by the transmission line,
or by parasitics.
Tamb = Ambient temperature (°C)
θJA = Thermal resistance, from junction to ambient,
for a given package (°C/W)
8
1.0
■
IM
Power (W)
0.8
IN
■
0.6
■
The readme file that accompanies the diskette lists
released models, and provides a list of modeled parameters. The application note OA-18, Simulation SPICE
Models for National’s Op Amps, contains schematics and
a reproduction of the readme file.
0.4
0.2
0
-40 -20
0
Support Berkeley SPICE 2G and its many derivatives
Reproduce typical DC, AC, Transient, and Noise
performance
Support room temperature simulations
20 40 60 80 100 120 140 160 180
Ambient Temperature (°C)
Figure 9: Power Derating Curves
Application Circuits
Layout Considerations
A proper printed circuit layout is essential for achieving
high frequency performance. National provides
evaluation boards for the CLC5602 (CLC730038-DIP,
CLC730036-SOIC) and suggests their use as a guide for
high frequency layout and as an aid for device testing and
characterization.
Single Supply Cable Driver
The typical application shown below shows one of the
CLC5602 amplifiers driving 10m of 75Ω coaxial cable.
The CLC5602 is set for a gain of +2V/V to compensate
for the divide-by-two voltage drop at Vo.
+5V
General layout and supply bypassing play major roles in
high frequency performance. Follow the steps below as
a basis for high frequency layout:
■
■
■
■
■
+
Include 6.8µF tantalum and 0.1µF ceramic
capacitors on both supplies.
Place the 6.8µF capacitors within 0.75 inches
of the power pins.
Place the 0.1µF capacitors less than 0.1 inches
from the power pins.
Remove the ground plane under and around the
part, especially near the input and output pins to
reduce parasitic capacitance.
Minimize all trace lengths to reduce series
inductances.
Use flush-mount printed circuit board pins for
prototyping, never use high profile DIP sockets.
Vin
■
■
5kΩ
3
5kΩ
2
+
8
0.1µF
1/2
CLC5602
-
4
75Ω
1
1kΩ
10m of 75Ω
Coaxial Cable
0.1µF
Vo
75Ω
1kΩ
0.1µF
Figure 10: Single Supply Cable Driver
Vin = 10MHz, 0.5Vpp
Evaluation Board Information
A data sheet is available for the CLC730038/ CLC730036
evaluation boards. The evaluation board data sheet
provides:
■
0.1µF
100mV/div
■
6.8µF
Evaluation board schematics
Evaluation board layouts
General information about the boards
20ns/div
The evaluation boards are designed to accommodate
dual supplies. The boards can be modified to provide
single supply operation. For best performance; 1) do
not connect the unused supply, 2) ground the unused
supply pin.
Figure 11: Response After 10m of Cable
Single Supply Lowpass Filter
Figures 12 and 13 illustrate a lowpass filter and design
equations. The circuit operates from a single supply of
+5V. The voltage divider biases the non-inverting input to
2.5V. And the input is AC coupled to prevent the need for
level shifting the input signal at the source. Use the
design equations to determine R1, R2, C1, and C2 based
on the desired Q and corner frequency.
SPICE Models
SPICE models provide a means to evaluate amplifier
designs. Free SPICE models are available for National’s
monolithic amplifiers that:
9
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Differential Line Driver With Load
Impedance Conversion
The circuit shown in the Typical Application schematic
on the front page and in Figure 15, operates as a
differential line driver. The transformer converts the load
impedance to a value that best matches the CLC5602’s
output capabilites. The single-ended input signal is
converted to a differential signal by the CLC5602. The
line’s characteristic impedance is matched at both the
input and the output. The schematic shows Unshielded
Twisted Pair for the transmission line; other types of lines
can also be driven.
+5V
0.1µF
5kΩ
Vin
0.1µF
R1
R2
3
158Ω 158Ω
5kΩ
2
C2
100pF
+
C1
8
1/2
CLC5602
-
4
1
0.1µF
Rf
Vo
100Ω
1kΩ
1.698kΩ Rg
0.1µF
Figure 12: Lowpass Filter Topology
Rf2
Rg2
Vd/2
Vin
R
Gain = K = 1 + f
Rg
+
1/2
CLC5602
Rt1
1/2
CLC5602
Rf1
Corner frequency = ω c =
1
R1R 2C1C2
Rg1
Rm/2
Io
1:n
Zo
Req
+
RL
UTP
+
Vo
-
Rm/2
Rt2
1
Q=
R 2C 2
+
R1C1
Figure 15: Differential Line Driver wtih
Load Impedance Conversion
R1C2
R1C1
+ (1− K)
R 2C1
R 2C 2
For R1 = R 2 = R and C1 = C2 = C
Set up the CLC5602 as a difference amplifier:
1
RC

Vd
R 
R
= 2 ⋅ 1 + f1  = 2 ⋅ f2
Vin
R
R

g1 
g2
1
(3 − K)
Make the best use of the CLC5602’s output drive
capability as follows:
ωc =
Q=
-Vd/2
Rm + Req =
Figure 13: Design Equations
This example illustrates a lowpass filter with Q = 0.707
and corner frequency fc = 10MHz. A Q of 0.707 was
chosen to achieve a maximally flat, Butterworth
response. Figure 14 indicates the filter response.
2 ⋅ Vmax
Imax
where Req is the transformed value of the load impedance, Vmax is the Output Voltage Range, and Imax is the
maximum Output Current.
Match the line’s characteristic impedance:
RL = Z o
Magnitude (dB)
3
Rm = Req
-3
n=
-9
Select the transformer so that it loads the line with a
value very near Zo over frequency range. The output
impedance of the CLC5602 also affects the match. With
an ideal transformer we obtain:
-15
-21
1M
10M
RL
Req
100M
Frequency (Hz)
Figure 14: Lowpass Response
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Return Loss = −20 ⋅ log10
10
n2 ⋅ Z o(5602) ( jω )
,dB
Zo
where Zo(5602)(jω) is the output impedance of the
CLC5602 and |Zo(5602)(jω)| << Rm.
The receiver output voltages are:
VoutA(B) ≈ VinA(B) ⋅ A +
The load voltage and current will fall in the ranges:
Vo
≤ n ⋅ Vmax
Io ≤
Imax
n
VinB(A) 
Z o(5602) (jω ) 
R
⋅ 1 − f2 +

2
Rm1
 R g2

where A is the attenuation of the cable, Zo(5602)(jω) is the
output impedance of the CLC5602 (see the Closed-Loop
Output Resistance plot), and | Zo(5602)(jω) | << Rm1.
The CLC5602’s high output drive current and low
distortion make it a good choice for this application.
We selected the component values as follows:
■
Full Duplex Cable Driver
The circuit shown in Figure 16 below, operates as a full
duplex cable driver which allows simultaneous transmission and reception of signals on one transmission line.
The circuit on either side of the transmission line uses are
CLC5602 as a cable driver, and the second CLC5602 as
a receiver. VoA is an attenuated version of VinA, while VoB
is an attenuated version of VinB.
■
■
■
Rf1 = 1.0kΩ, the recommended value for the
CLC5602 at unity gain
Rm1 = Zo = 50Ω, the characteristic impedance
of the transmission line
Rf2 = Rg2 = 750Ω ≥ Rm1, the recommended
value for the CLC5602 at Av = 2
R t2 = (R f2 || R g2 ) –
Rm1
= 25Ω
2
These values give excellent isolation from the other input:
VinA
Rt1
+
Rm1
1/2
CLC5602
Z0
Rm1
1/2
CLC5602
-
-
Rf1
Rg2
Rf2
1/2
CLC5602
+
VinB
VoA(B)
Rt1
VinB(A)
The CLC5602 provides large output current drive, while
consuming little supply current, at the nominal bias point.
It also produces low distortion with large signal swings
and heavy loads. These features make the CLC5602 an
excellent choice for driving transmission lines.
Rf2
-
Rt2
Rt2
≈ −38dB, f = 5.0MHz
Rf1
Rg2
-
VoB
+
1/2
CLC5602
VoA
+
Figure 16: Full Duplex Cable Driver
Rm1 is used to match the transmission line. Rf2 and Rg2
set the DC gain of the CLC5602, which is used in a
difference mode. Rt2 provides good CMRR and DC
offset. The transmitting CLC5602’s are shown in a unity
gain configuration because they consume the least
power of any gain, for a given load. For proper operation
we need Rf2 = Rg2.
11
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CLC5602
Dual, High Output, Video Amplifier
Customer Design Applications Support
National Semiconductor is committed to design excellence. For sales, literature and technical support, call the
National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018.
Life Support Policy
National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of
the president of National Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
N
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