TI OPA4684M

SGLS145B − AUGUST 2003 − REVISED FEBRUARY 2004
features
D Minimal Bandwidth Change Versus Gain
D 170-MHz Bandwidth at G = +2
D > 120 MHz Bandwidth To Gain > +10
D Low Distortion: < −78 dBc at 5 MHz
D High Output Current: 120 mA
D Single 5-V to 12-V Supply Operation
D Dual ±2.5 to ±6.0V Supply Operation
D Low Supply Current: 6.8 mA Total
applications
D Low-Power Broadcast Video Drivers
D Equalizing Filters
D Saw Filter High-Gain Post Amplifiers
D Multichannel Summing Amplifiers
D Wideband Differential Channels
D Analog-to-Digital Converters (ADC) Input
Drivers
D Multiple Pole Active Filters
D OPA4658 Low-Power Upgrade
description
The OPA4684 provides a new level of performance in low-power, wideband, current-feedback (CFB) amplifiers.
This CFBPLUS amplifier is among the first to use an internally closed-loop input buffer stage that enhances
performance significantly over earlier low-power CFB amplifiers. While retaining the benefits of very low power
operation, this new architecture provides many of the benefits of a more ideal CFB amplifier. The closed-loop
input stage buffer gives a very low and linearized impedance path at the inverting input to sense the feedback
error current. This improved inverting input impedance retains exceptional bandwidth to much higher gains and
improves harmonic distortion over earlier solutions limited by inverting input linearity. Beyond simple high-gain
applications, the OPA4684 CFBPLUS amplifier permits the gain setting element to be set with considerable
freedom from amplifier bandwidth interaction. This allows frequency response peaking elements to be added,
multiple input inverting summing circuits to have greater bandwidth, and low-power line drivers to meet the
demanding requirements of studio cameras and broadcast video.
The output capability of the OPA4684 also sets a new mark in performance for low-power current-feedback
amplifiers. Delivering a full ±4Vp-p swing on ±5V supplies, the OPA4684 also has the output current to support
> ±3-V swing into 50 Ω. This minimal output headroom requirement is complemented by a similar 1.2-V input
stage headroom giving exceptional capability for single +5V operation.
The OPA4684’s low 6.8-mA supply current is precisely trimmed at 25°C. This trim, along with low shift over
temperature and supply voltage, gives a very robust design over a wide range of operating conditions.
CFBPLUS BW (MHz) vs Gain
1 of 4 Channels
V+
VO
V−
Z(S)IERR
IERR
RF
RG
Low Power CFBPLUS Amplifer
Patent Pending
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003− 2004 Texas Instruments Incorporated
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SGLS145B − AUGUST 2003 − REVISED FEBRUARY 2004
pin assignments
JD PACKAGE
(TOP VIEW)
Output A
Output D
−Input A
−Input D
+Input A
+Input D
+V
−V
+Input B
+Input C
−Input B
−Input C
Output B
Output C
ORDERING INFORMATION†
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−55°C to 125°C
CDIP - JD
Tube
OPA4684MJD
OPA4684MJD
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6.5 V
Internal power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Thermal information
Differential input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.2 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C
ESD rating: HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 kV
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
Operating voltage
Single-supply operating voltage
Operating free-air temperature
NOM
MAX
UNIT
±5
±6
5
12
V
125
°C
−55
V
electrical characteristics, VS = ±5 V, RF = 800 Ω, RL = 100 Ω, G = +2 (unless otherwise noted) (see
Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC Performance (See Figure 41)
Small signal bandwidth (VO =
0.5 Vp-p)
Large signal bandwidth
Rise and fall time
Differential gain
Differential phase
All hostile cross talk, input
referred
G = +1, RF = 800 Ω
250
G = +5, RF = 800 Ω
138
G = +10, RF = 800 Ω
120
G = +20, RF = 800 Ω
95
VO = 4 V, G = +2
VO = 0.5 V step, G = +2
90
VO = 4 V step, G = +2
VO = 1.4 V, G = +2, RL = 150 Ω , NTSC
6.8
MHz
3
VO = 1.4 V, G = +2, RL = 150 Ω , NTSC
3 channels driven at 5 MHz, VI = 1 V,
4th channel measured
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MHz
• DALLAS, TEXAS 75265
ns
0.04%
0.02°
−52
dB
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electrical characteristics, VS = ±5 V, RF = 800 Ω, RL = 100 Ω, G = +2 (unless otherwise noted) (see
Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
160
355
MAX
UNIT
DC Performance (see Note 2)
Open-loop transimpedance
gain, ZOL
VO = 0 V, RL = 1 kΩ
Input offset voltage
VCM = 0 V
TA = 25°C
TA = −55°C to 125°C
±1.5
TA = 25°C
TA = −55°C to 85°C
Inverting input bias current
±13
±15
µA
±17
±5
TA = 25°C
TA = −55°C to 85°C
VCM = 0 V
mV
±6.0
±5
TA = −55°C to 85°C
TA = 125°C
VCM = 0 V
±4.0
±5.0
TA = 125°C
TA = 25°C
Non-inverting input bias current
kΩ
153
±17
±19.5
µA
±21
TA = 125°C
Input
±3.65
Common-mode input voltage
range, CMIR (see Note 3)
TA = 25°C
TA = −55°C to 125°C
TA = 25°C
TA = −55°C to 85°C
53
Common-mode rejection ratio,
CMRR
TA = 125°C
50
VCM = 0 V
V
60
52
Noninverting input impedance
Inverting input resistance, RI
±3.75
±3.6
Open-loop, DC
dB
50
kΩ
2
pF
4
Ω
Output
Voltage output swing
1 kΩ load
TA = 25°C
TA = −55°C to 125°C
±3.9
VO = 0 V
TA = 25°C
TA = −55°C to 125°C
120
Current output, sourcing
VO = 0 V
TA = 25°C
TA = −55°C to 125°C
−100
Current output, sinking
Closed-loop output impedance
G = +2, f = 100 kHz
±4.1
V
±3.8
160
mA
110
−120
mA
−90
Ω
0.006
Power Supply
Maximum quiescent current
Power supply rejection ratio,
−PSRR
VS = ±5 V
Input referred
TA = 25°C
TA = −55°C to 85°C
6.4
5.8
7.8
TA = 125°C
TA = 25°C
5.2
7.8
TA = −55°C to 125°C
6.8
60
53
7.2
mA
dB
NOTES: 1. All typical limits are at TA = 25°C unless otherwise specified. Junction temperature = ambient temperature for low temperature limits.
Junction temperature = ambient temperature + 7°C at high temperature limit over temperature tested specifications.
2. Current is considered positive out of node. VCM is the input common-mode voltage.
3. Tested < 3dB below minimum specified CMR at ±CMIR limits.
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electrical characteristics, VS = 5 V, RF = 1 kΩ, RL = 100 Ω, G = +2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC Performance (See Figure 41)
Small signal bandwidth (VO =
0.5 Vp-p)
Large signal bandwidth
Slew rate
Rise and fall time
Differential gain
Differential phase
All hostile cross talk, input
referred
G = +1, RF = 1.3 kΩ
140
G = +10, RF = 1.3 kΩ
90
G = +20, RF = 1.3 kΩ
75
VO = 2 V, G = +2
VO = 0.5 V step, G = +2
86
MHz
4.3
ns
5.3
ns
VO = 2 V step, G = +2
VO = 1.4 V, G = +2, RL = 150 Ω , NTSC
MHz
0.04%
VO = 1.4 V, G = +2, RL = 150 Ω , NTSC
3 channels driven at 5 MHz, VI = 1 V,
4th channel measured
0.07°
−52
dB
DC Performance (see Note 2)
Open-loop transimpedance
gain, ZOL
Input offset voltage
VO = VS/2, RL = 1 kΩ to VS/2
VCM = VS/2
Inverting input bias current
VCM = VS/2
160
355
kΩ
153
±1
TA = 25°C
TA = −55°C to 85°C
VCM = VS/2
Non-inverting input bias current
TA = 25°C
TA = −55°C to 125°C
±3.5
±4.3
mV
±5.0
TA = 125°C
TA = 25°C
±5
±13
±15
TA = −55°C to 125°C
TA = 25°C
±5
±13
±16
TA = −55°C to 125°C
µA
A
A
µA
Input
Least positive input voltage
(see Note 3)
TA = 25°C
TA = −55°C to 125°C
Most positive input voltage (see
Note 3)
TA = 25°C
TA = −55°C to 125°C
Common-mode rejection ratio,
CMRR
VCM = VS/2
1.25
1.38
3.68
TA = 25°C
TA = −55°C to 85°C
51
TA = 125°C
49
V
58
50
Open-loop
V
3.75
3.62
Noninverting input impedance
Inverting input resistance, RI
1.32
dB
50
kΩ
1
pF
5
Ω
Output
Most positive output voltage
RL = 1 kΩ to VS/2
TA = 25°C
TA = −55°C to 125°C
Least positive output voltage
RL = 1 kΩ to VS/2
TA = 25°C
TA = −55°C to 125°C
VO = VS/2
TA = 25°C
TA = −55°C to 125°C
62
Current output, sourcing
VO = VS/2
TA = 25°C
TA = −55°C to 125°C
−52
Current output, sinking
Closed-loop output impedance
G = +2, f = 100 kHz
POST OFFICE BOX 655303
3.9
4.10
V
3.8
0.9
1.2
V
80
mA
55
−70
mA
−45
0.006
• DALLAS, TEXAS 75265
1.1
Ω
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SGLS145B − AUGUST 2003 − REVISED FEBRUARY 2004
electrical characteristics, VS = 5 V, RF = 1 kΩ, RL = 100 Ω, G = +2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
TA = 25°C
TA = −55°C to 85°C
5.2
5.8
6.2
4.6
6.2
TA = 125°C
4.2
6.2
UNIT
Power Supply
Quiescent current range
Power supply rejection ratio,
+PSRR
VS = 5 V
Input referred
58
mA
dB
NOTES: 1. All typical limits are at TA = 25°C unless otherwise specified. Junction temperature = ambient temperature for low temperature limits.
Junction temperature = ambient temperature + 3°C at high temperature limit for over temperature tested specifications.
2. Current is considered positive out of node. VCM is the input common-mode voltage.
3. Tested < 3dB below minimum specified CMR at ±CMIR limits.
TYPICAL CHARACTERISTICS
Ω
Ω
Figure 1
Figure 2
Ω
Ω
Figure 3
6
Figure 4
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TYPICAL CHARACTERISTICS
Figure 5
Figure 6
Ω

Figure 7
Figure 8
Ω
Ω
±
±
±
±
±
±
±
±
±
Figure 9
Figure 10
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TYPICAL CHARACTERISTICS
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16

Figure 11
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TYPICAL CHARACTERISTICS
Figure 17
ϒ
Figure 18

Figure 19
∝
Figure 20
ϒ
ϒ
Figure 21
Figure 22
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TYPICAL CHARACTERISTICS
±
±
Figure 23
Figure 24
Figure 25
Figure 26
±
±
±
±
Figure 27
10
Figure 28
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TYPICAL CHARACTERISTICS
Ω
Ω
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
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TYPICAL CHARACTERISTICS
Ω

Figure 36
Figure 37
Figure 38
ϒ
Figure 35
ϒ
Ω
Figure 39
12
Figure 40
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APPLICATION INFORMATION
low-power current-feedback operation
The quad-channel OPA4684 gives a new level of performance in low-power current-feedback op amps. Using
a new input stage buffer architecture, the OPA4684 CFBPLUS amplifier holds nearly constant AC performance
over a wide gain range. This closed-loop internal buffer gives a very low and linearized impedance at the
inverting node, isolating the amplifier’s AC performance from gain element variations. This allows both the
bandwidth and distortion to remain nearly constant over gain, moving closer to the ideal current feedback
performance of gain bandwidth independence. This low-power amplifier also delivers exceptional output
power—it’s ±4V swing on ±5V supplies with > 100-mA output drive gives excellent performance into standard
video loads or doubly-terminated 50-Ω cables. Single +5V supply operation is also supported with similar
bandwidths but with reduced output power capability. For lower quiescent power in a CFBPLUS amplifier,
consider the OPA683 family; while for higher output power, consider the OPA691 family.
Figure 41 shows the DC-coupled, gain of +2, dual power-supply circuit used as the basis of the ±5V Electrical
and Typical Characteristics for each channel. For test purposes, the input impedance is set to 50 Ω with a
resistor to ground and the output impedance is set to 50 Ω with a series output resistor. Voltage swings reported
in the Electrical Characteristics are taken directly at the input and output pins while load powers (dBm) are
defined at a matched 50Ω load. For the circuit of Figure 41, the total effective load will be 100 Ω || 1600 Ω =
94 Ω. Gain changes are most easily accomplished by simply resetting the RG value, holding RF constant at its
recommended value of 800 Ω.
Figure 41. DC-Coupled, G = +2V/V, Bipolar Supply Specifications and Test Circuit
Figure 42 shows the DC-coupled, gain of −1V/V, dual power-suuply circuit used as the basis of the inverting
typical characteristics for each channel. Inverting operation offers several performance benefits. Since there
is no common-mode signal across the input stage, the slew rate for inverting operation is typically higher and
the distortion performance is slightly improved. An additional input resistor, RM, is included in Figure 42 to set
the input impedance equal to 50 Ω. The parallel combination of RM and RG set the input impedance. As the
desired gain increases for the inverting configuration, RG is adjusted to achieved the desired gain, while RM is
also adjusted to hold a 50Ω input match. A point will be reached where RG will equal 50 Ω, RM is removed, and
the input match is set by RG only. With RG fixed to achieve an input match to 50 Ω, increasing RF will increase
the gain. This will, however, quickly reduce the achievable bandwidth as the feedback resistor increases from
its recommended value of 800 Ω. If the source does not require an input match to 50 Ω, either adjust RM to get
the desired load, or remove it and let the RG resistor alone provide the input load.
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Figure 42. DC-Coupled, G = _1V/V, Bipolar Supply Specifications and Test Circuit
These circuits show ±5V operation. The same circuits can be applied with bipolar supplies from ±2.5V to ±6V.
Internal supply independent biasing gives nearly the same performance for the OPA4684 over this wide range
of supplies. Generally, the optimum feedback resistor value (for nominally flat frequency response at G = +2)
will increase in value as the total supply voltage across the OPA4684 is reduced.
See Figure 43 for the AC-coupled, single +5V supply, gain of +2V/V circuit configuration used as a basis for the
+5V only Electrical and Typical Characteristics for each channel. The key requirement of broadband
single-supply operation is to maintain input and output signal swings within the usable voltage ranges at both
the input and the output. The circuit of Figure 43 establishes an input midpoint bias using a simple resistive
divider from the +5V supply (two 10-kΩ resistors) to the noninverting input. The input signal is then AC-coupled
into this midpoint voltage bias. The input voltage can swing to within 1.25 V of either supply pin, giving a 2.5-Vp-p
input signal range centered between the supply pins. The input impedance of Figure 43 is set to give a 50Ω
input match. If the source does not require a 50Ω match, remove this and drive directly into the blocking
capacitor. The source will then see the 5-kΩ load of the biasing network as a load. The gain resistor (RG) is
AC-coupled, giving the circuit a DC gain of +1, which puts the noninverting input DC bias voltage (2.5 V) on the
output as well. The feedback resistor value has been adjusted from the bipolar ±5V supply condition to
re-optimize for a flat frequency response in +5V only, gain of +2, operation. On a single +5V supply, the output
voltage can swing to within 1.0 V of either supply pin while delivering more than 70-mA output current—easily
giving a 3-Vp-p output swing into 100 Ω (8dBm maximum at the matched 50Ω load). The circuit of Figure 43
shows a blocking capacitor driving into a 50Ω output resistor, then into a 50Ω load. Alternatively, the blocking
capacitor could be removed if the load is tied to a supply midpoint or to ground if the DC current required by the
load is acceptable.
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Figure 43. AC-Coupled, G = +2V/V, Single-Supply Specifications and Test Circuit
Figure 44 shows the AC-coupled, single +5-V supply, gain of −1V/V circuit configuration used as a basis for the
inverting +5 V only Typical Characteristics for each channel. In this case, the midpoint DC bias on the
noninverting input is also decoupled with an additional 0.1-µF capacitor. This reduces the source impedance
at higher frequencies for the noninverting input bias current noise. This 2.5-V bias on the noninverting input pin
appears on the inverting input pin and, since RG is DC-blocked by the input capacitor, will also appear at the
output pin. One advantage to inverting operation is that since there is no signal swing across the input stage,
higher slew rates and operation to even lower supply voltages is possible. To retain a 1-Vp-p output capability,
operation down to a 3-V supply is allowed. At a +3-V supply, the input stage is saturated, but for the inverting
configuration of a current-feedback amplifier, wideband operation is retained even under this condition.
The circuits of Figures 43 and 44 show single-supply operation at +5 V. These same circuits may be used up
to single supplies of +12 V with minimal change in the performance of the OPA4684.
Figure 44. AC-Coupled, G = −1V/V, Single-Supply Specifications and Test Circuit
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differential interface applications
Dual and quad op amps are particularly suitable to differential input to differential output applications. Typically,
these fall into either ADC input interface or line driver applications. Two basic approaches to differential I/O are
noninverting or inverting configurations. Since the output is differential, the signal polarity is somewhat
meaningless—the noninverting and inverting terminology applies here to where the input is brought into the
OPA4684. Each has its advantages and disadvantages. Figure 45 shows a basic starting point for noninverting
differential I/O applications.
Figure 45. Noninverting Differential I/O Amplifier
This approach provides for a source termination impedance that is independent of the signal gain. For instance,
simple differential filters may be included in the signal path right up to the noninverting inputs without interacting
with the amplifier gain. The differential signal gain for the circuit of Figure 45 is:
VO
+ AD + 1 ) 2
VI
RF
RG
Since the OPA4684 is a CFBPLUS amplifier, its bandwidth is principally controlled with the feedback resistor
value; Figure 45 shows the recommended value of 800 Ω. However, the gain may be adjusted with considerable
freedom using just the RG resistor. In fact, RG may be a reactive network providing a very isolated shaping to
the differential frequency response. Since the inverting inputs of the OPA4684 are very low impedance
closed-loop buffer outputs, the RG element does not interact with the amplifier’s bandwidth—wide ranges of
resistor values and/or filter elements may be inserted here with minimal amplifier bandwidth interaction.
Various combinations of single-supply or AC-coupled gains can also be delivered using the basic circuit of
Figure 45. Common-mode bias voltages on the two noninverting inputs pass on to the output with a gain of 1
since an equal DC voltage at each inverting node creates no current through RG, giving that voltage a
common-mode gain of 1 to the output.
Figure 46 shows a differential I/O stage configured as an inverting amplifier. In this case, the gain resistors (RG)
become the input resistance for the source. This provides a better noise performance than the noninverting
configuration but does limit the flexibility in setting the input impedance separately from the gain.
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Figure 46. Inverting Differential I/O Amplifier
The two noninverting inputs provide an easy common-mode control input. This is particularly useful if the source
is AC-coupled through either blocking caps or a transformer. In either case, the common-mode input voltages
on the two noninverting inputs again have a gain of 1 to the output pins, giving an easy common-mode control
for single-supply operation. The OPA4684 used in this configuration does constrain the feedback to the 800
region for best frequency response. With RF fixed, the input resistors may be adjusted to the desired gain but
will also be changing the input impedance as well. The differential gain for this circuit is:
VO
R
+* F
VI
RG
low-power video line driver applications
For low-power, video line driving, the OPA4684 provides the output current and linearity to support 4 channels
of either single video lines, or up to 4 video lines in parallel on each output. Figure 47 shows a typical ±5V supply
video line driver application where only one channel is shown and only a single line is being driven. The improved
2nd-harmonic distortion of the CFBPLUS architecture, along with the OPA684’s high output current and voltage,
gives exceptional differential gain and phase performance for a low-power solution. As the Typical
Characteristics show, a single video load shows a dG/dP of 0.04%/0.02°. Multiple loads may be driven on each
output, with minimal x-talk, while the dG/dP is still < 0.1%/0.1° for up to 4 parallel video loads.
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Figure 47. Gain of +2 Video Cable Driver
dc-coupled single-to-differential conversion
The previous differential output circuits were set up to receive a differential input as well as provide a differential
output. Figure 48 shows one way to provide a single to differential conversion, with DC coupling, and
independent output common-mode control using a quad op amp.
The circuit of Figure 48 provides several useful features for isolating the input signal from the final outputs. Using
the first amplifier as a simple noninverting stage gives an independent adjustment on RI (to set the source
loading) while the gain can be easily adjusting in this stage using the RG resistor. Bandwidth is relatively
independent of gain setting in the OPA4684. The next stage allows a separate output common-mode level to
be set up. The desired output common-mode voltage, VCM, is cut in half and applied to the noninverting input
of the 2nd stage. The signal path in this stage sees a gain of −1 while this (1/2 × VCM) voltage sees a gain of
+2. The output of this 2nd stage is then the original common-mode voltage plus the inverted signal from the
output of the first stage. The output of this 2nd stage then appears directly at the output of the noninverting final
stage. The inverting node of the inverting output stage is also biased to the common-mode voltage, equal to
the common-mode voltage appearing at the output of the 2nd stage, creating no current flow and placing the
desired VCM at the output of this stage as well.
low-power, differential I/O, 4th-order active filter
The OPA4684 can give a very capable gain block for low-power active filters. The quad design lends itself very
well to differential active filters. Where the filter topology is looking for a simple gain function to implement the
filter, the noninverting configuration is preferred to isolate the filter elements from the gain elements in the
design. Figure 49 shows an example of a very low-power, 10-MHz, 4th-order Butterworth, low-pass Sallen-Key
filter. Often, these filters are designed at an amplifier gain of 1 to minimize amplifier bandwidth interaction with
the desired filter shape. Since the OPA4684 shows minimal bandwidth change with gain, this would not be a
constraint in this design. The example of Figure 49 designs the filter for a differential gain of 4 in each differential
stage. This DC-coupled design gives a signal gain of 16 V/V in the passband with a f_3dB at 10 MHz. The design
places the higher Q stage first to allow the lower Q 2nd stage to roll off the peaked noise of the first stage. The
resistor values have been adjusted slightly to account for the amplifier group delay.
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Figure 48. High Gain, DC-Coupled, Single to Differential Conversion
Figure 49. Low-Power, Differential I/O, 4th-Order Butterworth Active Filter
While this circuit is bipolar, using ±5-V supplies, it can easily be adapted to single-supply operation. This is
typically done by providing a supply midpoint reference at the noninverting inputs then adding DC-blocking caps
at each input and in series with the amplifier gain resistor, RG. This will add two real zeroes in the response,
transforming this circuit into a bandpass. Figure 50 shows the frequency response for the filter of Figure 49.
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Figure 50. Low-Power, Differential 4th-Order, 100MHz Butterworth
low-power DSL transceiver interface
With four amplifiers available, the quad OPA4684 can meet the needs for both differential driver and receiver
in a low-power xDSL line interface design. Figure 51 shows a simplified design example. Two amplifiers are
used as a noninverting differential driver while the other two implement the driver echo cancellation and receiver
amplifier function. This example shows a single +12V design where the drive side is taking a 2-Vp-p maximum
input from the transmit filter and providing a differential gain of 7, giving a maximum 14-Vp-p differential output
swing. This is coupled through 50Ω matching resistors and a 1:1 transformer to give a maximum 7 Vp-p on a
100Ω line. This 7 Vp-p corresponds to a 10-dBm line power with a 3.5 crest factor.
The differential receiver is configured as an inverting summing stage where the outputs of the driver are
cancelled prior to appearing at the output of the receive amplifiers. This is done by summing the output voltages
for the drive amplifiers and their attenuated and inverted levels (at the transformer input) into the inverting inputs
of each receiver amplifier. The resistor values are set in Figure 51 to give perfect drive signal cancellation if the
drive signal is attenuated by 1/2 going from the drive amplifier outputs to the transformer input. The signal
received through the transformer has a gain of 1 through the receive amplifiers. Higher gain could easily be
provided by scaling the resistors summing into the inverting inputs of the receiver amplifiers down while keeping
the same ratio between them.
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Figure 51. Low-Power, XDSL Transceiver Design.
dual-channel, differential ADC driver
Where a low-power, single-supply, interface to a differential input +5-V ADC is required, the circuit of
Figure 52 can provide a high dynamic range, medium gain interface for dual high-performance ADCs. The circuit
of Figure 52 uses two amplifiers in the differential inverting configuration. The common-mode voltage is set on
the noninverting inputs to the supply midscale. In this example, the input signal is coupled in through a 1:2
transformer. This provides both signal gain, single to differential conversion, and a reduction in noise figure. To
show a 50Ω input impedance at the input to the transformer, two 200Ω resistors are required on the transformer
secondary. These two resistors are also the amplifier gain elements. Since the same DC voltage appears on
both inverting nodes in the circuit of Figure 52, no DC current will flow through the transformer, giving a DC gain
of 1 to the output for this common-mode voltage, VCM.
The circuit of Figure 52 is particularly suitable for a moderate resolution dual ADC used as I/Q samplers. The
optional 500Ω resistors to ground on each amplifier output can be added to improve the 2nd-and 3rd-harmonic
distortion by > 15dB if higher dynamic range is required. Figure 53 shows the harmonic distortion for the circuit
of Figure 52 with and without these pull-down resistors. The 5 mA added output stage current significantly
improves linearity if that is required. The measured 2nd-harmonic distortion is consistently lower than the
3rd-harmonics for this balanced differential design. It is particularly helpful for this low-power design if there are
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no grounds in the signal path after the low-level signal at the transformer input. The two pull-down resistors do
show a signal path ground and should be connected at the same physical point to ground to eliminate
imbalanced ground return currents from degrading 2nd-harmonic distortion.
Figure 52. Single-Supply Differential ADC Driver (1 of 2 Channels)
Figure 53. Harmonic Distortion vs Frequency
design-in tools
demonstration boards
Two PC boards are available to assist in the initial evaluation of circuit performance using the OPA4684 in its
two package styles. Both of these are available, free, as an unpopulated PC board delivered with descriptive
documentation. The summary information for these boards is shown in Table 1.
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Table 1. Evaluation Module Ordering Information
PRODUCT
OPA4684ID
OPA4684IDBW
PACKAGE
BOARD PART NUMBER
LITERATURE NUMBER
SO−14
DEM−OPA468xD
SBOU016
TSSOP−14
DEM−OPA46xxDPW
—
macromodels
Computer simulation of circuit performance using SPICE is often useful in predicting the performance of analog
circuits and systems. This is particularly true for Video and RF amplifier circuits where parasitic capacitance and
inductance can have a major effect on circuit performance. Check the TI web site (www.ti.com) for SPICE
macromodels within the OPA4684 product folder. These models do a good job of predicting small-signal AC and
transient performance under a wide variety of operating conditions. They do not do as well in predicting
distortion or dG/dP characteristics. These models do not attempt to distinguish between the package types in
their small-signal AC performance.
operating suggestions
setting resistor values to optimize bandwidth
Any current-feedback op amp like the OPA4684 can hold high bandwidth over signal-gain settings with the
proper adjustment of the external resistor values. A low-power part like the OPA4684 typically shows a larger
change in bandwidth due to the significant contribution of the inverting input impedance to loop-gain changes
as the signal gain is changed. Figure 54 shows a simplified analysis circuit for any current-feedback amplifier.
Figure 54. Current-Feedback Transfer Function Analysis Circuit
The key elements of this current-feedback op amp model are:
α — Buffer gain from the noninverting input to the inverting input
RI — Buffer output impedance
iERR — Feedback error current signal
Z(S) — Frequency-dependent open-loop transimpedance gain from iERR to VO
The buffer gain is typically very close to 1.00 and is normally neglected from signal gain considerations. It will,
however, set the CMRR for a single op amp differential amplifier configuration. For the buffer gain a < 1.0, the
CMRR = _20 × log(1 − α). The closed-loop input stage buffer used in the OPA4684 gives a buffer gain more
closely approaching 1.00 and this shows up in a slightly higher CMRR than previous current-feedback op amps.
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RI, the buffer output impedance, is a critical portion of the bandwidth control equation. The OPA4684 reduces
this element to approximately 4.0 Ω using the local loop gain of the input buffer stage. This significant reduction
in output impedance, on very low power, contributes significantly to extending the bandwidth at higher gains.
A current-feedback op amp senses an error current in the inverting node (as opposed to a differential input error
voltage for a voltage-feedback op amp) and passes this on to the output through an internal
frequency-dependent transimpedance gain. The Typical Characteristics show this open-loop transimpedance
response. This is analogous to the open-loop voltage gain curve for a voltage-feedback op amp. Developing
the transfer function for the circuit of Figure 53 gives Equation 1:
V
O+
V
I
ǒ
R
a 1 ) RF
G
Ǔ
ǒ Ǔ
R
1)
F
R )R 1)
R
F I
G
Z
+
ƪ ǒ
aNG
NG +
R )R NG
1 ) FZ I
(s)
1)
R
R
F
G
Ǔƫ
(1)
(s)
This is written in a loop-gain analysis format where the errors arising from a non-infinite open-loop gain are
shown in the denominator. If Z(S) were infinite over all frequencies, the denominator of Equation 1 would reduce
to 1 and the ideal desired signal gain shown in the numerator would be achieved. The fraction in the denominator
of Equation 1 determines the frequency response. Equation 2 shows this as the loop-gain equation.
Z
(s)
+ Loop Gain
R ) R NG
F
I
(2)
If 20 × log(RF + NG × RI) were drawn on top of the open-loop transimpedance plot, the difference between the
two would be the loop gain at a given frequency. Eventually, Z(S) rolls off to equal the denominator of Equation
2 at which point the loop gain has reduced to 1 (and the curves have intersected). This point of equality is where
the amplifier’s closed-loop frequency response given by Equation 1 will start to roll off, and is exactly analogous
to the frequency at which the noise gain equals the open-loop voltage gain for a voltage feedback op amp. The
difference here is that the total impedance in the denominator of Equation 2 may be controlled somewhat
separately from the desired signal gain (or NG).
The OPA4684 is internally compensated to give a maximally flat frequency response for RF = 800 Ω at
NG = 2 on ±5-V supplies. That optimum value goes to 1.0 kΩ on a single +5V supply. Normally, with a
current-feedback amplifier, it is possible to adjust the feedback resistor to hold this bandwidth up as the gain
is increased. The CFBPLUS architecture has reduced the contribution of the inverting input impedance to
provide exceptional bandwidth to higher gains without adjusting the feedback resistor value. The Typical
Characteristics show the small-signal bandwidth over gain with a fixed feedback resistor.
Putting a closed-loop buffer between the noninverting and inverting inputs does bring some added
considerations. Since the voltage at the inverting output node is now the output of a locally closed-loop buffer,
parasitic external capacitance on this node can cause frequency response peaking for the transfer function from
the noninverting input voltage to the inverting node voltage. While it is always important to keep the inverting
node capacitance low for any current-feedback op amp, it is critically important for the OPA4684. External layout
capacitance in excess of 2 pF will start to peak the frequency response. This peaking can be easily reduced
by then increasing the feedback resistor value−but it is preferable, from a noise and dynamic range standpoint,
to keep that capacitance low, allowing a close to nominal 800-Ω feedback resistor for flat frequency response.
Very high parasitic capacitance values on the inverting node (> 5 pF) can possibly cause input stage oscillation
that cannot be filtered by a feedback element adjustment.
At very high gains, 2nd-order effects in the inverting output impedance cause the overall response to peak up.
If desired, it is possible to retain a flat frequency response at higher gains by adjusting the feedback resistor
to higher values as the gain is increased. Since the exact value of feedback that will give a flat frequency
response depends strongly in inverting and output node parasitic capacitance values, it is best to experiment
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in the specific board with increasing values until the desired flatness (or pulse response shape) is obtained. In
general, increasing RF (and adjusting RG then to the desired gain) will move towards flattening the response,
while decreasing it will extend the bandwidth at the cost of some peaking.
output current and voltage
The OPA4684 provides output voltage and current capabilities that can support the needs of driving
doubly-terminated 50-Ω lines. For a 100-Ω load at the gain of +2, (see Figure 41), the total load is the parallel
combination of the 100-Ω load and the 1.6-kΩ total feedback network impedance. This 94-Ω load will require
no more than 40-mA output current to support the ±3.8-V minimum output voltage swing specified for 100-Ω
loads. This is well under the specified minimum +110 mA/−90mA output current specifications over the full
temperature range.
The specifications described above, though familiar in the industry, consider voltage and current limits
separately. In many applications, it is the voltage × current, or V-I product, which is more relevant to circuit
operation. Refer to the Output Current and Voltage Limitations curve (Figure 20) in the Typical Characteristics.
The X- and Y-axes of this graph show the zero-voltage output current limit and the zero-current output voltage
limit, respectively. The four quadrants give a more detailed view of the OPA4684’s output drive capabilities.
Superimposing resistor load lines onto the plot shows the available output voltage and current for specific loads.
The minimum specified output voltage and current over temperature are set by worst-case simulations at the
cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers
shown in the Electrical Characteristic tables. As the output transistors deliver power, their junction temperatures
will increase, decreasing their VBE’s (increasing the available output voltage swing) and increasing their current
gains (increasing the available output current). In steady-state operation, the available output voltage and
current will always be greater than that shown in the over temperature specifications since the output stage
junction temperatures will be higher than the minimum specified operating ambient.
To maintain maximum output stage linearity, no output short-circuit protection is provided. This will not normally
be a problem since most applications include a series-matching resistor at the output that will limit the internal
power dissipation if the output side of this resistor is shorted to ground. However, shorting the output pin directly
to a power-supply pin will, in most cases, destroy the amplifier. If additional short-circuit protection is required,
consider a small-series resistor in the power-supply leads. This will, under heavy output loads, reduce the
available output voltage swing. A 5-Ω series resistor in each power-supply lead will limit the internal power
dissipation to less than 1 W for an output short-circuit while decreasing the available output voltage swing only
0.25 V for up to 50 mA desired load currents. This slight drop in available swing is more if multiple channels are
driving heavy loads simultaneously. Always place the 0.1-µF power-supply decoupling capacitors after these
supply current limiting resistors directly on the supply pins.
driving capacitive loads
One of the most demanding, and yet very common load conditions, for an op amp is capacitive loading. Often,
the capacitive load is the input of an ADC—including additional external capacitance which may be
recommended to improve ADC linearity. A high-speed, high open-loop gain amplifier like the OPA4684 can be
very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed
directly on the output pin. When the amplifier’s open-loop output resistance is considered, this capacitive load
introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions
to this problem have been suggested. When the primary considerations are frequency response flatness, pulse
response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from
the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load.
This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency.
The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin
and improving stability.
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The Typical Characteristics show the recommended RS vs CLOAD and the resulting frequency response at the
load. The 1-kΩ resistor shown in parallel with the load capacitor is a measurement path and may be omitted.
Parasitic capacitive loads greater than 5 pF can begin to degrade the performance of the OPA4684. Long PC
board traces, unmatched cables, and connections to multiple devices can easily cause this value to be
exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible
to the OPA4684 output pin (see Board Layout Guidelines).
distortion performance
The OPA4684 provides very low distortion in a low-power part. The CFBPLUS architecture also gives two
significant areas of distortion improvement. First, in operating regions where the 2nd-harmonic distortion due
to output stage nonlinearities is very low (frequencies < 1MHz, low output swings into light loads) the
linearization at the inverting node provided by the CFBPLUS design gives 2nd-harmonic distortions that extend
into the −90 dBc region. Previous current-feedback amplifiers have been limited to approximately −85 dBc due
to the nonlinearities at the inverting input. The second area of distortion improvement comes in a distortion
performance that is largely gain independent. To the extent that the distortion at a particular output power is
output stage dependent, 3rd-harmonics particularly, and to a lesser extend 2nd-harmonic distortion, is constant
as the gain is increased. This is due to the constant loop gain versus signal gain provided by the CFBPLUS
design. As shown in the Typical Characteristic curves, while the 3rd-harmonic is constant with gain, the
2nd-harmonic degrades at higher gains. This is largely due to board parasitic issues. Slightly imbalanced load
return currents will couple into the gain resistor to cause a portion of the 2nd-harmonic distortion. At high gains,
this imbalance has more gain to the output giving reduced 2nd-harmonic distortion. Differential stages using
two of the channels together can reduce this 2nd-harmonic issue enormously getting back to an essentially gain
independent distortion.
Relative to alternative amplifiers with < 2-mA/ch supply current, the OPA4684 holds much lower distortion at
higher frequencies (> 5 MHz) and to higher gains. Generally, until the fundamental signal reaches very high
frequency or power levels, the 2nd-harmonic will dominate the distortion with a lower 3rd-harmonic component.
Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Remember that
the total load includes the feedback network−in the noninverting configuration (see Figure 41) this is the sum
of RF + RG, while in the inverting configuration it is just RF. Also, providing an additional supply decoupling
capacitor (0.1 µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB
to 6dB).
In most op amps, increasing the output voltage swing increases harmonic distortion directly. A low-power part
like the OPA4684 includes quiescent boost circuits to provide the large-signal bandwidth in the Electrical
Characteristics. These act to increase the bias in a very linear fashion only when high slew rate or output power
are required. This also acts to actually reduce the distortion slightly at higher output power levels. The Typical
Characteristic curves show the 2nd-harmonic holding constant from 500 mVp-p to 5 Vp-p outputs while the
3rd-harmonics actually decrease with increasing output power.
The OPA4684 has an extremely low 3rd-order harmonic distortion, particularly for light loads and at lower
frequencies. This also gives low 2-tone, 3rd-order intermodulation distortion as shown in the Typical
Characteristic curves. Since the OPA4684 includes internal power boost circuits to retain good full-power
performance at high frequencies and outputs, it does not show a classical 2-tone, 3rd-order intermodulation
intercept characteristic. Instead, it holds relatively low and constant 3rd-order intermodulation spurious levels
over power. The Typical Characteristic curves show this spurious level as a dBc below the carrier at fixed center
frequencies swept over single-tone power at a matched 50-Ω load. These spurious levels drop significantly (>
12 dB) for lighter loads than the 100 Ω used in the 2-Tone, 3rd-Order Intermodulation Distortion curve. Converter
inputs for instance will see < −82dBc 3rd-order spurious to 10 MHz for full-scale inputs. For even lower 3rd-order
intermodulation distortion to much higher frequencies, consider the OPA2691 dual or OPA691 and OPA685
single-channel current-feedback amplifiers.
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noise performance
Wideband current-feedback op amps generally have a higher output noise than comparable voltage-feedback
op amps. The OPA4684 offers an excellent balance between voltage and current noise terms to achieve low
output noise in a low-power amplifier. The inverting current noise (17 pA/√Hz) is comparable to most other
current-feedback op amps while the input voltage noise (3.7 nV/√Hz) is lower than any unity-gain stable,
comparable slew rate, voltage-feedback op amp. This low input voltage noise was achieved at the price of
higher noninverting input current noise (9.4 pA/√Hz). As long as the AC source impedance looking out of the
noninverting node is less than 200 Ω, this current noise will not contribute significantly to the total output noise.
The op amp input voltage noise and the two input current noise terms combine to give low output noise under
a wide variety of operating conditions. Figure 55 shows the op amp noise analysis model with all the noise terms
included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz
or pA/√Hz.
Figure 55. Op Amp Noise Analysis Model
The total output spot noise voltage can be computed as the square root of the sum of all squared output noise
voltage contributors. Equation 3 shows the general form for the output noise voltage using the terms presented
in Figure 52.
E
O
+
Ǹǒ
E
2
NI
ǒ BNRSǓ
) I
2
) 4kTR
Ǔ
S
G
2
N
ǒ
Ǔ
) I R
BI F
2
) 4kTR G
F N
(3)
Dividing this expression by the noise gain (GN = (1+RF/RG)) will give the equivalent input referred spot noise
voltage at the noninverting input, as shown in Equation 4.
E
O
+
Ǹ
E
2
NI
) ǒI R Ǔ
BN S
2
) 4kTR )
S
ǒ Ǔ
I R
BI F
G
N
2
)
4kTR
G
F
(4)
N
Evaluating these two equations for the OPA4684 circuit and component values presented in Figure 41 will give
a total output spot noise voltage of 16.3 nV/√Hz and a total equivalent input spot noise voltage of 8.1 nV/√Hz.
This total input referred spot noise voltage is higher than the 3.7-nV/√Hz specification for the op amp voltage
noise alone. This reflects the noise added to the output by the inverting current noise times the feedback resistor.
As the gain is increased, this fixed output noise power term contributes less to the total output noise and the
total input referred voltage noise given by Equation 3 will approach just the 3.7 nV/√Hz of the op amp itself. For
example, going to a gain of +20 in the circuit of Figure 41, adjusting only the gain resistor to 42.1 Ω, will give
a total input referred noise of 3.9 nV/√Hz. A more complete description of op amp noise analysis can be found
in the Texas Instruments application note, AB−103, Noise Analysis for High Speed Op Amps (SBOA066),
located at www.ti.com.
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dc accuracy and offset control
A current-feedback op amp like the OPA4684 provides exceptional bandwidth in high gains, giving fast pulse
settling but only moderate DC accuracy. The Electrical Characteristics show an input offset voltage comparable
to high slew rate voltage-feedback amplifiers. However, the two input bias currents are somewhat higher and
are unmatched. Whereas bias current cancellation techniques are very effective with most voltage-feedback
op amps, they do not generally reduce the output DC offset for wideband current-feedback op amps. Since the
two input bias currents are unrelated in both magnitude and polarity, matching the source impedance looking
out of each input to reduce their error contribution to the output is ineffective. Evaluating the configuration of
Figure 41, using worst-case +25°C input offset voltage and the two input bias currents, gives a worst-case output
offset range equal to:
±(NG × VOS(MAX)) + (IBN × RS/2 × NG) ± (IBI × RF)
where NG = noninverting signal gain
= ±(2 × 4.0 mV) ± (13 µA × 25 Ω × 2) ± (800 Ω × 17 µA)
= ±8 mV + 0.65 mV ± 13.6 mV
= ±22.3 mV
While the last term, the inverting bias current error, is dominant in this low-gain circuit, the input offset voltage
will become the dominant DC error term as the gain exceeds 5 V/V. Where improved DC precision is required
in a high-speed amplifier, consider the OPA656 single and OPA2822 dual voltage-feedback amplifiers.
thermal analysis
The OPA4684 will not require external heatsinking or airflow most applications. Maximum desired junction
temperature will set the maximum allowed internal power dissipation as described below. In no case should the
maximum junction temperature be allowed to exceed 175°C.
Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the
sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power.
Quiescent power is simply the specified no-load supply current times the total supply voltage across the part.
PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum
when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). Under this
condition PDL = VS2/(4 × RL) where RL includes feedback network loading.
Note that it is the power in the output stage and not into the load that determines internal power dissipation.
As an absolute worst-case example, compute the maximum TJ using an OPA4684IPW (TSSOP-14 package)
in the circuit of Figure 41 operating at the maximum specified ambient temperature of +85°C with all channels
driving a grounded 100-Ω load to 2.5 VDC.
PD = 10 V × 7.8 mA + 4 × (52 /(4 × (100 Ω || 1.6 kΩ))) = 144 mW
Maximum TJ = +85°C + (0.144 W × 110°C/W) = 101°C.
This maximum operating junction temperature is well below most system level targets. Most applications will
be lower than this since an absolute worst-case output stage power was assumed in this calculation with all 4
channels running maximum output power simultaneously.
board layout guidelines
Achieving optimum performance with a high-frequency amplifier like the OPA4684 requires careful attention to
board layout parasitics and external component types. Recommendations that will optimize performance
include:
−
28
Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on
the output and inverting input pins can cause instability; on the noninverting input, it can react with the
source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all of the ground and power planes around those pins.
Otherwise, ground and power planes should be unbroken elsewhere on the board.
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−
Minimize the distance (< 0.25”) from the power-supply pins to high-frequency 0.1-µF decoupling
capacitors. At the device pins, the ground and power-plane layout should not be in close proximity to the
signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the
decoupling capacitors. The power-supply connections should always be decoupled with these
capacitors. An optional supply de-coupling capacitor (0.01 µF) across the two power supplies (for
bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2 µF to 6.8 µF)
decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins.
These may be placed somewhat farther from the device and may be shared among several devices in
the same area of the PC board.
−
Careful selection and placement of external components will preserve the high-frequency performance
of the OPA4684. Resistors should be a very low reactance type. Surface-mount resistors work best and
allow a tighter overall layout. Metal film and carbon composition axially-leaded resistors can also
provide good high-frequency performance. Again, keep their leads and PC-board trace length as short
as possible. Never use wirewound type resistors in a high-frequency application. Since the output pin
and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and
series output resistor, if any, as close as possible to the output pin. The quad amplifier pinout allows
each output and inverting input to be connected by the feedback element with virtually no trace length.
Other network components, such as noninverting input termination resistors, should also be placed
close to the package. The frequency response is primarily determined by the feedback resistor value as
described previously. Increasing its value will reduce the peaking at higher gains, while decreasing it will
give a more peaked frequency response at lower gains. The 800-Ω feedback resistor used in the Typical
Characteristics at a gain of +2 on ±5-V supplies is a good starting point for design. Note that a 800-Ω
feedback resistor, rather than a direct short, is required for the unity-gain follower application. A
current-feedback op amp requires a feedback resistor even in the unity-gain follower configuration to
control stability.
−
Connections to other wideband devices on the board may be made with short direct traces or through
onboard transmission lines. For short connections, consider the trace and the input to the next device as
a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably with
ground and power planes opened up around them. Estimate the total capacitive load and set RS from
the plot of recommended RS vs CLOAD. Low parasitic capacitive loads (< 5 pF) may not need an RS
since the OPA4684 is nominally compensated to operate with a 2-pF parasitic load. If a long trace is
required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable,
implement a matched impedance transmission line using microstrip or stripline techniques (consult an
ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is normally
not necessary on board, and in fact a higher impedance environment will improve distortion, see the
distortion versus load plots. With a characteristic board trace impedance defined based on board
material and trace dimensions, a matching series resistor into the trace from the output of the OPA4684
is used, as well as a terminating shunt resistor at the input of the destination device. Remember also that
the terminating impedance will be the parallel combination of the shunt resistor and the input impedance
of the destination device; this total effective impedance should be set to match the trace impedance.
The high output voltage and current capability of the OPA4684 allows multiple destination devices to be
handled as separate transmission lines, each with their own series and shunt terminations. If the 6-dB
attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be
series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the
series resistor value as shown in the plot of RS vs CLOAD. This will not preserve signal integrity as well
as a doubly-terminated line. If the input impedance of the destination device is LOW, there will be some
signal attenuation due to the voltage divider formed by the series output into the terminating impedance.
−
Socketing a high-speed part like the OPA4684 is not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network
which can make it almost impossible to achieve a smooth, stable frequency response. Best results are
obtained by soldering the OPA4684 onto the board.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
SGLS145B − AUGUST 2003 − REVISED FEBRUARY 2004
input and esd protection
The OPA4684 is built using a very high-speed complementary bipolar process. The internal junction breakdown
voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the
Absolute Maximum Ratings table where an absolute maximum 13 V across the supply pins is reported. All
device pins have limited ESD protection using internal diodes to the power supplies, as shown in Figure 56.
Figure 56. Internal ESD Protection
These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection
diodes can typically support 30-mA continuous current. Where higher currents are possible (e.g. in systems with
±15-V supply parts driving into the OPA4684), current limiting series resistors should be added into the two
inputs. Keep these resistor values as low as possible since high values degrade both noise performance and
frequency response.
30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
OPA4684MJD
ACTIVE
CDIP SB
JD
Pins Package Eco Plan (2)
Qty
14
1
TBD
Lead/Ball Finish
MSL Peak Temp (3)
POST-PLATE N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA4684M :
• Catalog: OPA4684
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
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