TOSHIBA
TLCS-900 Series
TMP96C041AF
CMOS 16-bit Microcontrollers
TMP96C041AF
1.
Outline and Device Characteristics
The TMP96C041AF are high-speed advanced 16-bit microcontrollers developed for controlling medium to large-scale
equipment. The TMP96C041AF has the improved bus release
function, serial interface and RAMless for TMP96C141AF. Otherwise, the devices function in the same way.
The TMP96C041AF is housed in an 80-pin flat package
and is pin compatible with TMP96C141F except the P92
(CTS0/SCLK0). Device characteristics are as follows:
(1) Original 16-bit CPU
• TLCS-90 instruction mnemonic upward compatible.
• 16M-byte linear address space
• General-purpose registers and register bank system
• 16-bit multiplication/division and bit transfer/arithmetic
instructions
• High-speed micro DMA
- 4 channels (1.6µs/2 bytes @ 20MHz)
(2) Minimum instruction execution time
- 200ns @ 20MHz
(3) Internal RAM: None
Internal ROM: None
(4) External memory expansion
• Can be expanded up to 16M bytes (for both programs and
data).
• Can mix 8- and 16-bit external data buses.
(5) 8-bit timers: 2 channels
(6) 8-bit PWM timers: 2 channels
(7) 16-bit timers: 2 channels
(8) Pattern generators: 4 bits, 2 channels
(9) Serial interface: 2 channels
(10) 10-bit A/D converter: 4 channels
(11) Watchdog timer
(12) Chip select/wait controller: 3 blocks
(13) Interrupt functions
• 3 CPU interrupts… …SWI instruction, privileged violation,
and Illegal instruction
• 14 internal interrupts
7-level priority can be set.
• 6 external interrupts
(14) I/O ports
- 47pins
(15) Standby function : 3 halt modes (RUN, IDLE, STOP)
The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equipments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
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1/20
TMP96C041AF
Figure 1. TMP96C041AF Block Diagram
2/20
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TMP96C041AF
2.
Pin Assignment and Functions
The assignment of input/output pins for TMP96C041AF, their
name and outline functions are described below.
2.1 Pin Assignment
Figure 2.1 shows pin assignment of TMP96C041AF.
Figure 2.1. Pin Assignment (80-pin QFP)
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TMP96C041AF
2.2 Pin Names and Functions
The names of input/output pins and their functions are described below.
Table 2.2. Pin Names and Functions
Number
of Pins
I/O
P00 ~ P07
AD0 ~ AD7
8
I/O
Tri-state
Port 0: I/O port that allows I/O to be selected on a bit basis
Address / data (lower): 0 - 7 for address / data bus
P10 ~ P17
AD8 ~ AD15
A8 ~ A15
8
I/O
Tri-state
Output
Port 1: I/O port that allows I/O to be selected on a bit basis
Address data (upper): 8 - 15 for address / data bus
Address: 8 to 15 for address bus
P20 ~ P27
A0 ~ A7
A16 ~ A23
8
I/O
Output
Output
Port 2: I/O port that allows selection of I/O on a bit basis (with pull-down resistor)
Address: 0 - 7 for address bus
Address: 16 - 23 for address bus
P30
RD
1
Output
Output
Port 30: Output port
Read: Strobe signal for reading external memory
P31
WR
1
Output
Output
Port 31: Output port
Write: Strobe signal for writing data on pins AD0 -7
P32
HWR
1
I/O
Output
Port 32: I/O port (with pull-up resistor)
High write: Strobe signal for writing data on pins AD8 - 15
P33
WAIT
1
I/O
Input
Port 33: I/O port (with pull-up resistor)
Wait: Pin used to request CPU bus wait
P34
BUSRQ
1
I/O
Input
Port 34: I/O port (with pull-up resistor)
Bus request: Signal used to request high impedance for AD0 - 15, A0 - 23, RD, WR, HWR, R/W, RAS, CS0,
CS1, and CS2 pins. (For external DMAC)
P35
BUSAK
1
I/O
Output
Port 35: I/O (with pull-up resistor)
Bus acknowledge: Signal indicating that AD0 - 15, A0 - 23, RD, WR, HWR, R/W, RAS, CS0, CS1, and CS2
pins are at high impedance after receiving BUSRQ. (For external DMAC)
P36
R/W
1
I/O
Output
Port 36: I/O port (with pull-up resistor)
Read/write: 1 represents read or dummy cycle; 0, write cycle.
P37
RAS
1
I/O
Output
Port 37: I/O port (with pull-up resistor)
Row address strobe: Outputs RAS strobe for DRAM.
P40
CS0
CAS0
1
I/O
Output
Output
Port 40: I/O port (with pull-up resistor)
Chip select 0: Outputs 0 when address is within specified address area.
Column address strobe 0: Outputs CAS strobe for DRAM when address is within specified address area.
Pin Name
Note:
4/20
Functions
With the external DMA controller, this device’s built-in memory or built-in I/O
cannot be accessed using the BUSRQ and BUSAK pins.
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TMP96C041AF
Number
of Pins
I/O
P41
CS1
CAS1
1
I/O
Output
Output
Port 41: I/O port (with pull-up resistor)
Chip select 1: Outputs 0 if address is within specified address area.
Column address strobe 1: Outputs CAS strobe for DRAM if address is within specified address area.
P42
CS2
CAS2
1
I/O
Output
Output
Port 42: I/O port (with pull-up resistor)
Chip select 2: Outputs 0 if address is within specified address area.
Column address strobe 2: Outputs CAS strobe for DRAM if address is within specified address area.
P50 ~ P53
AN0 ~ AN3
4
Input
Input
Port 5: Input port
Analog input: Input to A/D converter
VREF
1
Input
Pin for reference voltage input to A/D converter
AGND
Pin Name
Functions
1
Input
Ground pin for A/D converter
P60 ~ P63
PG00 ~ PG03
4
I/O
Output
Ports 60 - 63: I/O ports that allow selection of I/O on a bit basis (with pull-up resistor)
Pattern generator ports: 00 - 03
P64 ~ P67
PG10 ~ PG13
4
I/O
Output
Ports 64 - 67: I/O ports that allow selection of I/O on a bit basis (with pull-up resistor)
Pattern generator ports: 10 - 13
P70
T10
1
I/O
Input
Port 70: I/O port (with pull-up resistor)
Timer input 0: Timer 0 input
P71
T01
1
I/O
Output
Port 71: I/O port (with pull-up resistor)
Timer output 1: Timer 0 or 1 output
P72
T02
1
I/O
Output
Port 72: I/O port (with pull-up resistor)
PWM output 2: 8-bit PWM timer 2 output
P73
T03
1
I/O
Output
Port 73: I/O port (with pull-up resistor)
PWM output 3: 8-bit PWM timer 3 output
P80
TI4
INT4
1
I/O
Input
Input
Port 80: I/O port (with pull-up resistor)
Timer input 4: Timer 4 count/capture trigger signal input
Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge
P81
TI5
INT5
1
I/O
Input
Input
Port 81: I/O port (with pull-up resistor)
Timer input 5: Timer 4 count/capture trigger signal input
Interrupt request pin 5: Interrupt request pin with rising edge
P82
TO4
1
I/O
Output
Port 82: I/O port (with pull-up resistor)
Timer output 4: Timer 4 output pin
P83
TO5
1
I/O
Output
Port 83: I/O port (with pull-up resistor)
Timer output 5: Timer 4 output pin
Note 1: Case of the settable CS2 and CAS2; when TMP96C041AF is bus release, this pin is not added the internal pull-down resistor but is added the internal
pull-up resistor.
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TMP96C041AF
Number
of Pins
I/O
P84
TI6
INT6
1
I/O
Input
Input
Port 84: I/O port (with pull-up resistor)
Timer input 6: Timer 5 count/capture trigger signal input
Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge
P85
TI7
INT7
1
I/O
Input
Input
Port 85: I/O port (with pull-up resistor)
Timer input 7: Timer 5 count/capture trigger signal input
Interrupt request pin 7: Interrupt request pin with rising edge
P86
TO6
1
I/O
Output
Port 86: I/O port (with pull-up resistor)
Timer output 6: Timer 5 output pin
P87
INT0
1
I/O
Input
Port 87: I/O port (with pull-up resistor)
Interrupt request pin 0: Interrupt request pin with programmable level/rising edge
P90
TXD0
1
I/O
Output
Port 90: I/O port (with pull-up resistor)
Serial send data 0
P91
RXD0
1
I/O
Input
Port 91: I/O port (with pull-up resistor)
Serial receive data 0
P92
CTS0
SCLK0
1
I/O
Input
Port 92: I/O port (with pull-up resistor)
Serial data send enable 0 (Clear to Send)
Serial clock I/O 0
P93
TXD1
1
I/O
Output
Port 93: I/O port (with pull-up resistor)
Serial send data 1
P94
RXD1
1
I/O
Input
Port 94: I/O port (with pull-up resistor)
Serial receive data 1
P95
SCLK1
1
I/O
I/O
Port 95: I/O port (with pull-up resistor)
Serial clock I/O 1
WDTOUT
1
Output
Watchdog timer output pin
1
Input
Non-maskable interrupt request pin: Interrupt request pin with falling edge.
Can also be operated at rising edge by program.
Pin Name
NMI
Functions
CLK
1
Output
Clock output: Outputs X1 ÷ 4 clock. Pulled-up during reset.
EA
1
Input
External access: 0 should be inputted with TMP96C041AF.
ALE
1
Output
Address latch enable
RESET
1
Input
Reset: Initializes LSI. (With pull-up resistor)
X1/X2
2
I/O
VCC
2
Power supply pin (+ 5V)
VSS
3
GND pin (0V)
Note:
6/20
Oscillator connecting pin
Pull-up/pull-down resistor can be released from the pin by software (except the RESET pin).
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TMP96C041AF
3.
Operation
This section describes in blocks the functions and basic operations of the TMP96C041AF device.
Check the chapter Guidelines and Restrictions for proper
care of the device.
3.1 CPU
The TMP96C041AF device has a built-in high-performance
16-bit CPU. (For CPU operation, see TLCS-900 CPU in the
book Core Architecture User Manual.)
3.2 Memory Map
The TMP96C041AF has two register modes. One is minimum
mode; in this mode, the area of program memory is 64K bytes
maximum. The other is maximum mode; in this mode, the area
of the program memory is 16M bytes maximum.
Both minimum and maximum modes are the data memory area 16M bytes maximum.
That is, the program memory can locate 0H ~ FFFFFFH
in maximum mode.
(1)
Internal /O Devices
The TMP96C041AF uses the address space of 128
bytes for the internal I/O devices area. This area is
located to 0H ~ 7FH.
The CPU can access the internal I/O devices area with
using short instruction code of direct addressing
mode.
Check the access area of each addressing mode and
the memory map in Fig. 3.2 (1).
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7/20
TMP96C041AF
3.2 Memory Map
Figure 3.2 is a memory map of the TMP96C041AF.
Note:
The start address after reset is 8000H. Resetting sets the stack pointer (XSP) on the system mode side to 100H.
Figure 3.2. Memory Map
8/20
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TMP96C041AF
(2)
CS1 Area (Chip Select/Wait Controller)
address area for CS1 (only B1C1.0 = “00”). Show the
address area of CS1 in Fig. 3.2 (2).
The TMP96C041AF is expanded the part of the
Fig. 3.2 (2). CS1 Address Area
Show the table 3.3 of pin condition at bus release
(BUSAK = 0).
3.3 Bus Release Function
The TMP96C041AF has the internal pull-up and pull down
resistors to fix the bus control signals at bus release.
Table 3.3 Pin Condition at Bus Release (BUSAK = “L”)
Pin state at bus release
Pin Name
Port Mode
P00 - P07
(AD0 - AD7)
P10 - P17
(AD8 - 15/AD8 - 15)
P30 (RD)
P31 (WR)
Function Mode
The status is no-change (these pins are not “Hz”)
These pins are “Hz”.
↑
These pins are “Hz”.
("Hz" stays after these pins driven high level)
↑
The output buffer is “OFF” after these pins driven high.
These pins are added the internal resistor of pull-up. It’s no
relation for the value of output latch.
P36 (R/W)
P40 (CS0/CAS0)
P41 (CS1/CAS1)
↑
↑
P20 - P27
(A16 - A23)
P42 (CS2/CAS2)
↑
(∗) ↑
↑
The output buffer is “OFF” after these pins driven low.
These pins are added the internal resistor of pull-up. It’s no
relation for the value of output latch.
P32 (HWR)
P37 (RAS)
P20 - P27
(A16 - A23)
That is, when it is used for bus release (BUSAK = 0), the
pins of below need pull-up or pull-down resistor for an external
circuit.
P00 - P07 (AD0 AD7)
P10 - P17 (AD8 AD15)
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P30 (RD)
P31 (WR)
(*) P42 has the resistor of programmable pull-down, but
when the bus are released, P42 pin is added a resistor of pullup.
9/20
TMP96C041AF
For the bus release function; show a sample of external
bus interface in the Figure 3.3 (1).
When the bus is released, both internal memory and
internal I/O cannot be accessed. But the internal I/O continues
to run. So, the watchdog timer also continues to run. Therefore, be careful about bus releasing time and set the detection
time of WDT.
Figure 3.3 (1). Example of the Interface Circuit (Bus Releasing Function)
3.4 Serial Function
The TMP96C041AF has two Serial I/O devices. But channel 0
and channel 1 are same function except the handshake (CTS0
10/20
pin) function of the channel 0 and can use I/O interface mode.
Show the part of TMP96C41AF in detail.
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TMP96C041AF
4.
Electrical Characteristics
4.1 Absolute Maximum (TMP96C041AF)
Symbol
Parameter
Vcc
Power Supply Voltage
V IN
Input Voltage
Rating
Unit
-0.5 ~ 6.5
V
-0.5 ~ Vcc + 0.5
V
Σ IOL
Output Current (total)
100
mA
Σ IOH
Output Current (total)
-100
mA
Power Dissipation (Ta = 70°C)
600
mW
PD
260
°C
T STG
Storage Temperature
-65 ~ 150
°C
T OPR
Operating Temperature
-20 ~ 70
°C
T SOLDER
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Soldering Temperature (10s)
11/20
TMP96C041AF
4.2 DC Characteristics (TMP96C041AF)
Vcc = 5V ± 10%, TA = -40 ~ 85°C (4 ~ 16MHz) TA = -20 ~ 70°C (4 ~ 20MHz)
(Typical values are for Ta = 25°C and Vcc = 5V)
Symbol
Parameter
Min
Max
Unit
-0.3
0.8
V
V IL
Input Low Voltage (AD0-15)
V IL1
P2, P3, P4, P5, P6, P7, P8, P9
-0.3
0.3Vcc
V
V IL2
RESET, NMI, INTO (P87)
-0.3
0.25Vcc
V
V IL3
EA
-0.3
0.3
V
V IL4
X1
-0.3
0.2Vcc
V
V IH
Input High Voltage (AD0-15)
2.2
Vcc + 0.3
V
Test Condition
V IH1
P2, P3, P4, P5, P6, P7, P8, P9
0.7Vcc
Vcc + 0.3
V
V IH2
RESET, NMI, INTO (P87)
0.75Vcc
Vcc + 0.3
V
V IH3
EA
Vcc - 0.3
Vcc + 0.3
V
0.8Vcc
Vcc + 0.3
V
0.45
V
I OL = 1.6mA
V
I OH = -400µA
V IH4
X1
V OL
Output Low Voltage
V OH
Output High Voltage
2.4
V OH1
0.75Vcc
V
I OH = -100µA
V OH2
0.9Vcc
V
I OH= - 20µA
-3.5
mA
V EXT - 1.5V
R EXT = 1.1KΩ
µA
0.0 ≤ Vin ≤ Vcc
I DAR
Darlington Drive Current
(8 Output Pins max.)
I LI
Input Leakage Current
TBD (Typ)
±5
I LO
Output Leakage Current
TBD (Typ)
±10
µA
0.2 ≤ Vin ≤ Vcc - 0.2
TBD (Typ)
TBD (Typ)
TBD (Typ)
TBD
10
50
10
mA
mA
µA
µA
t osc = 20MHz
I cc
Operating Current (RUN)
IDLE
STOP (Ta = -20 ~ 70°C)
STOP (Ta = 0 ~ 50°C)
V STOP
Power Down Voltage
(@STOP, RAM Back up)
2.0
6.0
V
R RST
RESET Pull Up Register
50
150
KΩ
C IO
Pin Capacitance
10
pF
V TH
Schmitt Width
RESET, NMI, INTO (P87)
0.4
TBD (Typ)
V
RK
Pull Down/Up Register
50
150
KΩ
Note:
12/20
-1.0
0.2 ≤ Vin ≤ Vcc - 0.2
0.2 ≤ Vin ≤ Vcc - 0.2
V IL2 = 0.2Vcc,
V IH2 = 0.8Vcc
tosc = 1MHz
I-DAR is guaranteed for a total of up to 8 ports.
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TMP96C041AF
4.3 AC Electrical Characteristics (TMP96C041AF)
Vcc = 5V± 10%TA = -40 ~ 85°C (4 ~ 16MHz) TA = -20 ~ 70°C (4MHz ~ 20MHz)
Variable
No.
Symbol
16MHz
20MHz
Parameter
1
tOSC
Osc. Period (= x)
2
tCLK
CLK width
3
tAK
A0 - 23 Valid→CLK Hold
Unit
Min
Max
Min
50
250
62.5
50
ns
85
60.0
ns
11.0
50
ns
2x - 40
0.5x - 20
Max
Min
Max
4
tKA
CLK Valid→A0 - 23 Hold
1.5x - 70
240
50
ns
5
tAL
A0-15 Valid→ALE fall
0.5x - 15
160
10
ns
6
tLA
ALE fall→A0 - 15 Hold
0.5x - 15
160
100
ns
7
tLL
ALE High width
x - 40
23.0
100
ns
8
tLC
ALE fall→RD/WR fall
0.5x - 30
1.0
-5
ns
9
tCL
RD/WR rise→ALE rise
0.5x - 20
11.0
50
ns
10
tACL
A0 - 15 Valid→RD/WR fall
x - 25
38.0
250
ns
11
tACH
A0 - 23 Valid→RD/WR fall
1.5x - 50
44.0
25.0
ns
12
tCA
RD/WR rise→A0 - 23 Hold
0.5x - 20
13
tADL
A0 - 15 Valid→D0 - 15 input
3.0x - 45
143
105
ns
14
tADH
A0 - 23 Valid→D0 - 15 input
3.5x - 65
154
110
ns
15
tRD
RD fall→D0 - 15 input
16
tRR
RD Low width
11.0
2.0x - 50
2.0x - 40
17
tHR
RD rise→D0 - 15 Hold
18
tRAE
RD rise→A0 - 15 output
19
tWW
5
75
85.0
0
ns
50
ns
60.0
ns
0.0
0.0
ns
x - 15
48.0
35.0
ns
WR Low width
2.0x - 40
85.0
60.0
ns
20
tDW
D0 - 15 Valid→WR rise
2.0x - 50
75.0
50.0
ns
21
tWD
WR rise→D0 - 15 Hold
0.5x - 10
21.0
15.0
ns
22
tAEH
A0 - 23 Valid→WAIT input (1WAIT + n mode)
23
tAWL
A0 - 15 Valid→WAIT input (1WAIT + n mode)
24
tCW
RD/WR fall→WAIT Hold (1WAIT + n mode)
25
tAPH
A0 - 23 Valid→PORT input
A0 - 23 Valid→PORT Hold
26
tAPH2
27
tCP
3.5x - 90
129
3.0x - 80
2.0x + 0
108
125.0
2.5x - 120
2.5x + 50
WR rise→PORT Valid
ns
70
ns
100.0
80
206.0
200
85
ns
36
ns
200
ns
175.0
200
ns
28
tASRH
A0 - 23 Valid→RAS fall
1.0x - 40
23.0
10.0
ns
29
tASRL
A0 - 15 Valid→RAS fall
0.5x - 15
16.0
10.0
ns
30
tRAC
RAS fall→D0 - 15 input
2.5x - 70
130
86
ns
31
tRAH
RAS fall→A0 - 15 Hold
0.5x - 15
16.0
10.0
ns
32
tRAS
RAS Low width
2.0x - 40
85.0
60.0
ns
33
tRP
RAS High width
2.0x - 40
85.0
60.0
ns
34
tRSH
CAS fall→RAS rise
1.0x - 35
28.0
15.0
ns
35
tRSC
RAS rise→CAS rise
0.5x - 25
6.0
0.0
ns
36
tRCD
RAS fall→CAS fall
1.0x - 40
23.0
100
ns
37
tCAC
CAS fall→D0 - 15 input
38
tCAS
CAS Low width
1.5x - 30
64.0
40.0
ns
39
tDS
D0 - 15 valid →CAS fall
0.5x - 15
16.0
10.0
ns
AC Measuring Conditions
• Output Level:
High 2.2V
(However CL = 100pF for AD0 ~
• Input Level:
High 2.4V
High 0.8Vcc
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1.5x - 65
29
10
ns
/Low 0.8V, CL50pF
AD15, AD0 ~ AD23, ALE, RD, WR, HWR, R/W, CLK, RAS, CAS0 ~ CAS2)
/Low 0.45V (AD0 ~ AD15)
/Low 0.2Vcc (Except for AD0 ~ AD15)
13/20
TMP96C041AF
(1) Read Cycle
14/20
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TMP96C041AF
(2) Write Cycle
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15/20
TMP96C041AF
4.4 A/D Conversion Characteristics (TMP96C041AF)
Vcc = 5V±10%, TA = -40 ~ 85°C (4 ~ 16MHz) TA = -20 ~ 70°C (4 ~ 20MHz)
Symbol
Parameter
Min
Typ
Max
VREF
Analog reference voltage
Vcc - 1.5
Vcc
AGND
Analog reference voltage
Vss
Vss
VAIN
Analog input voltage range
Vss
Vcc
IREF
Analog current for analog reference voltage
Error
4 ≤ fc ≤ 16MHz
(Quantize error of
±0.5 LSB not included)
16 ≤ fc ≤ 20MHz
TBD
1.5
High speed conversion mode
TBD
±4.0
Low speed conversion mode
TBD
±6.0
High speed conversion mode
TBD
±4.0
Low speed conversion mode
TBD
±8.0
Unit
V
mA
LSB
4.5 Serial Channel Timing - I/O Interface Mode
Vcc = 5V±10%, TA = -40 ~ 85°C (4 ~ 16MHz) TA = -20 ~ 70°C (4 ~ 20MHz)
(1) SCLK Input Mode
Variable
Symbol
16MHz
20MHz
Parameter
Unit
Min
Max
Min
Max
Min
Max
16x
1
0.8
µs
tSCY/2 - 5x - 50
137
100
ns
SCLK rising edge→Output Data hold
5x - 100
212
150
ns
SCLK rising edge→Input Data hold
0
0
0
ns
tSCY
SCLK cycle
tOSS
Output Data→Rising edge of SCLK
tOHS
tHSR
tSRD
SCLK rising edge→effective data input
tSCY - 5x - 100
587
450
ns
Vcc = 5V±10%, TA = -40 ~ 85°C (4 ~ 16MHz) TA = -20 ~ 70°C (4 ~ 20MHz)
(2) SCLK Output Mode
Variable
Symbol
16MHz
20MHz
Parameter
tSCY
SCLK cycle (programmable)
Unit
Min
Max
Min
Max
Min
Max
16x
8192x
1
512
0.8
409.6
µs
tOSS
Output Data→Rising edge of SCLK
tSCY - 2x - 150
725
550
ns
tOHS
SCLK rising edge→Output Data hold
2x - 80
45
20
ns
tHSR
SCLK rising edge→Input Data hold
0
0
0
ns
tSRD
SCLK rising edge→effective data input
tSCY - 2x - 150
725
550
ns
4.6 Timer/Counter Input Clock (TI0, TI4, TI5, TI6, TI7)
Vcc = 5V±10%, TA = -40 ~ 85°C (4 ~ 16MHz) TA = -20 ~ 70°C (4 ~ 20MHz)
Variable
Symbol
16MHz
20MHz
Parameter
Unit
Min
Max
Min
Max
Min
Max
tVCK
Clock cycle
8x + 100
600
500
ns
tVCKL
Low level clock pulse width
4x + 40
290
240
ns
tVCKH
High level clock pulse width
4x + 40
290
240
ns
16/20
TOSHIBA CORPORATION
TMP96C041AF
4.7 Interrupt Operation
Vcc = 5V±10%, TA = -40 ~ 85°C (4 ~ 16MHz) TA = -20 ~ 70°C (4 ~ 20MHz)
Variable
Symbol
16MHz
20MHz
Parameter
Unit
Min
Max
Min
Max
Min
Max
tINTAL
NMI, INT0 Low level pulse width
4x
250
200
ns
tINTAH
NMI, INT0 High level pulse width
4x
250
200
ns
tINTBL
INT4 ~ INT7 Low level pulse width
8x + 100
600
500
ns
tINTBH
INT4 ~ INT7 High level pulse width
8x + 100
600
500
ns
TOSHIBA CORPORATION
17/20
TMP96C041AF
4.8 Timing Chart for I/O Interface Mode
18/20
TOSHIBA CORPORATION
TMP96C041AF
4.9 Timing Chart for Bus Request (BUSRQ)/BUS Acknowledge (BUSAK)
Variable
Symbol
16MHz
20MHz
Parameter
Unit
Min
tBRC
BUSRQ setup time for CLK
Max
120
Min
Max
120
Min
Max
120
ns
tCBAL
CLK→BUSAK falling edge
1.5x + 120
245
220
ns
tCBAH
CLK→BUSAK rising edge
0.5x + 40
71
65
ns
tABA
Output buffer is off to BUSAK
0
80
0
80
0
80
ns
tBAA
BUSAK
0
80
0
80
0
80
ns
output buffer is on.
Note 1: The Bus will be released after the WAIT request is inactive, when the BUSRQ is set to “0” during “Wait” cycle.
Note 2: The internal programmable pull-up/pull-down resistance is added.
The internal programmable pull-up/pull-up resistance is added.
But the CS2/CAS2 pin does not have the internal programmable pull-up resistor. And in the condition of release, this pin is added the internal pull-up
resistor.
TOSHIBA CORPORATION
19/20
TMP96C041AF
5. Differences Between TMP96C141AF and
TMP96C041AF
Parameter
Internal RAM
The devices TMP96C141AF and TMP96C041AF have much
the same function, but they are different from following points.
TMP96C141AF
TMP96C041AF
1K byte
Does not exist
Pin condition at bus release
TMP96C141AF
see Figure 3.3
TMP96C041AF
see Figure 3.3
Mapping area of CS1 default setting
(B1C1/0: 00)
480H ~ 7FFFH
80H ~ 7FFFH
20/20
TOSHIBA CORPORATION