LCP1521S/LCP152DEE ® A.S.D.™ PROGRAMMABLE TRANSIENT VOLTAGE SUPPRESSOR FOR SLIC PROTECTION PRELIMINAY DATASHEET FEATURES ■ ■ ■ ■ ■ ■ ■ Dual programmable transient suppressor Wide negative firing voltage range: VMGL = -150 V max. Low dynamic switching voltages: VFP and VDGL Low gate triggering current: IGT = 5 mA max Peak pulse current: IPP = 30 A (10/1000 µs) Holding current: IH = 150 mA min Low space consuming package DESCRIPTION These devices have been especially designed to protect new high voltage, as well as classical SLICs, against transient overvoltages. Positive overvoltages are clamped by 2 diodes. Negative surges are suppressed by 2 thyristors, their breakdown voltage being referenced to -VBAT through the gate. These components present a very low gate triggering current (IGT) in order to reduce the current consumption on printed circuit board during the firing phase. A particular attention has been given to the internal wire bonding. The Kelvin method configuration ensures reliable protection, reducing the overvoltage introduced by the parasitic inductances of the wiring, especially for very fast transients. QFN 3x3 LCP152DEE SO-8 LCP1521S FUNCTIONAL DIAGRAM (LCP1521S) TIP TIP 1 GATE GND NC GND RING RING FUNCTIONAL DIAGRAM (LCP152DEE) BENEFITS Trisils are not subject to ageing and provide a fail safe mode in short circuit for a better protection. Trisils are used to help equipment to meet various standards such as UL1950, IEC950 / CSA C22.2, UL1459 and FCC part68. Trisils have UL94 V0 resin approved (Trisils are UL497B approved (file: E136224)). TIP GATE RING TIP GND NC RING TM: ASD is a trademark of STMicroelectronics January 2003 - Ed: 1A 1/9 LCP1521S/LCP152DEE IN COMPLIANCES WITH THE FOLLOWING STANDARDS STANDARD Peak Surge Voltage (V) Voltage Waveform Required peak current (A) Minimum serial Current resistor to meet Waveform standard (Ω) GR-1089 Core First level 2500 1000 2/10µs 10/1000µs 500 100 2/10µs 10/1000µs 10 24 GR-1089 Core Second level 5000 2/10µs 500 2/10µs 20 GR-1089 Core Intra-building 1500 2/10µs 100 2/10µs 0 ITU-T-K20/K21 6000 1500 10/700µs 150 37.5 5/310µs 110 0 ITU-T-K20 (IEC61000-4-2) 8000 15000 1/60 ns VDE0433 4000 2000 10/700µs 100 50 5/310µs 60 10 VDE0878 4000 2000 1.2/50µs 100 50 1/20µs 0 0 IEC61000-4-5 4000 4000 10/700µs 1.2/50µs 100 100 5/310µs 8/20µs 60 0 FCC Part 68, lightning surge type A 1500 800 10/160µs 10/560µs 200 100 10/160µs 10/560µs 22.5 15 FCC Part 68, lightning surge type B 1000 9/720µs 25 5/320µs 0 ESD contact discharge ESD air discharge 0 0 THERMAL RESISTANCE Symbol Rth (j-a) Parameter Junction to ambient Value Unit SO-8 130 °C/W QFN 3x3 170 ELECTRICAL CHARACTERISTICS (Tamb = 25°C) Symbol Parameter IGT Gate triggering current IH Holding current IRM Reverse leakage current LINE / GND IRG Reverse leakage current GATE / LINE VRM Reverse voltage LINE / GND VGT Gate triggering voltage VF VF IH Peak forward voltage LINE / GND Dynamic switching voltage GATE / LINE VGATE GATE / GND voltage 2/9 VRM Forward drop voltage LINE / GND VFP C VR IRM IR VDGL VRG I Reverse voltage GATE / LINE Capacitance LINE / GND IPP V LCP1521S/LCP152DEE ABSOLUTE RATINGS (Tamb = 25°C, unless otherwise specified). Symbol Parameter Value Unit 10/1000µs 8/20µs 10/560µs 5/310µs 10/160µs 1/20µs 2/10µs 30 100 35 40 50 100 170 A IPP Peak pulse current (see note1) ITSM Non repetitive surge peak on-state current (50Hz sinusoidal) t = 10ms t = 1s 10 3 A IGSM Maximum gate current (50Hz sinusoidal) t = 10ms 2 A VMLG VMGL Maximum voltage LINE/GND Maximum voltage GATE/LINE -40°C < Tamb < +85°C -40°C < Tamb < +85°C -150 -150 V Tstg Tj Storage temperature range Maximum junction temperature - 55 to + 150 150 °C TL Maximum lead temperature for soldering during 10s 260 °C Repetitive peak pulse current % IPP 100 tr: rise time (µs) tp: pulse duration (µs) ex: Pulse waveform 10/1000µs tr = 10µs tp = 1000µs 50 0 tr t tp 1- PARAMETERS RELATED TO THE DIODE LINE / GND (Tamb = 25°C) Symbol VF VFP (note 1) Test conditions IF = 5A 10/700µs 1.2/50µs 2/10µs t = 500µs 1.5kV 1.5kV 2.5kV RS = 10Ω RS = 10Ω RS = 62Ω Max Unit 2 V 5 9 30 V Note 1: see test circuit for VFP; RS is the protection resistor located on the line card. 3/9 LCP1521S/LCP152DEE 2 - PARAMETERS RELATED TO THE PROTECTION THYRISTOR (Tamb = 25°C unless otherwise specified) Symbol Test conditions Min Max Unit 5 mA IGT VGND / LINE = -48V 0.1 IH VGATE = -48V (note 2) 150 VGT at IGT IRG VRG = -150V VRG = -150V VDGL VGATE = -48V Tc=25°C Tc=85°C mA 2.5 V 5 50 µA 7 10 25 V (note 3) 10/700µs 1.2/50µs 2/10µs 1.5kV 1.5kV 2.5kV RS = 10Ω RS = 10Ω RS = 62Ω IPP = 30A IPP = 30A IPP = 38A Note 2: see functional holding current (IH) test circuit Note 3: see test circuit for VDGL The oscillations with a time duration lower than 50ns are not taken into account 3 - PARAMETERS RELATED TO DIODE AND PROTECTION THYRISTOR (Tamb = 25°C, unless otherwise specified) Symbol IRM C 4/9 Test conditions VGATE / LINE = -1V VGATE / LINE = -1V VRM = -150V VRM = -150V VR = 50V bias, VRMS = 1V, F = 1MHz VR = 2V bias, VRMS = 1V, F = 1MHz Typ. Tc=25°C Tc=85°C 15 35 Max. Unit 5 50 µA pF LCP1521S/LCP152DEE FUNCTIONAL HOLDING CURRENT (IH) TEST CIRCUIT : GO-NO GO TEST R Surge generator VBAT = - 100V D.U.T This is a GO-NO GO test which allows to confirm the holding current (IH) level in a functional test circuit. TEST PROCEDURE : - Adjust the current level at the IH value by short circuiting the D.U.T. - Fire the D.U.T. with a surge current : IPP = 10A, 10/1000µs. - The D.U.T. will come back to the off-state within a duration of 50ms max. TEST CIRCUIT FOR VFP AND VDGL PARAMETERS R4 (V is defined in unload condition) P TIP L R2 RING R3 VP R1 C1 C2 G ND Pulse (µs) Vp C1 C2 L R1 R2 R3 R4 IPP Rs tr tp (V) (µF) (nF) (µH) (Ω) (Ω) (Ω) (Ω) (A) (Ω) 10 700 1500 20 200 0 50 15 25 25 30 10 1.2 50 1500 1 33 0 76 13 25 25 30 10 2 10 2500 10 0 1.1 1.3 0 3 3 38 62 5/9 LCP1521S/LCP152DEE TECHNICAL INFORMATION Fig. A1: LCP152 concept behavior. Rs1 L1 TIP IG GND -Vbat V Tip ID1 T1 Th1 D1 Gate GND C Rs2 VRing RING L2 Figure A1 shows the classical protection circuit using the LCP152 crowbar concept. This topology has been developed to protect the new high voltage SLIC’s. It allows to program the negative firing threshold while the positive clamping value is fixed at GND. When a negative surge occurs on one wire (L1 for example) a current IG flows through the base of the transistor T1 and then injects a current in the gate of the thyristor Th1. Th1 fires and all the surge current flows through the ground. After the surge when the current flowing through Th1 becomes less negative than the holding current IH, then Th1 switches off. When a positive surge occurs on one wire (L1 for example) the diode D1 conducts and the surge current flows through the ground. To line side 220 nF Fig. A2: Example of PCB layout based on LCP152 protection. GND To SLIC side In order to minimize the remaining voltage across the SLIC inputs during the surge, the TIP and RING pins of the LCP152 are doubled (Pins 1 and 8 for TIP / Pins 4 and 5 for RING). This fact allows the board designer to connect the tracks like in figure A2. With such a PCB design, the extra voltages caused by track stray inductance remain located on the line side of the LCP and do not affects the SLIC side. The capacitor C is used to speed up the crowbar structure firing during the fast surge edges. This allows to minimize the dynamical breakover voltage at the SLIC Tip and Ring inputs during fast strikes. Note that this capacitor is generally present around the SLIC - Vbat pin. So to be efficient it has to be as close as possible from the LCP152 Gate pin and from the reference ground track (or plan) (see Fig. A2). The optimized value for C is 220nF. 6/9 LCP1521S/LCP152DEE The series resitors Rs1 and Rs2 designed in figure A1 represent the fuse resistors or the PTC which are mandatory to withstand the power contact or the power induction tests imposed by the various country standards. Taking into account this fact the actual lightning surge current flowing through the LCP is equal to: I surge = V surge / (Rg + Rs) With V surge = peak surge voltage imposed by the standard. Rg = series resistor of the surge generator Rs = series resistor of the line card (e.g. PTC) e.g. For a line card with 30Ω of series resistors which has to be qualified under GR1089 Core 1000V 10/1000µs surge, the actual current through the LCP152 is equal to: I surge = 1000 / (10 + 30) = 25A The LCP152 is particularly optimized for the new telecom applications such as the fiber in the loop, the WLL, the remote central office. In this case, the operating voltages are smaller than in the classical system. This makes the high voltage SLICs particularly suitable. The schematics of figure A3 gives the most frequent topology used for these applications. Fig. A3: Protection of high voltage SLIC. -Vbat Rs (*) TIP Gate Line GND TIP GND 220nF GND RING SLIC Rs (*) RING LCP152 Line card Rs (*) = PTC or Resitor fuse 7/9 LCP1521S/LCP152DEE Fig. 1: Surge peak current versus overload duration. Fig. 2: Relative variation of holding current versus junction temperature IH ( Tj ) / IH ( Tj=25°C ) 1.3 1.2 TO BE DEFINED 1.1 1 0.9 0.8 Tj ( °C ) 0.7 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 PACKAGE MECHANICAL DATA QFN 3x3 (6 Leads) DIMENSIONS REF. Millimetres Min. Typ. Max. Min. Typ. Max. A 0.80 1 0.031 0.040 A1 0 0.05 0 0.002 A2 0.65 A3 0.33 D 2.90 D2 1.92 E 2.90 E2 1.11 L 0.75 0.026 20 b e 3 0.787 3.10 0.114 0.118 0.122 3 0.037 0.45 0.008 < 0° 0.018 0.009 0.13 0.20 0.083 3.10 0.114 0.118 0.122 1.31 0.044 0.051 0.24 K 0.017 2.12 0.076 0.20 L2 0.030 0.43 0.013 0.95 L1 8/9 Inches 0.005 0.008 12° 0° 12° LCP1521S/LCP152DEE PACKAGE MECHANICAL DATA SO-8 (Plastic) DIMENSIONS REF. Millimetres Min. c1 a1 C a3 a2 A e b b1 a1 S E e3 Typ. Max. A L D M 0.1 a2 Typ. Max. 0.069 0.25 0.004 0.010 1.65 0.065 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.014 0.019 b1 0.19 C 0.25 0.50 0.25 0.007 0.010 0.50 0.010 0.020 45° (typ) 5 F 1 Min. 1.75 c1 8 Inches 4 D 4.8 5.0 0.189 0.197 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 F 3.8 4.0 0.15 0.157 L 0.4 1.27 0.016 0.050 0.6 0.024 M S 8° (max) Order code Marking Package Weight Base qty Delivery mode LCP1521S CP152S SO-8 0.08 g 100 Tube LCP1521SRL CP152S SO-8 0.08 g 2500 Tape & Reel LCP152DEERL CP15 QFN 3x3 0.022 g 3000 Tape & Reel Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 9/9