LCP1521S/LCP152DEE ASD (Application Specific Devices) Programmable transient voltage suppressor for SLIC protection Features ■ Dual programmable transient suppressor ■ Wide negative firing voltage range: VMGL = -150 V max. ■ Low dynamic switching voltages: VFP and VDGL ■ Low gate triggering current: IGT = 5 mA max ■ Peak pulse current: IPP = 30 A (10/1000 µs) ■ Holding current: IH = 150 mA min ■ Low space consuming package Order codes Description These devices have been especially designed to protect new high voltage, as well as classical SLICs, against transient overvoltages. Positive overvoltages are clamped by 2 diodes. Negative surges are suppressed by 2 thyristors, their breakdown voltage being referenced to -VBAT through the gate. Part Number Marking LCP1521S CP152S LCP1521SRL CP152S LCP152DEERL LCP152 Figure 1. LCP1521S Functional diagram TIP These components present a very low gate triggering current (IGT) in order to reduce the current consumption on printed circuit board during the firing phase. Benefits TRISILs™ are not subject to ageing and provide a fail safe mode in short circuit for a better level of protection. Trisils are used to ensure equipment meets various standards such as UL60950, IEC950 / CSA C22.2, UL1459 and FCC part 68. Trisils have UL94 V0 approved resin (Trisils are UL497B approved [file: E136224]). QFN 3x3 6 leads LCP152DEE SO-8 LCP1521S TIP 1 GATE GND NC GND RING RING Figure 2. LCP152DEE Functional diagram TIP GATE RING TIP GND NC RING TM: TRISIL is a trademark of STMicroelectronics July 2006 Rev 5 1/11 www.st.com 11 Characteristics 1 LCP1521S/LCP152DEE Characteristics Table 1. Standards compliance Peak surge voltage (V) Voltage waveform Required peak current (A) Current waveform Minimum serial resistor to meet standard (Ω) GR-1089 Core First level 2500 1000 2/10 µs 10/1000 µs 500 100 2/10 µs 10/1000 µs 12 24 GR-1089 Core Second level 5000 2/10 µs 500 2/10 µs 24 GR-1089 Core Intra-building 1500 2/10 µs 100 2/10 µs 0 ITU-T-K20/K21 6000 1500 10/700 µs 150 37.5 5/310 µs 110 0 ITU-T-K20 (IEC 61000-4-2) 8000 15000 1/60 ns VDE0433 4000 2000 10/700 µs 100 50 5/310 µs 60 10 VDE0878 4000 2000 1.2/50 µs 100 50 1/20 µs 0 0 IEC61000-4-5 4000 4000 10/700 µs 1.2/50 µs 100 100 5/310 µs 8/20 µs 60 0 FCC Part 68, lightning surge type A 1500 800 10/160 µs 10/560 µs 200 100 10/160 µs 10/560 µs 22.5 15 FCC Part 68, lightning surge type B 1000 9/720 µs 25 5/320 µs 0 Standard Table 2. 2/11 0 0 Thermal resistances Symbol Rth(j-a) ESD contact discharge ESD air discharge Parameter Junction to ambient Value SO-8 120 QFN 140 Unit ° C/W LCP1521S/LCP152DEE Table 3. Characteristics Electrical characteristics (Tamb = 25° C) Symbol Parameter I IGT Gate triggering current IH Holding current IRM Reverse leakage current LINE / GND IRG Reverse leakage current GATE / LINE VRM Reverse voltage LINE / GND VGT Gate triggering voltage VF Forward drop voltage LINE / GND VFP Peak forward voltage LINE / GND Dynamic switching voltage GATE / LINE VRG Reverse voltage GATE / LINE Table 4. VRM VF V IRM IR VDGL C VR IH IPP Capacitance LINE / GND Absolute ratings (Tamb = 25° C, unless otherwise specified) Symbol Value Unit Peak pulse current 10/1000 µs 8/20 µs 10/560 µs 5/310 µs 10/160 µs 1/20 µs 2/10 µs 30 100 35 40 50 100 150 A ITSM Non repetitive surge peak on-state current (50Hz sinusoidal) t = 20 ms t = 200 ms t=1s 18 10 7 A IGSM Maximum gate current (50Hz sinusoidal) t = 10 ms 2 A VMLG VMGL Maximum voltage LINE/GND Maximum voltage GATE/LINE -40° C < Tamb < +85° C -40° C < Tamb < +85° C -150 -150 V Tstg Tj Storage temperature range Maximum junction temperature -55 to +150 150 °C 260 °C IPP TL Table 5. Symbol tr tp Parameter Maximum lead temperature for soldering during 10 s. Repetitive peak pulse current Definition Rise time (µs) Pulse duration (µs) Example % IPP 100 Pulse waveform 10/1000 µs: tr = 10 µs tp = 1000 µs 50 0 tr tp t 3/11 Characteristics LCP1521S/LCP152DEE Table 6. Parameters related to the diode LINE / GND (Tamb = 25° C) Symbol VF VFP(1) 1. Test conditions IF = 5A 10/700 µs 1.2/50 µs 2/10 µs See test circuit for VFP Table 7. t = 500 µs RS = 10 Ω RS = 10 Ω RS = 62 Ω 1.5 kV 1.5 kV 2.5 kV Max Unit 3 V 5 9 30 V (Figure 4.): RS is the protection resistor located on the line card. Parameters related to the protection Thyristors (Tamb = 25° C, unless otherwise specified) Symbol Test conditions Typ Max Unit 5 mA IGT VGND / LINE = -48 V 0.1 IH VGATE = -48 V(1) 150 VGT at IGT IRG VRG = -150 V VRG = -150 V mA 2.5 V Tj = 25° C Tj = 85° C 5 50 µA IPP = 30 A IPP = 30 A IPP = 38 A 7 10 25 V VGATE = -48 V(2) VDGL 10/700 µs 1.2/50 µs 2/10 µs 1.5 kV 1.5 kV 2.5 kV 1. see functional holding current (IH) test circuit 2. see test circuit for VDG The oscillations with a time duration lower than 50ns are not taken into account. Table 8. Parameters related to diode and protection Thyristors (Tamb = 25° C, unless otherwise specified) Symbol IRM C 4/11 RS = 10 Ω RS = 10 Ω RS = 62 Ω Test conditions VGATE / LINE = -1 V VGATE / LINE = -1 V VRM = -150 V VRM = -150 V VR = 50 V bias, VRMS = 1 V, F = 1 MHz VR = 2 V bias, VRMS = 1 V, F = 1 MHz Typ Tj = 25° C Tj = 85° C 15 35 Max Unit 5 50 µA pF LCP1521S/LCP152DEE Figure 3. Characteristics Functional Holding Current (IH) test circuit: GO-NO GO test R Surge generator VBAT = - 100V D.U.T This is a GO-NO GO test which allows to confirm the holding current (IH) level in a functional test circuit. TEST PROCEDURE: - Adjust the current level at the IH value by short circuiting the D.U.T. - Fire the D.U.T. with a surge current: IPP = 10A, 10/1000µs - The D.U.T. will come back to the off-state within a duration of 50ms max. Test circuit for VFP and VDGL parameters Figure 4. R4 (V is defined in unload condition) P TIP L R2 RING R3 VP R1 C1 C2 G ND Pulse (µs) Vp C1 C2 L R1 R2 R3 R4 IPP Rs tr tp (V) (µF) (nF) (µH) (Ω) (Ω) (Ω) (Ω) (A) (Ω) 10 700 1500 20 200 0 50 15 25 25 30 10 1.2 50 1500 1 33 0 76 13 25 25 30 10 2 10 2500 10 0 1.1 1.3 0 3 3 38 62 5/11 Technical information 2 LCP1521S/LCP152DEE Technical information Figure 5. LCP152 concept behavior Rs1 L1 TIP GND -Vbat V Tip ID1 IG T1 Th1 D1 Gate GND C Rs2 VRing RING L2 Figure 5. shows the classical protection circuit using the LCP152 crowbar concept. This topology has been developed to protect the new high voltage SLICs. It allows to program the negative firing threshold while the positive clamping value is fixed at GND. When a negative surge occurs on one wire (L1 for example) a current IG flows through the base of the transistor T1 and then injects a current in the gate of the thyristor Th1. Th1 fires and all the surge current flows through the ground. After the surge when the current flowing through Th1 becomes less negative than the holding current IH, then Th1 switches off. When a positive surge occurs on one wire (L1 for example) the diode D1 conducts and the surge current flows through the ground. Figure 6. Example of PCB layout based on LCP152S protection To line side 220 nF LCP1521S GND To SLIC side Figure 6. shows the classical PCB layout used to optimize line protection. The capacitor C is used to speed up the crowbar structure firing during the fast surge edges. This allows to minimize the dynamical breakover voltage at the SLIC Tip and Ring inputs during fast strikes. Note that this capacitor is generally present around the SLIC - Vbat pin. So to be efficient it has to be as close as possible from the LCP152 Gate pin and from the reference ground track (or plan) (see Figure 6.). The optimized value for C is 220 nF. The series resitors Rs1 and Rs2 designed in Figure 5. represent the fuse resistors or the PTC which are mandatory to withstand the power contact or the power induction tests 6/11 LCP1521S/LCP152DEE Technical information imposed by the various country standards. Taking into account this fact the actual lightning surge current flowing through the LCP is equal to: I surge = V surge / (Rg + Rs) With: V surge = peak surge voltage imposed by the standard. Rg = series resistor of the surge generator Rs = series resistor of the line card (e.g. PTC) e.g. For a line card with 30 Ω of series resistors which has to be qualified under GR1089 Core 1000V 10/1000 µs surge, the actual current through the LCP152 is equal to: I surge = 1000 / (10 + 30) = 25 A The LCP152 is particularly optimized for the new telecom applications such as the fiber in the loop, the WLL, the remote central office. In this case, the operating voltages are smaller than in the classical system. This makes the high voltage SLICs particularly suitable. The schematics of Figure 7. give the most frequent topology used for these applications. Figure 7. Protection of high voltage SLIC -Vbat Rs (*) TIP Gate Line TIP GND 220nF GND GND SLIC RING Rs (*) RING LCP152xx Line card Rs (*) = PTC or fuse resistor Figure 8. Surge peak current versus overload Figure 9. duration ITSM(A) Relative variation of holding current versus junction temperature IH[Tj] / IH[Tj=25°C] 1.3 24 F=50Hz Tj initial=25°C 1.2 20 1.1 16 1 12 0.9 8 0.8 Tj(°C) 4 0.7 -40 t(s) -30 -20 -10 0 10 20 30 40 50 60 70 80 90 0 1.E-02 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 7/11 Package information 3 LCP1521S/LCP152DEE Package information Table 9. SO-8 Dimensions Dimensions Ref. Millimeters Min. Typ. A C (Seating Plane) ccc C A2 0.25mm (Gage Plane) C k D 5 E1 1 Typ. 1.75 A1 0.1 A2 1.25 Max. 0.069 0.25 0.004 0.010 0.049 E 4 b 0.28 0.48 0.011 0.019 C 0.17 0.23 0.007 0.009 D 4.80 4.90 5.00 0.189 0.193 0.197 E 5.80 6.00 6.20 0.228 0.236 0.244 E1 3.80 3.90 4.00 0.150 0.154 0.157 e 1.27 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 8 0 k° ccc Figure 10. Footprint (dimensions in mm) 0.050 h L1 8/11 Min. h x 45° L1 8 Max. L A1 e b A Inches 1.04 0 0.041 0.10 8 0.004 LCP1521S/LCP152DEE Table 10. Package information QFN 3x3 6 Leads Package dimensions DIMENSIONS Millimeters REF. Min. Typ. Inches Max. Min. Typ. Max. A 0.80 1 0.031 0.040 A1 0 0.05 0 0.002 A2 0.65 0.75 0.026 0.030 A3 20 b 0.33 D 2.90 D2 1.92 E 2.90 E2 1.11 e L 3 3 0.787 0.43 0.013 3.10 0.114 0.118 0.122 2.12 0.076 3.10 0.114 0.118 0.122 1.31 0.044 0.95 0.20 L1 < 0° 0.018 0.009 0.13 0.20 0.051 0.008 0.24 K 0.083 0.037 0.45 L2 0.017 0.005 0.008 12° 0° 12° Figure 11. QFN 3x3 6 Leads Footprint dimensions (in mm) 0.95 0.48 1.05 0.35 1.21 0.34 2.02 4.00 9/11 Ordering information 4 LCP1521S/LCP152DEE Ordering information Part Number Marking LCP1521S CP152S LCP1521SRL (1) Package Weight SO-8 0.11 g CP152S LCP152DEERL(1) LCP152 QFN 3x3 6L 0.022 g Base qty Delivery mode 100 Tube 2500 Tape and reel 3000 Tape and reel 1. Preferred device 5 10/11 Revision history Date Revision Description of Changes Sep-2003 1A 08-Dec-2004 2 1/ Page 2 table 3: Thermal resistances changed from 130° C/W (SO-8) to 120° C/W and from 170° C/W (QFN) to 140° C/W. 2/ SO-8 and QFN footprint dimensions added. 17-Feb-2005 3 Table 9 on page 4: correction of typo on capacitance unit. 03-May-2005 4 Table 5 on page 3: ITSM value @ t= 1s from 4 A to 4.5 A. 07-Jul-2006 5 Replaced QFN package illustration on page 1. Reformatted document to current layout standard. Values of ITSM modified in Table 4. SO-8 package dimensions updated in Table 9. First issue. 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