STMICROELECTRONICS LCDP1521

LCDP1521
®
DUAL LINE PROGRAMMABLE TRANSIENT VOLTAGE
SUPPRESSOR FOR SLIC PROTECTION
A.S.D.™
FEATURES
■
■
■
■
■
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Dual line programmable transient voltage
suppressor
Wide negative firing voltage range:
VMGL = -150 V max.
Low dynamic switching voltages: VFP and VDGL
Low gate triggering current: IGT = 5 mA max
Peak pulse current: IPP = 15 A (10/1000 µs)
Holding current: IH = 150 mA min
DESCRIPTION
This device has been especially designed to
protect 2 new high voltage, as well as classical
SLICs, against transient overvoltages.
Positive overvoltages are clamped by 2 diodes.
Negative surges are suppressed by 2 thyristors,
their breakdown voltage being referenced to -VBAT
through the gate.
This component presents a very low gate
triggering current (IGT) in order to reduce the current consumption on printed circuit board during
the firing phase.
BENEFITS
Trisils are not subject to ageing and provide a fail
safe mode in short circuit for a better protection.
Trisils are used to help equipment to meet various
standards such as UL1950, IEC950 / CSA C22.2,
UL1459 and FCC part68. Trisils have UL94 V0
resin approved (Trisils are UL497B approved (file:
E136224)).
March 2002 - Ed: 1A
SO-8
FUNCTIONAL DIAGRAM
TIP 1 1
8 RING 1
GATE 2
7 GND
GATE 3
6 GND
TIP 2 4
5 RING 2
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LCDP1521
IN COMPLIANCES WITH THE FOLLOWING STANDARDS
STANDARD
Peak Surge
Voltage
(V)
Voltage
Waveform
Required
peak current
(A)
Minimum serial
Current
resistor to meet
Waveform
standard (Ω)
GR-1089 Core
First level
2500
1000
2/10µs
10/1000µs
500
100
2/10µs
10/1000µs
31
57
GR-1089 Core
Second level
5000
2/10µs
500
2/10µs
62
GR-1089 Core
Intra-building
1500
2/10µs
100
2/10µs
7
ITU-T-K20/K21
6000
1500
10/700µs
150
37.5
5/310µs
200
20
ITU-T-K20
(IEC61000-4-2)
8000
15000
1/60 ns
VDE0433
4000
2000
10/700µs
100
50
5/310µs
120
40
VDE0878
4000
2000
1.2/50µs
100
50
1/20µs
27
0
IEC61000-4-5
4000
4000
10/700µs
1.2/50µs
100
100
5/310µs
8/20µs
120
27
FCC Part 68, lightning
surge type A
1500
800
10/160µs
10/560µs
200
100
10/160µs
10/560µs
43
32
FCC Part 68, lightning
surge type B
1000
9/720µs
25
5/320µs
0
ESD contact discharge
ESD air discharge
0
0
THERMAL RESISTANCE
Symbol
Rth (j-a)
Parameter
Junction to ambient
Value
Unit
170
°C/W
ELECTRICAL CHARACTERISTICS (Tamb = 25°C)
Symbol
Parameter
IGT
Gate triggering current
IH
Holding current
IRM
Reverse leakage current LINE / GND
IRG
Reverse leakage current GATE / LINE
VRM
Reverse voltage LINE / GND
VGT
Gate triggering voltage
VF
VF
IH
Peak forward voltage LINE / GND
Dynamic switching voltage GATE / LINE
VGATE
GATE / GND voltage
2/8
VRM
Forward drop voltage LINE / GND
VFP
C
VR
IRM
IR
VDGL
VRG
I
Reverse voltage GATE / LINE
Capacitance LINE / GND
IPP
V
LCDP1521
ABSOLUTE RATINGS (Tamb = 25°C, unless otherwise specified).
Symbol
Parameter
Value
Unit
10/1000µs
8/20µs
10/560µs
5/310µs
10/160µs
1/20µs
2/10µs
15
60
20
25
30
60
70
A
t = 10ms
t = 1s
5
3.5
A
I t value for fusing
(50Hz sinusoidal)
t = 10ms
0.125
A2s
IGSM
Maximum gate current
(50Hz sinusoidal)
t = 10ms
2
A
VMLG
VMGL
Maximum voltage LINE/GND
Maximum voltage GATE/LINE
-40°C < Tamb < +85°C
-40°C < Tamb < +85°C
-150
-150
V
Tstg
Tj
Storage temperature range
Maximum junction temperature
- 55 to + 150
150
°C
TL
Maximum lead temperature for soldering during 10s
260
°C
IPP
Peak pulse current (see note1)
ITSM
Non repetitive surge peak on-state
current
(50Hz sinusoidal)
I2t
2
Repetitive peak pulse current
% IPP
100
tr: rise time (µs)
tp: pulse duration (µs)
ex: Pulse waveform 10/1000µs
tr = 10µs tp = 1000µs
50
0
tr
t
tp
PARAMETERS RELATED TO THE DIODE LINE / GND (Tamb = 25°C)
Symbol
VF
VFP
(note 1)
Test conditions
IF = 1A
10/700µs
1.2/50µs
2/10µs
t = 500µs
1.5kV
1.5kV
2.5kV
RS = 110Ω
RS = 60Ω
RS = 245Ω
IPP = 10A
IPP = 15A
IPP = 10A
Max
Unit
2
V
5
10
20
V
Note 1: see test circuit for VFP; RS is the protection resistor located on the line card.
3/8
LCDP1521
PARAMETERS RELATED TO THE PROTECTION THYRISTOR (Tamb = 25°C unless otherwise specified)
Symbol
Test conditions
Min
Max
Unit
5
mA
IGT
VGND / LINE = -48V
0.1
IH
VGATE = -48V (note 2)
150
VGT
at IGT
IRG
VRG = -150V
VRG = -150V
VDGL
VGATE = -48V
Tc=25°C
Tc=85°C
mA
2.5
V
5
50
µA
5
10
20
V
(note 3)
10/700µs
1.2/50µs
2/10µs
1.5kV
1.5kV
2.5kV
RS = 110Ω
RS = 60Ω
RS = 245Ω
IPP = 10A
IPP = 15A
IPP = 10A
Note 2: see functional holding current (IH) test circuit
Note 3: see test circuit for VDGL
The oscillations with a time duration lower than 50ns are not taken into account
PARAMETERS RELATED TO DIODE AND PROTECTION THYRISTOR (Tamb = 25°C, unless otherwise
specified)
Symbol
IRM
C
4/8
Test conditions
VGATE / LINE = -1V
VGATE / LINE = -1V
VRM = -150V
VRM = -150V
VR = 50V bias, VRMS = 1V, F = 1MHz
VR = 2V bias, VRMS = 1V, F = 1MHz
Typ.
Tc=25°C
Tc=85°C
20
48
Max.
Unit
5
50
µA
pF
LCDP1521
FUNCTIONAL HOLDING CURRENT (IH) TEST CIRCUIT : GO-NO GO TEST
R
Surge generator
VBAT = - 100V
D.U.T
This is a GO-NO GO test which allows to confirm the holding current (IH) level in a functional test circuit.
TEST PROCEDURE :
- Adjust the current level at the IH value by short circuiting the D.U.T.
- Fire the D.U.T. with a surge current : IPP = 10A, 10/1000µs.
- The D.U.T. will come back to the off-state within a duration of 50ms max.
TEST CIRCUIT FOR VFP AND VDGL PARAMETERS
R4
(VP is defined in unload condition)
TIP
L
R2
RING
R3
VP
R1
C1
C2
GND
Pulse (µs)
Vp
C1
C2
L
R1
R2
R3
R4
IPP
Rs
tr
tp
(V)
(µF)
(nF)
(µH)
(Ω)
(Ω)
(Ω)
(Ω)
(A)
(Ω)
10
700
1500
20
200
0
50
15
25
25
10
110
1.2
50
1500
1
33
0
76
13
25
25
15
60
2
10
2500
10
0
1.1
1.3
0
3
3
10
245
5/8
LCDP1521
TECHNICAL INFORMATION
Fig. A1: LCDP1521 concept behavior.
Rs1
L1
TIP
IG
GND
-Vbat
V Tip
ID1
T1
Th1
D1
Gate
GND
C
Rs2
RING
VRing
L2
Figure A1 shows the classical protection circuit using the LCDP1521 crowbar concept. This topology has been developed to protect the new high voltage SLICs. It allows to program the negative
firing threshold while the positive clamping value is fixed at GND.
When a negative surge occurs on one wire (L1 for example), a current IG flows through the base of the
transistor T1 and then injects a current in the gate of the thyristor Th1. Th1 fires and all the surge current
flows through the ground. After the surge when the current flowing through Th1 becomes less negative
than the holding current IH, then Th1 switches off.
When a positive surge occurs on one wire (L1 for example), the diode D1 conducts and the surge current
flows through the ground.
The capacitor C is used to speed up the crowbar structure firing during the fast surge edges.
This allows to minimize the dynamical breakover voltage at the SLIC Tip and Ring inputs during fast
strikes. Note that this capacitor is generally present around the SLIC - Vbat pin.
So to be efficient it has to be as close as possible from the LCDP1521 Gate pin and from the reference
ground track (or plan). The optimized value for C is 220nF.
The series resitors Rs1 and Rs2 designed in figure A1 represent the fuse resistors or the PTC which are
mandatory to withstand the power contact or the power induction tests imposed by the various country
standards. Taking into account this fact the actual lightning surge current flowing through the LCDP is
equal to:
I surge = V surge / (Rg + Rs)
With
V surge = peak surge voltage imposed by the standard.
Rg = series resistor of the surge generator
Rs = series resistor of the line card (equivalent to PTC + R on Fig. A2)
e.g. For a line card with 60Ω of series resistors which has to be qualified under GR1089 Core 1000V
10/1000µs surge, the actual current through the LCDP1521 is equal to:
I surge = 1000 / (10 + 60) = 14A
The LCDP1521 is particularly optimized for the new telecom applications such as the fiber in the loop,
the WLL, the remote central office. In this case, the operating voltages are smaller than in the classical
system. This makes the high voltage SLICs particularly suitable. The schematics of figure A2 gives the
most frequent topology used for these applications.
6/8
LCDP1521
Fig. A2: Protection of high voltage SLICs.
-Vbat
PTC or Fuse
LCDPxxxx
TIP
Ring relay 1
R
Line 1
SLIC 1
R
PTC or Fuse
RING
R
Ring relay 2
PTC or Fuse
Line 2
SLIC 2
R
PTC or Fuse
Fig. 1: Surge peak current versus overload duration.
Fig. 2: Relative variation of holding current versus
junction temperature
ITSM(A)
IH ( Tj ) / IH ( Tj=25°C )
7
1.3
F=50Hz
Tj initial=25°C
6
1.2
5
1.1
4
1
3
0.9
2
0.8
1
Tj ( °C )
t(s)
0
0.01
0.10
1.00
10.00
100.00
1000.00
0.7
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90
ORDER CODE
LCDP
LINE CARD
DUAL PROTECTION
15
2
1
RL
PACKAGE
1 : SO-8
IH = 150 mA
VERSION
RL : Tape & Reel
: Tube
7/8
LCDP1521
PACKAGE MECHANICAL DATA
SO-8 (Plastic)
DIMENSIONS
REF.
Millimetres
Min.
A
L
c1
a1
C
a3
a2
A
e
b
b1
a1
S
0.1
a2
D
M
Typ. Max.
1.75
0.069
0.25 0.004
0.010
1.65
0.065
a3
0.65
0.85 0.025
0.033
b
0.35
0.48 0.014
0.019
b1
0.19
C
0.25
0.50
c1
5
F
1
Min.
E
e3
8
Inches
Typ. Max.
4
0.25 0.007
0.010
0.50 0.010
0.020
45° (typ)
D
4.8
5.0
0.189
0.197
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
3.81
0.150
F
3.8
4.0
0.15
0.157
L
0.4
1.27 0.016
0.050
0.6
0.024
M
S
8° (max)
Order code
Marking
Package
Weight
Base qty
Delivery mode
LCDP1521
CDP152
SO-8
0.08 g
100
Tube
LCDP1521RL
CDP152
SO-8
0.08 g
2500
Tape & Reel
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use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied.
STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written
approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 2002 STMicroelectronics - Printed in Italy - All rights reserved.
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