2SJ384 L , 2SJ384 S Silicon P-Channel MOS FET Application LDPAK High speed power switching 4 Features 1 • • • • Low on–resistance High speed switching Low drive current 2.5 V gate drive device can be driven from 3 V source • Suitable for Switching regulator, DC – DC converter • Avalanche Ratings 2 4 3 1 2, 4 2 3 1 1. Gate 2. Drain 3. Source 4. Drain 3 Table 1 Absolute Maximum Ratings (Ta = 25°C) Item Symbol Ratings Unit ——————————————————————————————————————————— Drain to source voltage VDSS –60 V ——————————————————————————————————————————— Gate to source voltage VGSS ±20 V ——————————————————————————————————————————— Drain current ID –15 A ——————————————————————————————————————————— Drain peak current ID(pulse)* –60 A ——————————————————————————————————————————— Body–drain diode reverse drain current IDR –15 A ——————————————————————————————————————————— Avalanche current IAP*** –15 A ——————————————————————————————————————————— Avalanche energy EAR*** 19 mJ ——————————————————————————————————————————— Channel dissipation Pch** 50 W ——————————————————————————————————————————— Channel temperature Tch 150 °C ——————————————————————————————————————————— Storage temperature Tstg –55 to +150 °C ——————————————————————————————————————————— * PW ≤ 10 µs, duty cycle ≤ 1 % ** Value at Tc = 25 °C *** Value at Tch = 25 °C, Rg ≥ 50 Ω 2SJ384 L , 2SJ384 S Table 2 Electrical Characteristics (Ta = 25°C) Item Symbol Min Typ Max Unit Test conditions ———————————————————————————————————————————– Drain to source breakdown voltage V(BR)DSS –60 — — V ID = –10 mA, VGS = 0 ———————————————————————————————————————————– Gate to source breakdown voltage V(BR)GSS ±20 — — V IG = ±100 µA, VDS = 0 ———————————————————————————————————————————– Gate to source leak current IGSS — — ±10 µA VGS = ±16 V, VDS = 0 ———————————————————————————————————————————– Zero gate voltage drain current IDSS — — –250 µA VDS = –50 V, VGS = 0 ———————————————————————————————————————————– Gate to source cutoff voltage VGS(off) –0.5 — –1.5 V ID = –1 mA, VDS = –10 V ———————————————————————————————————————————– Static drain to source on state resistance RDS(on) — 0.07 0.01 Ω ID = –8 A VGS = –10 V * ————————————————————————– — 0.12 0.19 Ω ID = –3 A VGS = –2.5 V * ———————————————————————————————————————————– Forward transfer admittance |yfs| 8 14 — S ID = –8 A VDS = –10 V * ———————————————————————————————————————————– Input capacitance Ciss — 2170 — pF VDS = –10 V ———————————————————————————————— Output capacitance Coss — 830 — pF VGS = 0 ———————————————————————————————— Reverse transfer capacitance Crss — 130 — pF f = 1 MHz ———————————————————————————————————————————– Turn–on delay time td(on) — 16 — ns ID = –8 A ———————————————————————————————— Rise time tr — 75 — ns ———————————————————————————————— Turn–off delay time td(off) — 360 — ns VGS = –10 V RL = 3.75 Ω ———————————————————————————————— Fall time tf — 180 — ns ———————————————————————————————————————————– Body–drain diode forward voltage VDF — –1.0 — V IF = –15 A, VGS = 0 ———————————————————————————————————————————– Body–drain diode reverse recovery time trr — 130 — ns IF = –15 A, VGS = 0, diF / dt = 50 A / µs ———————————————————————————————————————————– * Pulse Test 2SJ384 L , 2SJ384 S Power vs. Temperature Derating –200 I D (A) 60 40 20 50 100 Case Temperature 10 –20 –10 DC –5 PW Op 0µ s =1 era 1m s 0m s( 1s tio Operation in n( ho Tc t) –2 this area is =2 5° limited by R DS(on) C) –1 150 200 –0.2 –1 Tc (°C) Typical Output Characteristics Pulse Test V DS = –10 V Pulse Test (A) –2.5 V –12 –8 –2 V –4 –16 –12 –8 –4 VGS = –1.5 V 0 –2 –4 –6 Drain to Source Voltage –8 –10 V DS (V) –2 –5 –10 –20 –50 –100 Drain to Source Voltage V DS (V) Typical Transfer Characteristics ID –16 –10 V –4 V –3 V Ta = 25 °C –20 Drain Current –20 I D (A) 10 µs –50 –0.5 0 Drain Current Maximum Safe Operation Area –100 Drain Current Channel Dissipation Pch (W) 80 Tc = –25 °C 25 °C 75 °C 0 –2 –4 –6 Gate to Source Voltage –8 –10 V GS (V) 2SJ384 L , 2SJ384 S Pulse Test I D = –10 A –0.8 –0.6 –5 A –0.4 –0.2 Static Drain to Source on State Resistance R DS(on) ( Ω) 0 –2 A –2 –4 –6 Gate to Source Voltage VGS = –2.5 V –4 V 0.1 0.3 I D = –10 A –2 A –5 A VGS = –2.5 V 0.1 –2, –5, –10 A –10 V 0 40 80 120 160 Case Temperature Tc (°C) –10 V 0.01 –0.5 –10 V GS (V) 0.4 0 –40 0.2 0.02 –8 Static Drain to Source on State Resistance vs. Temperature 0.5 Pulse Test 0.2 Static Drain to Source on State Resistance vs. Drain Current 1 Pulse Test 0.5 0.05 –1 –2 –5 –10 –20 Drain Current I D (A) –50 Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |y fs | (S) V DS(on) (V) –1.0 Drain to Source On State Resistance R DS(on) ( Ω ) Drain to Source Saturation Voltage vs. Gate to Source Voltage 50 20 Tc = –25 °C 25 °C 10 5 75 °C 2 1 0.5 –0.1 –0.3 V DS = –10 V Pulse Test –1 –3 –10 –30 Drain Current I D (A) –100 2SJ384 L , 2SJ384 S Typical Capacitance vs. Drain to Source Voltage Body–Drain Diode Reverse Recovery Time 10000 Capacitance C (pF) Reverse Recovery Time trr (ns) 500 200 100 50 20 10 V DD = –50 V –25 V –10 V –80 –100 0 –8 V GS (V) –12 –16 I D = –15 A 80 20 40 60 Gate Charge Qg (nc) VGS = 0 f = 1 MHz –10 1000 –20 100 500 Switching Time t (ns) –60 –4 V GS Crss 100 –20 –30 –40 –50 Switching Characteristics 0 V DS 300 Drain to Source Voltage V DS (V) Gate to Source Voltage V DS (V) Drain to Source Voltage –40 Coss 0 Dynamic Input Characteristics –20 1000 10 5 –0.1 –0.3 –1 –3 –10 –30 –100 Reverse Drain Current I DR (A) V DD = –10 V –25 V –50 V Ciss 30 di / dt = 50 A / µs VGS = 0, Ta = 25 °C 0 3000 V GS = –10 V, V DD = –30 V PW = 5 µs, duty < 1 % t d(off) 200 tf 100 50 tr t d(on) 20 10 –0.05 –0.1 –0.3 –1 –3 Drain Current –10 I D (A) –30 –50 2SJ384 L , 2SJ384 S Reverse Drain Current vs. Source to Drain Voltage Maximun Avalanche Energy vs. Channel Temperature Derating Repetive Avalanche Energy E AR (mJ) –20 Reverse Drain Current I DR (A) Pulse Test –16 –12 –10 V V GS = 0, 5 V –5 V –8 –4 0 –0.4 –0.8 –1.2 Source to Drain Voltage –1.6 –2.0 20 I AP = –15 A V DD = –25 V duty < 0.1 % Rg > 50 Ω 16 12 8 4 0 25 V SD (V) 50 75 100 125 150 Channel Temperature Tch (°C) Avalanche Test Circuit and Waveform V DS Monitor EAR = L 1 2 • L • I AP • 2 I AP Monitor VDSS VDSS – V DD V (BR)DSS I AP Rg D. U. T V DS VDD ID Vin –15 V 50Ω 0 VDD 2SJ384 L , 2SJ384 S Normalized Transient Thermal Impedance vs. Pulse Width Normalized Transient Thermal Impedance γ s (t) 3 Tc = 25°C 1 D=1 0.5 0.3 0.2 0.1 θ ch – c(t) = γ s (t) • θ ch – c θ ch – c = 2.5 °C/W, Tc = 25 °C 0.1 0.05 0.03 PDM 0.02 1 lse 0.0 t pu o h 1s 0.01 10 µ D= PW T PW T 100 µ 1m 10 m Pulse Width 100 m 10 PW (S) Switching Time Test Circuit Waveforms Vout Monitor Vin Monitor 1 Vin 10% D.U.T. RL 90% Vin –10 V 50Ω V DD = 30 V 90% 90% Vout td(on) 10% 10% tr td(off) tf